[J-u-boot.git] / drivers / spi / pic32_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Microchip PIC32 SPI controller driver.
 *
 * Copyright (c) 2015, Microchip Technology Inc.
 *      Purna Chandra Mandal <[email protected]>
 */

#include <clk.h>
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compat.h>
#include <malloc.h>
#include <spi.h>

#include <asm/types.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dt-bindings/clock/microchip,clock.h>
#include <mach/pic32.h>

DECLARE_GLOBAL_DATA_PTR;

/* PIC32 SPI controller registers */
struct pic32_reg_spi {
	struct pic32_reg_atomic ctrl;
	struct pic32_reg_atomic status;
	struct pic32_reg_atomic buf;
	struct pic32_reg_atomic baud;
	struct pic32_reg_atomic ctrl2;
};

/* Bit fields in SPI Control Register */
#define PIC32_SPI_CTRL_MSTEN	BIT(5) /* Enable SPI Master */
#define PIC32_SPI_CTRL_CKP	BIT(6) /* active low */
#define PIC32_SPI_CTRL_CKE	BIT(8) /* Tx on falling edge */
#define PIC32_SPI_CTRL_SMP	BIT(9) /* Rx at middle or end of tx */
#define PIC32_SPI_CTRL_BPW_MASK	0x03   /* Bits per word */
#define  PIC32_SPI_CTRL_BPW_8		0x0
#define  PIC32_SPI_CTRL_BPW_16		0x1
#define  PIC32_SPI_CTRL_BPW_32		0x2
#define PIC32_SPI_CTRL_BPW_SHIFT	10
#define PIC32_SPI_CTRL_ON	BIT(15) /* Macro enable */
#define PIC32_SPI_CTRL_ENHBUF	BIT(16) /* Enable enhanced buffering */
#define PIC32_SPI_CTRL_MCLKSEL	BIT(23) /* Select SPI Clock src */
#define PIC32_SPI_CTRL_MSSEN	BIT(28) /* SPI macro will drive SS */
#define PIC32_SPI_CTRL_FRMEN	BIT(31) /* Enable framing mode */

/* Bit fields in SPI Status Register */
#define PIC32_SPI_STAT_RX_OV		BIT(6) /* err, s/w needs to clear */
#define PIC32_SPI_STAT_TF_LVL_MASK	0x1f
#define PIC32_SPI_STAT_TF_LVL_SHIFT	16
#define PIC32_SPI_STAT_RF_LVL_MASK	0x1f
#define PIC32_SPI_STAT_RF_LVL_SHIFT	24

/* Bit fields in SPI Baud Register */
#define PIC32_SPI_BAUD_MASK	0x1ff

struct pic32_spi_priv {
	struct pic32_reg_spi	*regs;
	u32			fifo_depth; /* FIFO depth in bytes */
	u32			fifo_n_word; /* FIFO depth in words */
	struct gpio_desc	cs_gpio;

	/* Current SPI slave specific */
	ulong			clk_rate;
	u32			speed_hz; /* spi-clk rate */
	int			mode;

	/* Current message/transfer state */
	const void		*tx;
	const void		*tx_end;
	const void		*rx;
	const void		*rx_end;
	u32			len;

	/* SPI FiFo accessor */
	void (*rx_fifo)(struct pic32_spi_priv *);
	void (*tx_fifo)(struct pic32_spi_priv *);
};

static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
{
	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
}

static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
{
	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
}

static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
{
	u32 sr = readl(&priv->regs->status.raw);

	return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
}

static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
{
	u32 sr = readl(&priv->regs->status.raw);

	return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
}

/* Return the max entries we can fill into tx fifo */
static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
{
	u32 tx_left, tx_room, rxtx_gap;

	tx_left = (priv->tx_end - priv->tx) / n_bytes;
	tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);

	rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
	rxtx_gap /= n_bytes;
	return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
}

/* Return the max entries we should read out of rx fifo */
static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
{
	u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;

	return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
}

#define BUILD_SPI_FIFO_RW(__name, __type, __bwl)		\
static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv)	\
{								\
	__type val;						\
	u32 mx = pic32_rx_max(priv, sizeof(__type));		\
								\
	for (; mx; mx--) {					\
		val = read##__bwl(&priv->regs->buf.raw);	\
		if (priv->rx_end - priv->len)			\
			*(__type *)(priv->rx) = val;		\
		priv->rx += sizeof(__type);			\
	}							\
}								\
								\
static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv)	\
{								\
	__type val;						\
	u32 mx = pic32_tx_max(priv, sizeof(__type));		\
								\
	for (; mx ; mx--) {					\
		val = (__type) ~0U;				\
		if (priv->tx_end - priv->len)			\
			val =  *(__type *)(priv->tx);		\
		write##__bwl(val, &priv->regs->buf.raw);	\
		priv->tx += sizeof(__type);			\
	}							\
}
BUILD_SPI_FIFO_RW(byte, u8, b);
BUILD_SPI_FIFO_RW(word, u16, w);
BUILD_SPI_FIFO_RW(dword, u32, l);

static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
				   unsigned int wordlen)
{
	u32 bits_per_word;
	u32 val;

	switch (wordlen) {
	case 8:
		priv->rx_fifo = pic32_spi_rx_byte;
		priv->tx_fifo = pic32_spi_tx_byte;
		bits_per_word = PIC32_SPI_CTRL_BPW_8;
		break;
	case 16:
		priv->rx_fifo = pic32_spi_rx_word;
		priv->tx_fifo = pic32_spi_tx_word;
		bits_per_word = PIC32_SPI_CTRL_BPW_16;
		break;
	case 32:
		priv->rx_fifo = pic32_spi_rx_dword;
		priv->tx_fifo = pic32_spi_tx_dword;
		bits_per_word = PIC32_SPI_CTRL_BPW_32;
		break;
	default:
		printf("pic32-spi: unsupported wordlen\n");
		return -EINVAL;
	}

	/* set bits-per-word */
	val = readl(&priv->regs->ctrl.raw);
	val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
	val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
	writel(val, &priv->regs->ctrl.raw);

	/* calculate maximum number of words fifo can hold */
	priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);

	return 0;
}

static int pic32_spi_claim_bus(struct udevice *slave)
{
	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);

	/* enable chip */
	pic32_spi_enable(priv);

	return 0;
}

static int pic32_spi_release_bus(struct udevice *slave)
{
	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);

	/* disable chip */
	pic32_spi_disable(priv);

	return 0;
}

static void spi_cs_activate(struct pic32_spi_priv *priv)
{
	if (!dm_gpio_is_valid(&priv->cs_gpio))
		return;

	dm_gpio_set_value(&priv->cs_gpio, 1);
}

static void spi_cs_deactivate(struct pic32_spi_priv *priv)
{
	if (!dm_gpio_is_valid(&priv->cs_gpio))
		return;

	dm_gpio_set_value(&priv->cs_gpio, 0);
}

static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
			  const void *tx_buf, void *rx_buf,
			  unsigned long flags)
{
	struct dm_spi_slave_plat *slave_plat;
	struct udevice *bus = slave->parent;
	struct pic32_spi_priv *priv;
	int len = bitlen / 8;
	int ret = 0;
	ulong tbase;

	priv = dev_get_priv(bus);
	slave_plat = dev_get_parent_plat(slave);

	debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
	      dev_seq(bus), slave_plat->cs[0], flags);
	debug("msg tx %p, rx %p submitted of %d byte(s)\n",
	      tx_buf, rx_buf, len);

	/* assert cs */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(priv);

	/* set current transfer information */
	priv->tx = tx_buf;
	priv->rx = rx_buf;
	priv->tx_end = priv->tx + len;
	priv->rx_end = priv->rx + len;
	priv->len = len;

	/* transact by polling */
	tbase = get_timer(0);
	for (;;) {
		priv->tx_fifo(priv);
		priv->rx_fifo(priv);

		/* received sufficient data */
		if (priv->rx >= priv->rx_end) {
			ret = 0;
			break;
		}

		if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
			printf("pic32_spi: error, xfer timedout.\n");
			flags |= SPI_XFER_END;
			ret = -ETIMEDOUT;
			break;
		}
	}

	/* deassert cs */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(priv);

	return ret;
}

static int pic32_spi_set_speed(struct udevice *bus, uint speed)
{
	struct pic32_spi_priv *priv = dev_get_priv(bus);
	u32 div;

	debug("%s: %s, speed %u\n", __func__, bus->name, speed);

	/* div = [clk_in / (2 * spi_clk)] - 1 */
	div = (priv->clk_rate / 2 / speed) - 1;
	div &= PIC32_SPI_BAUD_MASK;
	writel(div, &priv->regs->baud.raw);

	priv->speed_hz = speed;

	return 0;
}

static int pic32_spi_set_mode(struct udevice *bus, uint mode)
{
	struct pic32_spi_priv *priv = dev_get_priv(bus);
	u32 val;

	debug("%s: %s, mode %d\n", __func__, bus->name, mode);

	/* set spi-clk mode */
	val = readl(&priv->regs->ctrl.raw);
	/* HIGH when idle */
	if (mode & SPI_CPOL)
		val |= PIC32_SPI_CTRL_CKP;
	else
		val &= ~PIC32_SPI_CTRL_CKP;

	/* TX at idle-to-active clk transition */
	if (mode & SPI_CPHA)
		val &= ~PIC32_SPI_CTRL_CKE;
	else
		val |= PIC32_SPI_CTRL_CKE;

	/* RX at end of tx */
	val |= PIC32_SPI_CTRL_SMP;
	writel(val, &priv->regs->ctrl.raw);

	priv->mode = mode;

	return 0;
}

static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
{
	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);

	return pic32_spi_set_word_size(priv, wordlen);
}

static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
{
	u32 val;

	/* disable module */
	pic32_spi_disable(priv);

	val = readl(&priv->regs->ctrl);

	/* enable enhanced fifo of 128bit deep */
	val |= PIC32_SPI_CTRL_ENHBUF;
	priv->fifo_depth = 16;

	/* disable framing mode */
	val &= ~PIC32_SPI_CTRL_FRMEN;

	/* enable master mode */
	val |= PIC32_SPI_CTRL_MSTEN;

	/* select clk source */
	val &= ~PIC32_SPI_CTRL_MCLKSEL;

	/* set manual /CS mode */
	val &= ~PIC32_SPI_CTRL_MSSEN;

	writel(val, &priv->regs->ctrl);

	/* clear rx overflow indicator */
	writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
}

static int pic32_spi_probe(struct udevice *bus)
{
	struct pic32_spi_priv *priv = dev_get_priv(bus);
	struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
	int node = dev_of_offset(bus);
	struct udevice *clkdev;
	fdt_addr_t addr;
	fdt_size_t size;
	int ret;

	debug("%s: %d, bus: %i\n", __func__, __LINE__, dev_seq(bus));
	addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = ioremap(addr, size);
	if (!priv->regs)
		return -EINVAL;

	dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
					250000000);
	/* get clock rate */
	ret = clk_get_by_index(bus, 0, &clkdev);
	if (ret < 0) {
		printf("pic32-spi: error, clk not found\n");
		return ret;
	}
	priv->clk_rate = clk_get_periph_rate(clkdev, ret);

	/* initialize HW */
	pic32_spi_hw_init(priv);

	/* set word len */
	pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);

	/* PIC32 SPI controller can automatically drive /CS during transfer
	 * depending on fifo fill-level. /CS will stay asserted as long as
	 * TX fifo is non-empty, else will be deasserted confirming completion
	 * of the ongoing transfer. To avoid this sort of error we will drive
	 * /CS manually by toggling cs-gpio pins.
	 */
	ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
					 &priv->cs_gpio, GPIOD_IS_OUT);
	if (ret) {
		printf("pic32-spi: error, cs-gpios not found\n");
		return ret;
	}

	return 0;
}

static const struct dm_spi_ops pic32_spi_ops = {
	.claim_bus	= pic32_spi_claim_bus,
	.release_bus	= pic32_spi_release_bus,
	.xfer		= pic32_spi_xfer,
	.set_speed	= pic32_spi_set_speed,
	.set_mode	= pic32_spi_set_mode,
	.set_wordlen	= pic32_spi_set_wordlen,
};

static const struct udevice_id pic32_spi_ids[] = {
	{ .compatible = "microchip,pic32mzda-spi" },
	{ }
};

U_BOOT_DRIVER(pic32_spi) = {
	.name		= "pic32_spi",
	.id		= UCLASS_SPI,
	.of_match	= pic32_spi_ids,
	.ops		= &pic32_spi_ops,
	.priv_auto	= sizeof(struct pic32_spi_priv),
	.probe		= pic32_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e19b9004 PCM	2	/*
	3	* Microchip PIC32 SPI controller driver.
	4	*
	5	* Copyright (c) 2015, Microchip Technology Inc.
	6	* Purna Chandra Mandal <[email protected]>
e19b9004 PCM	7	*/
e19b9004 PCM	8
e19b9004 PCM	9	#include <clk.h>
e19b9004 PCM	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
401d1c4f	12	#include <asm/global_data.h>
cd93d625	13	#include <linux/bitops.h>
e19b9004 PCM	14	#include <linux/compat.h>
	15	#include <malloc.h>
	16	#include <spi.h>
	17
	18	#include <asm/types.h>
	19	#include <asm/io.h>
	20	#include <asm/gpio.h>
	21	#include <dt-bindings/clock/microchip,clock.h>
	22	#include <mach/pic32.h>
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	/* PIC32 SPI controller registers */
	27	struct pic32_reg_spi {
	28	struct pic32_reg_atomic ctrl;
	29	struct pic32_reg_atomic status;
	30	struct pic32_reg_atomic buf;
	31	struct pic32_reg_atomic baud;
	32	struct pic32_reg_atomic ctrl2;
	33	};
	34
	35	/* Bit fields in SPI Control Register */
	36	#define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
	37	#define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
	38	#define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
	39	#define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
	40	#define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
	41	#define PIC32_SPI_CTRL_BPW_8 0x0
	42	#define PIC32_SPI_CTRL_BPW_16 0x1
	43	#define PIC32_SPI_CTRL_BPW_32 0x2
	44	#define PIC32_SPI_CTRL_BPW_SHIFT 10
	45	#define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
	46	#define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
	47	#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
	48	#define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
	49	#define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
	50
	51	/* Bit fields in SPI Status Register */
	52	#define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
	53	#define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
	54	#define PIC32_SPI_STAT_TF_LVL_SHIFT 16
	55	#define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
	56	#define PIC32_SPI_STAT_RF_LVL_SHIFT 24
	57
	58	/* Bit fields in SPI Baud Register */
	59	#define PIC32_SPI_BAUD_MASK 0x1ff
	60
	61	struct pic32_spi_priv {
	62	struct pic32_reg_spi *regs;
	63	u32 fifo_depth; /* FIFO depth in bytes */
	64	u32 fifo_n_word; /* FIFO depth in words */
	65	struct gpio_desc cs_gpio;
	66
	67	/* Current SPI slave specific */
	68	ulong clk_rate;
	69	u32 speed_hz; /* spi-clk rate */
	70	int mode;
	71
	72	/* Current message/transfer state */
	73	const void *tx;
	74	const void *tx_end;
	75	const void *rx;
	76	const void *rx_end;
	77	u32 len;
78
79	/* SPI FiFo accessor */
80	void (rx_fifo)(struct pic32_spi_priv );
81	void (tx_fifo)(struct pic32_spi_priv );
82	};
83
84	static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
85	{
86	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
87	}
88
89	static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
90	{
91	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
92	}
93
94	static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
95	{
96	u32 sr = readl(&priv->regs->status.raw);
97
98	return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
99	}
100
101	static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
102	{
103	u32 sr = readl(&priv->regs->status.raw);
104
105	return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
106	}
107
108	/* Return the max entries we can fill into tx fifo */
109	static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
110	{
111	u32 tx_left, tx_room, rxtx_gap;
112
113	tx_left = (priv->tx_end - priv->tx) / n_bytes;
114	tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
115
116	rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
117	rxtx_gap /= n_bytes;
118	return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
119	}
120
121	/* Return the max entries we should read out of rx fifo */
122	static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
123	{
124	u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
125
126	return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
127	}
128
129	#define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
130	static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
131	{ \
132	__type val; \
133	u32 mx = pic32_rx_max(priv, sizeof(__type)); \
134	\
135	for (; mx; mx--) { \
136	val = read##__bwl(&priv->regs->buf.raw); \
137	if (priv->rx_end - priv->len) \
138	(__type )(priv->rx) = val; \
139	priv->rx += sizeof(__type); \
140	} \
141	} \
142	\
143	static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
144	{ \
145	__type val; \
146	u32 mx = pic32_tx_max(priv, sizeof(__type)); \
147	\
148	for (; mx ; mx--) { \
149	val = (__type) ~0U; \
150	if (priv->tx_end - priv->len) \
151	val = (__type )(priv->tx); \
152	write##__bwl(val, &priv->regs->buf.raw); \
153	priv->tx += sizeof(__type); \
154	} \
155	}
156	BUILD_SPI_FIFO_RW(byte, u8, b);
157	BUILD_SPI_FIFO_RW(word, u16, w);
158	BUILD_SPI_FIFO_RW(dword, u32, l);
159
160	static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
161	unsigned int wordlen)
162	{
163	u32 bits_per_word;
164	u32 val;
165
166	switch (wordlen) {
167	case 8:
168	priv->rx_fifo = pic32_spi_rx_byte;
169	priv->tx_fifo = pic32_spi_tx_byte;
170	bits_per_word = PIC32_SPI_CTRL_BPW_8;
171	break;
172	case 16:
173	priv->rx_fifo = pic32_spi_rx_word;
174	priv->tx_fifo = pic32_spi_tx_word;
175	bits_per_word = PIC32_SPI_CTRL_BPW_16;
176	break;
177	case 32:
178	priv->rx_fifo = pic32_spi_rx_dword;
179	priv->tx_fifo = pic32_spi_tx_dword;
180	bits_per_word = PIC32_SPI_CTRL_BPW_32;
181	break;
182	default:
183	printf("pic32-spi: unsupported wordlen\n");
184	return -EINVAL;
185	}
186
187	/* set bits-per-word */
188	val = readl(&priv->regs->ctrl.raw);
189	val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
190	val \|= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
191	writel(val, &priv->regs->ctrl.raw);
192
193	/* calculate maximum number of words fifo can hold */
194	priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
195
196	return 0;
197	}
198
199	static int pic32_spi_claim_bus(struct udevice *slave)
200	{
201	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
202
203	/* enable chip */
204	pic32_spi_enable(priv);
205
206	return 0;
207	}
208
209	static int pic32_spi_release_bus(struct udevice *slave)
210	{
211	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
212
213	/* disable chip */
214	pic32_spi_disable(priv);
215
216	return 0;
217	}
218
219	static void spi_cs_activate(struct pic32_spi_priv *priv)
220	{
221	if (!dm_gpio_is_valid(&priv->cs_gpio))
222	return;
223
224	dm_gpio_set_value(&priv->cs_gpio, 1);
225	}
226
227	static void spi_cs_deactivate(struct pic32_spi_priv *priv)
228	{
229	if (!dm_gpio_is_valid(&priv->cs_gpio))
230	return;
231
232	dm_gpio_set_value(&priv->cs_gpio, 0);
233	}
234
235	static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
236	const void tx_buf, void rx_buf,
237	unsigned long flags)
238	{
8a8d24bd	239	struct dm_spi_slave_plat *slave_plat;
e19b9004 PCM	240	struct udevice *bus = slave->parent;
	241	struct pic32_spi_priv *priv;
	242	int len = bitlen / 8;
	243	int ret = 0;
	244	ulong tbase;
	245
	246	priv = dev_get_priv(bus);
caa4daa2	247	slave_plat = dev_get_parent_plat(slave);
e19b9004 PCM	248
e19b9004 PCM	249	debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
34da258b	250	dev_seq(bus), slave_plat->cs[0], flags);
e19b9004 PCM	251	debug("msg tx %p, rx %p submitted of %d byte(s)\n",
	252	tx_buf, rx_buf, len);
	253
	254	/* assert cs */
	255	if (flags & SPI_XFER_BEGIN)
	256	spi_cs_activate(priv);
	257
	258	/* set current transfer information */
	259	priv->tx = tx_buf;
	260	priv->rx = rx_buf;
	261	priv->tx_end = priv->tx + len;
	262	priv->rx_end = priv->rx + len;
	263	priv->len = len;
	264
	265	/* transact by polling */
	266	tbase = get_timer(0);
	267	for (;;) {
	268	priv->tx_fifo(priv);
	269	priv->rx_fifo(priv);
	270
	271	/* received sufficient data */
	272	if (priv->rx >= priv->rx_end) {
	273	ret = 0;
	274	break;
	275	}
	276
	277	if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
	278	printf("pic32_spi: error, xfer timedout.\n");
	279	flags \|= SPI_XFER_END;
	280	ret = -ETIMEDOUT;
	281	break;
	282	}
	283	}
	284
	285	/* deassert cs */
	286	if (flags & SPI_XFER_END)
	287	spi_cs_deactivate(priv);
	288
	289	return ret;
	290	}
	291
	292	static int pic32_spi_set_speed(struct udevice *bus, uint speed)
	293	{
	294	struct pic32_spi_priv *priv = dev_get_priv(bus);
	295	u32 div;
	296
	297	debug("%s: %s, speed %u\n", __func__, bus->name, speed);
	298
	299	/* div = [clk_in / (2 * spi_clk)] - 1 */
	300	div = (priv->clk_rate / 2 / speed) - 1;
	301	div &= PIC32_SPI_BAUD_MASK;
	302	writel(div, &priv->regs->baud.raw);
	303
	304	priv->speed_hz = speed;
	305
	306	return 0;
	307	}
	308
	309	static int pic32_spi_set_mode(struct udevice *bus, uint mode)
	310	{
	311	struct pic32_spi_priv *priv = dev_get_priv(bus);
	312	u32 val;
	313
	314	debug("%s: %s, mode %d\n", __func__, bus->name, mode);
315
316	/* set spi-clk mode */
317	val = readl(&priv->regs->ctrl.raw);
318	/* HIGH when idle */
319	if (mode & SPI_CPOL)
320	val \|= PIC32_SPI_CTRL_CKP;
321	else
322	val &= ~PIC32_SPI_CTRL_CKP;
323
324	/* TX at idle-to-active clk transition */
325	if (mode & SPI_CPHA)
326	val &= ~PIC32_SPI_CTRL_CKE;
327	else
328	val \|= PIC32_SPI_CTRL_CKE;
329
330	/* RX at end of tx */
331	val \|= PIC32_SPI_CTRL_SMP;
332	writel(val, &priv->regs->ctrl.raw);
333
334	priv->mode = mode;
335
336	return 0;
337	}
338
339	static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
340	{
341	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
342
343	return pic32_spi_set_word_size(priv, wordlen);
344	}
345
346	static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
347	{
348	u32 val;
349
350	/* disable module */
351	pic32_spi_disable(priv);
352
353	val = readl(&priv->regs->ctrl);
354
355	/* enable enhanced fifo of 128bit deep */
356	val \|= PIC32_SPI_CTRL_ENHBUF;
357	priv->fifo_depth = 16;
358
359	/* disable framing mode */
360	val &= ~PIC32_SPI_CTRL_FRMEN;
361
362	/* enable master mode */
363	val \|= PIC32_SPI_CTRL_MSTEN;
364
365	/* select clk source */
366	val &= ~PIC32_SPI_CTRL_MCLKSEL;
367
368	/* set manual /CS mode */
369	val &= ~PIC32_SPI_CTRL_MSSEN;
370
371	writel(val, &priv->regs->ctrl);
372
373	/* clear rx overflow indicator */
374	writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
375	}
376
377	static int pic32_spi_probe(struct udevice *bus)
378	{
379	struct pic32_spi_priv *priv = dev_get_priv(bus);
380	struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
e160f7d4	381	int node = dev_of_offset(bus);
e19b9004 PCM	382	struct udevice *clkdev;
	383	fdt_addr_t addr;
	384	fdt_size_t size;
	385	int ret;
	386
8b85dfc6	387	debug("%s: %d, bus: %i\n", __func__, __LINE__, dev_seq(bus));
e160f7d4	388	addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
e19b9004 PCM	389	if (addr == FDT_ADDR_T_NONE)
	390	return -EINVAL;
	391
	392	priv->regs = ioremap(addr, size);
	393	if (!priv->regs)
	394	return -EINVAL;
	395
e160f7d4 SG	396	dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
e160f7d4 SG	397	250000000);
e19b9004 PCM	398	/* get clock rate */
	399	ret = clk_get_by_index(bus, 0, &clkdev);
	400	if (ret < 0) {
	401	printf("pic32-spi: error, clk not found\n");
	402	return ret;
	403	}
	404	priv->clk_rate = clk_get_periph_rate(clkdev, ret);
	405
	406	/* initialize HW */
	407	pic32_spi_hw_init(priv);
	408
	409	/* set word len */
	410	pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
	411
	412	/* PIC32 SPI controller can automatically drive /CS during transfer
	413	* depending on fifo fill-level. /CS will stay asserted as long as
	414	* TX fifo is non-empty, else will be deasserted confirming completion
	415	* of the ongoing transfer. To avoid this sort of error we will drive
	416	* /CS manually by toggling cs-gpio pins.
	417	*/
150c5afe	418	ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
e19b9004 PCM	419	&priv->cs_gpio, GPIOD_IS_OUT);
	420	if (ret) {
	421	printf("pic32-spi: error, cs-gpios not found\n");
	422	return ret;
	423	}
	424
	425	return 0;
	426	}
	427
	428	static const struct dm_spi_ops pic32_spi_ops = {
	429	.claim_bus = pic32_spi_claim_bus,
	430	.release_bus = pic32_spi_release_bus,
	431	.xfer = pic32_spi_xfer,
	432	.set_speed = pic32_spi_set_speed,
	433	.set_mode = pic32_spi_set_mode,
	434	.set_wordlen = pic32_spi_set_wordlen,
	435	};
	436
	437	static const struct udevice_id pic32_spi_ids[] = {
	438	{ .compatible = "microchip,pic32mzda-spi" },
	439	{ }
	440	};
	441
	442	U_BOOT_DRIVER(pic32_spi) = {
	443	.name = "pic32_spi",
	444	.id = UCLASS_SPI,
	445	.of_match = pic32_spi_ids,
	446	.ops = &pic32_spi_ops,
41575d8e	447	.priv_auto = sizeof(struct pic32_spi_priv),
e19b9004 PCM	448	.probe = pic32_spi_probe,
e19b9004 PCM	449	};