projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fcc18e0 WD |
1 | I2C Edge Conditions: |
| 2 | ==================== | |
| 3 | ||
| 4 | I2C devices may be left in a write state if a read was occuring | |
| 5 | and the CPU was reset. This may result in EEPROM data corruption. | |
| 6 | ||
| 7 | The edge condition is as follows: | |
| 8 | 1) A read operation begins. | |
| 9 | 2) I2C controller issues a start command. | |
| 10 | 3) The I2C writes the device address. | |
| 11 | 4) The CPU is reset at this point. | |
| 12 | ||
| 13 | Once the CPU reinitializes and the read is tried again: | |
| 14 | 1) The I2C controller issues a start command. | |
| 15 | 2) The I2C controller writes the device address. | |
| 16 | 3) The I2C controller writes the offset. | |
| 17 | ||
| 18 | The EEPROM sees: | |
| 19 | 1) START | |
| 20 | 2) device address | |
| 21 | 3) START "this start is ignored by most EEPROMs" | |
| 22 | 4) device address "EEPROM interprets this as offset" | |
| 23 | 5) Offset in device, "EEPROM interprets this as data to write" | |
| 24 | ||
| 25 | The device will interpret this sequence as a WRITE command and | |
| 26 | write rubbish into itself, i.e. the "offset" will be interpreted | |
| 27 | as data to be written in location "device address". | |
| 28 | ||
| 29 | Notes | |
| 30 | ----- | |
| 0c8721a4 | 31 | !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!! |
| 6fcc18e0 WD |
32 | |
| 33 | This reset edge condition could possibly be present in every I2C | |
| 56ec7a69 SG |
34 | controller and device available. |
| 35 | ||
| 36 | Note that this problem does not happen when using the bit-banging I2C driver | |
| 37 | (common/soft_i2c.c) as this already includes the I2C bus reset sequence. | |
| 3e38691e | 38 | |
| 6fcc18e0 WD |
39 | |
| 40 | Many thanks to Bill Hunter for finding this serious BUG. | |
| 41 | email to: <[email protected]> | |
| 42 | ||
| 43 | Erik Theisen <[email protected]> | |
| 44 | Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET) |