[J-u-boot.git] / tools / socfpgaimage.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2014 Charles Manning <[email protected]>
 *
 * Reference documents:
 *   Cyclone V SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5400a.pdf
 *   Arria V SoC:   https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-v/av_5400a.pdf
 *   Arria 10 SoC:  https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_5400a.pdf
 *
 * Bootable SoCFPGA image requires a structure of the following format
 * positioned at offset 0x40 of the bootable image. Endian is LSB.
 *
 * There are two versions of the SoCFPGA header format, v0 and v1.
 * The version 0 is used by Cyclone V SoC and Arria V SoC, while
 * the version 1 is used by the Arria 10 SoC.
 *
 * Version 0:
 * Offset   Length   Usage
 * -----------------------
 *   0x40        4   Validation word (0x31305341)
 *   0x44        1   Version (0x0)
 *   0x45        1   Flags (unused, zero is fine)
 *   0x46        2   Length (in units of u32, including the end checksum).
 *   0x48        2   Zero (0x0)
 *   0x4A        2   Checksum over the header. NB Not CRC32
 *
 * Version 1:
 * Offset   Length   Usage
 * -----------------------
 *   0x40        4   Validation word (0x31305341)
 *   0x44        1   Version (0x1)
 *   0x45        1   Flags (unused, zero is fine)
 *   0x46        2   Header length (in units of u8).
 *   0x48        4   Length (in units of u8).
 *   0x4C        4   Image entry offset from standard of header
 *   0x50        2   Zero (0x0)
 *   0x52        2   Checksum over the header. NB Not CRC32
 *
 * At the end of the code we have a 32-bit CRC checksum over whole binary
 * excluding the CRC.
 *
 * Note that the CRC used here is **not** the zlib/Adler crc32. It is the
 * CRC-32 used in bzip2, ethernet and elsewhere.
 *
 * The Image entry offset in version 1 image is relative the the start of
 * the header, 0x40, and must not be a negative number. Therefore, it is
 * only possible to make the SoCFPGA jump forward. The U-Boot bootloader
 * places a trampoline instruction at offset 0x5c, 0x14 bytes from the
 * start of the SoCFPGA header, which jumps to the reset vector.
 *
 * The image is padded out to 64k, because that is what is
 * typically used to write the image to the boot medium.
 */

#include "pbl_crc32.h"
#include "imagetool.h"
#include "mkimage.h"
#include <u-boot/crc.h>

#include <image.h>

#define HEADER_OFFSET	0x40
#define VALIDATION_WORD	0x31305341

/* Minimum and default entry point offset */
#define ENTRY_POINT_OFFSET	0x14

static uint8_t buffer_v0[0x10000];
static uint8_t buffer_v1[0x40000];

struct socfpga_header_v0 {
	uint32_t	validation;
	uint8_t		version;
	uint8_t		flags;
	uint16_t	length_u32;
	uint16_t	zero;
	uint16_t	checksum;
};

struct socfpga_header_v1 {
	uint32_t	validation;
	uint8_t		version;
	uint8_t		flags;
	uint16_t	header_u8;
	uint32_t	length_u8;
	uint32_t	entry_offset;
	uint16_t	zero;
	uint16_t	checksum;
};

static unsigned int sfp_hdr_size(uint8_t ver)
{
	if (ver == 0)
		return sizeof(struct socfpga_header_v0);
	if (ver == 1)
		return sizeof(struct socfpga_header_v1);
	return 0;
}

static unsigned int sfp_pad_size(uint8_t ver)
{
	if (ver == 0)
		return sizeof(buffer_v0);
	if (ver == 1)
		return sizeof(buffer_v1);
	return 0;
}

/*
 * The header checksum is just a very simple checksum over
 * the header area.
 * There is still a crc32 over the whole lot.
 */
static uint16_t sfp_hdr_checksum(uint8_t *buf, unsigned char ver)
{
	uint16_t ret = 0;
	int len = sfp_hdr_size(ver) - sizeof(ret);

	while (--len)
		ret += *buf++;

	return ret;
}

static void sfp_build_header(uint8_t *buf, uint8_t ver, uint8_t flags,
			     uint32_t length_bytes,
			     struct image_tool_params *params)
{
	uint32_t entry_offset = params->eflag ? params->ep : ENTRY_POINT_OFFSET;
	struct socfpga_header_v0 header_v0 = {
		.validation	= cpu_to_le32(VALIDATION_WORD),
		.version	= 0,
		.flags		= flags,
		.length_u32	= cpu_to_le16(length_bytes / 4),
		.zero		= 0,
	};

	struct socfpga_header_v1 header_v1 = {
		.validation	= cpu_to_le32(VALIDATION_WORD),
		.version	= 1,
		.flags		= flags,
		.header_u8	= cpu_to_le16(sizeof(header_v1)),
		.length_u8	= cpu_to_le32(length_bytes),
		/* Trampoline offset */
		.entry_offset	= cpu_to_le32(entry_offset),
		.zero		= 0,
	};

	uint16_t csum;

	if (ver == 0) {
		csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
		header_v0.checksum = cpu_to_le16(csum);
		memcpy(buf, &header_v0, sizeof(header_v0));
	} else {
		csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
		header_v1.checksum = cpu_to_le16(csum);
		memcpy(buf, &header_v1, sizeof(header_v1));
	}
}

/*
 * Perform a rudimentary verification of header and return
 * size of image.
 */
static int sfp_verify_header(const uint8_t *buf, uint8_t *ver)
{
	struct socfpga_header_v0 header_v0;
	struct socfpga_header_v1 header_v1;
	uint16_t hdr_csum, sfp_csum;
	uint32_t img_len;

	/*
	 * Header v0 is always smaller than Header v1 and the validation
	 * word and version field is at the same place, so use Header v0
	 * to check for version during verifiction and upgrade to Header
	 * v1 if needed.
	 */
	memcpy(&header_v0, buf, sizeof(header_v0));

	if (le32_to_cpu(header_v0.validation) != VALIDATION_WORD)
		return -1;

	if (header_v0.version == 0) {
		hdr_csum = le16_to_cpu(header_v0.checksum);
		sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
		img_len = le16_to_cpu(header_v0.length_u32) * 4;
	} else if (header_v0.version == 1) {
		memcpy(&header_v1, buf, sizeof(header_v1));
		hdr_csum = le16_to_cpu(header_v1.checksum);
		sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
		img_len = le32_to_cpu(header_v1.length_u8);
	} else {	/* Invalid version */
		return -EINVAL;
	}

	/* Verify checksum */
	if (hdr_csum != sfp_csum)
		return -EINVAL;

	*ver = header_v0.version;
	return img_len;
}

/* Sign the buffer and return the signed buffer size */
static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags,
			   int len, int pad_64k,
			   struct image_tool_params *params)
{
	uint32_t calc_crc;

	/* Align the length up */
	len = ALIGN(len, 4);

	/* Build header, adding 4 bytes to length to hold the CRC32. */
	sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4, params);

	/* Calculate and apply the CRC */
	calc_crc = ~pbl_crc32(0, (char *)buf, len);

	*((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);

	if (!pad_64k)
		return len + 4;

	return sfp_pad_size(ver);
}

/* Verify that the buffer looks sane */
static int sfp_verify_buffer(const uint8_t *buf)
{
	int len; /* Including 32bit CRC */
	uint32_t calc_crc;
	uint32_t buf_crc;
	uint8_t ver = 0;

	len = sfp_verify_header(buf + HEADER_OFFSET, &ver);
	if (len < 0) {
		debug("Invalid header\n");
		return -1;
	}

	if (len < HEADER_OFFSET || len > sfp_pad_size(ver)) {
		debug("Invalid header length (%i)\n", len);
		return -1;
	}

	/*
	 * Adjust length to the base of the CRC.
	 * Check the CRC.
	*/
	len -= 4;

	calc_crc = ~pbl_crc32(0, (const char *)buf, len);

	buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));

	if (buf_crc != calc_crc) {
		fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
			buf_crc, calc_crc);
		return -1;
	}

	return 0;
}

/* mkimage glue functions */
static int socfpgaimage_verify_header(unsigned char *ptr, int image_size,
				      struct image_tool_params *params)
{
	if (image_size < 0x80)
		return -1;

	return sfp_verify_buffer(ptr);
}

static void socfpgaimage_print_header(const void *ptr)
{
	if (sfp_verify_buffer(ptr) == 0)
		printf("Looks like a sane SOCFPGA preloader\n");
	else
		printf("Not a sane SOCFPGA preloader\n");
}

static int socfpgaimage_check_params_v0(struct image_tool_params *params)
{
	/* Not sure if we should be accepting fflags */
	return	(params->dflag && (params->fflag || params->lflag)) ||
		(params->fflag && (params->dflag || params->lflag)) ||
		(params->lflag && (params->dflag || params->fflag));
}

static int socfpgaimage_check_params_v1(struct image_tool_params *params)
{
	/*
	 * If the entry point is specified, ensure it is >= ENTRY_POINT_OFFSET
	 * and it is 4 bytes aligned.
	 */
	if (params->eflag && (params->ep < ENTRY_POINT_OFFSET ||
			      params->ep % 4 != 0)) {
		fprintf(stderr,
			"Error: Entry point must be greater than 0x%x.\n",
			ENTRY_POINT_OFFSET);
		return -1;
	}

	/* Not sure if we should be accepting fflags */
	return	(params->dflag && (params->fflag || params->lflag)) ||
		(params->fflag && (params->dflag || params->lflag)) ||
		(params->lflag && (params->dflag || params->fflag));
}

static int socfpgaimage_check_image_types_v0(uint8_t type)
{
	if (type == IH_TYPE_SOCFPGAIMAGE)
		return EXIT_SUCCESS;
	return EXIT_FAILURE;
}

static int socfpgaimage_check_image_types_v1(uint8_t type)
{
	if (type == IH_TYPE_SOCFPGAIMAGE_V1)
		return EXIT_SUCCESS;
	return EXIT_FAILURE;
}

/*
 * To work in with the mkimage framework, we do some ugly stuff...
 *
 * First, socfpgaimage_vrec_header() is called.
 * We prepend a fake header big enough to make the file sfp_pad_size().
 * This gives us enough space to do what we want later.
 *
 * Next, socfpgaimage_set_header() is called.
 * We fix up the buffer by moving the image to the start of the buffer.
 * We now have some room to do what we need (add CRC and padding).
 */

static int data_size;

static int sfp_fake_header_size(unsigned int size, uint8_t ver)
{
	return sfp_pad_size(ver) - size;
}

static int sfp_vrec_header(struct image_tool_params *params,
			   struct image_type_params *tparams, uint8_t ver)
{
	struct stat sbuf;

	if (params->datafile &&
	    stat(params->datafile, &sbuf) == 0 &&
	    sbuf.st_size <= (sfp_pad_size(ver) - sizeof(uint32_t))) {
		data_size = sbuf.st_size;
		tparams->header_size = sfp_fake_header_size(data_size, ver);
	}
	return 0;

}

static int socfpgaimage_vrec_header_v0(struct image_tool_params *params,
				       struct image_type_params *tparams)
{
	return sfp_vrec_header(params, tparams, 0);
}

static int socfpgaimage_vrec_header_v1(struct image_tool_params *params,
				       struct image_type_params *tparams)
{
	return sfp_vrec_header(params, tparams, 1);
}

static void sfp_set_header(void *ptr, unsigned char ver,
			   struct image_tool_params *params)
{
	uint8_t *buf = (uint8_t *)ptr;

	/*
	 * This function is called after vrec_header() has been called.
	 * At this stage we have the sfp_fake_header_size() dummy bytes
	 * followed by data_size image bytes. Total = sfp_pad_size().
	 * We need to fix the buffer by moving the image bytes back to
	 * the beginning of the buffer, then actually do the signing stuff...
	 */
	memmove(buf, buf + sfp_fake_header_size(data_size, ver), data_size);
	memset(buf + data_size, 0, sfp_fake_header_size(data_size, ver));

	sfp_sign_buffer(buf, ver, 0, data_size, 0, params);
}

static void socfpgaimage_set_header_v0(void *ptr, struct stat *sbuf, int ifd,
				       struct image_tool_params *params)
{
	sfp_set_header(ptr, 0, params);
}

static void socfpgaimage_set_header_v1(void *ptr, struct stat *sbuf, int ifd,
				       struct image_tool_params *params)
{
	sfp_set_header(ptr, 1, params);
}

U_BOOT_IMAGE_TYPE(
	socfpgaimage,
	"Altera SoCFPGA Cyclone V / Arria V image support",
	0, /* This will be modified by vrec_header() */
	(void *)buffer_v0,
	socfpgaimage_check_params_v0,
	socfpgaimage_verify_header,
	socfpgaimage_print_header,
	socfpgaimage_set_header_v0,
	NULL,
	socfpgaimage_check_image_types_v0,
	NULL,
	socfpgaimage_vrec_header_v0
);

U_BOOT_IMAGE_TYPE(
	socfpgaimage_v1,
	"Altera SoCFPGA Arria10 image support",
	0, /* This will be modified by vrec_header() */
	(void *)buffer_v1,
	socfpgaimage_check_params_v1,
	socfpgaimage_verify_header,
	socfpgaimage_print_header,
	socfpgaimage_set_header_v1,
	NULL,
	socfpgaimage_check_image_types_v1,
	NULL,
	socfpgaimage_vrec_header_v1
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
832472a9 CM	2	/*
	3	* Copyright (C) 2014 Charles Manning <[email protected]>
	4	*
cece78fa MV	5	* Reference documents:
	6	* Cyclone V SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5400a.pdf
	7	* Arria V SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-v/av_5400a.pdf
	8	* Arria 10 SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_5400a.pdf
832472a9	9	*
cece78fa MV	10	* Bootable SoCFPGA image requires a structure of the following format
cece78fa MV	11	* positioned at offset 0x40 of the bootable image. Endian is LSB.
832472a9	12	*
cece78fa MV	13	* There are two versions of the SoCFPGA header format, v0 and v1.
	14	* The version 0 is used by Cyclone V SoC and Arria V SoC, while
	15	* the version 1 is used by the Arria 10 SoC.
832472a9	16	*
cece78fa	17	* Version 0:
832472a9 CM	18	* Offset Length Usage
832472a9 CM	19	* -----------------------
cece78fa MV	20	* 0x40 4 Validation word (0x31305341)
	21	* 0x44 1 Version (0x0)
	22	* 0x45 1 Flags (unused, zero is fine)
	23	* 0x46 2 Length (in units of u32, including the end checksum).
	24	* 0x48 2 Zero (0x0)
832472a9 CM	25	* 0x4A 2 Checksum over the header. NB Not CRC32
832472a9 CM	26	*
cece78fa MV	27	* Version 1:
	28	* Offset Length Usage
	29	* -----------------------
	30	* 0x40 4 Validation word (0x31305341)
	31	* 0x44 1 Version (0x1)
	32	* 0x45 1 Flags (unused, zero is fine)
	33	* 0x46 2 Header length (in units of u8).
	34	* 0x48 4 Length (in units of u8).
	35	* 0x4C 4 Image entry offset from standard of header
	36	* 0x50 2 Zero (0x0)
	37	* 0x52 2 Checksum over the header. NB Not CRC32
	38	*
832472a9 CM	39	* At the end of the code we have a 32-bit CRC checksum over whole binary
	40	* excluding the CRC.
	41	*
	42	* Note that the CRC used here is not the zlib/Adler crc32. It is the
	43	* CRC-32 used in bzip2, ethernet and elsewhere.
	44	*
cece78fa MV	45	* The Image entry offset in version 1 image is relative the the start of
	46	* the header, 0x40, and must not be a negative number. Therefore, it is
	47	* only possible to make the SoCFPGA jump forward. The U-Boot bootloader
	48	* places a trampoline instruction at offset 0x5c, 0x14 bytes from the
	49	* start of the SoCFPGA header, which jumps to the reset vector.
	50	*
832472a9 CM	51	* The image is padded out to 64k, because that is what is
	52	* typically used to write the image to the boot medium.
	53	*/
	54
	55	#include "pbl_crc32.h"
	56	#include "imagetool.h"
26621799	57	#include "mkimage.h"
3db71108	58	#include <u-boot/crc.h>
26621799	59
832472a9 CM	60	#include <image.h>
	61
	62	#define HEADER_OFFSET 0x40
	63	#define VALIDATION_WORD 0x31305341
832472a9	64
963e17ab LFT	65	/* Minimum and default entry point offset */
	66	#define ENTRY_POINT_OFFSET 0x14
	67
cece78fa MV	68	static uint8_t buffer_v0[0x10000];
cece78fa MV	69	static uint8_t buffer_v1[0x40000];
832472a9	70
cece78fa MV	71	struct socfpga_header_v0 {
	72	uint32_t validation;
	73	uint8_t version;
	74	uint8_t flags;
	75	uint16_t length_u32;
	76	uint16_t zero;
	77	uint16_t checksum;
	78	};
832472a9	79
cece78fa MV	80	struct socfpga_header_v1 {
	81	uint32_t validation;
	82	uint8_t version;
	83	uint8_t flags;
	84	uint16_t header_u8;
	85	uint32_t length_u8;
	86	uint32_t entry_offset;
	87	uint16_t zero;
	88	uint16_t checksum;
9f0021a5	89	};
832472a9	90
cece78fa MV	91	static unsigned int sfp_hdr_size(uint8_t ver)
	92	{
	93	if (ver == 0)
	94	return sizeof(struct socfpga_header_v0);
	95	if (ver == 1)
	96	return sizeof(struct socfpga_header_v1);
	97	return 0;
	98	}
	99
	100	static unsigned int sfp_pad_size(uint8_t ver)
	101	{
	102	if (ver == 0)
	103	return sizeof(buffer_v0);
	104	if (ver == 1)
	105	return sizeof(buffer_v1);
	106	return 0;
	107	}
	108
832472a9 CM	109	/*
	110	* The header checksum is just a very simple checksum over
	111	* the header area.
	112	* There is still a crc32 over the whole lot.
	113	*/
cece78fa	114	static uint16_t sfp_hdr_checksum(uint8_t *buf, unsigned char ver)
832472a9	115	{
832472a9	116	uint16_t ret = 0;
cece78fa	117	int len = sfp_hdr_size(ver) - sizeof(ret);
832472a9 CM	118
	119	while (--len)
	120	ret += *buf++;
	121
	122	return ret;
	123	}
	124
cece78fa	125	static void sfp_build_header(uint8_t *buf, uint8_t ver, uint8_t flags,
1d0dc5bc LFT	126	uint32_t length_bytes,
1d0dc5bc LFT	127	struct image_tool_params *params)
832472a9	128	{
1d0dc5bc	129	uint32_t entry_offset = params->eflag ? params->ep : ENTRY_POINT_OFFSET;
cece78fa MV	130	struct socfpga_header_v0 header_v0 = {
	131	.validation = cpu_to_le32(VALIDATION_WORD),
	132	.version = 0,
	133	.flags = flags,
	134	.length_u32 = cpu_to_le16(length_bytes / 4),
	135	.zero = 0,
	136	};
	137
	138	struct socfpga_header_v1 header_v1 = {
	139	.validation = cpu_to_le32(VALIDATION_WORD),
	140	.version = 1,
	141	.flags = flags,
	142	.header_u8 = cpu_to_le16(sizeof(header_v1)),
	143	.length_u8 = cpu_to_le32(length_bytes),
1d0dc5bc LFT	144	/* Trampoline offset */
1d0dc5bc LFT	145	.entry_offset = cpu_to_le32(entry_offset),
cece78fa MV	146	.zero = 0,
	147	};
	148
	149	uint16_t csum;
	150
	151	if (ver == 0) {
	152	csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
	153	header_v0.checksum = cpu_to_le16(csum);
	154	memcpy(buf, &header_v0, sizeof(header_v0));
	155	} else {
	156	csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
	157	header_v1.checksum = cpu_to_le16(csum);
	158	memcpy(buf, &header_v1, sizeof(header_v1));
	159	}
832472a9 CM	160	}
	161
	162	/*
	163	* Perform a rudimentary verification of header and return
	164	* size of image.
	165	*/
cece78fa	166	static int sfp_verify_header(const uint8_t buf, uint8_t ver)
832472a9	167	{
cece78fa MV	168	struct socfpga_header_v0 header_v0;
	169	struct socfpga_header_v1 header_v1;
	170	uint16_t hdr_csum, sfp_csum;
	171	uint32_t img_len;
9f0021a5	172
cece78fa MV	173	/*
	174	* Header v0 is always smaller than Header v1 and the validation
	175	* word and version field is at the same place, so use Header v0
	176	* to check for version during verifiction and upgrade to Header
	177	* v1 if needed.
	178	*/
	179	memcpy(&header_v0, buf, sizeof(header_v0));
832472a9	180
cece78fa	181	if (le32_to_cpu(header_v0.validation) != VALIDATION_WORD)
832472a9 CM	182	return -1;
832472a9 CM	183
cece78fa MV	184	if (header_v0.version == 0) {
	185	hdr_csum = le16_to_cpu(header_v0.checksum);
	186	sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
	187	img_len = le16_to_cpu(header_v0.length_u32) * 4;
	188	} else if (header_v0.version == 1) {
	189	memcpy(&header_v1, buf, sizeof(header_v1));
	190	hdr_csum = le16_to_cpu(header_v1.checksum);
	191	sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
	192	img_len = le32_to_cpu(header_v1.length_u8);
	193	} else { /* Invalid version */
	194	return -EINVAL;
	195	}
	196
	197	/* Verify checksum */
	198	if (hdr_csum != sfp_csum)
	199	return -EINVAL;
	200
0ca8fd37	201	*ver = header_v0.version;
cece78fa	202	return img_len;
832472a9 CM	203	}
	204
	205	/* Sign the buffer and return the signed buffer size */
cece78fa	206	static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags,
1d0dc5bc LFT	207	int len, int pad_64k,
1d0dc5bc LFT	208	struct image_tool_params *params)
832472a9 CM	209	{
	210	uint32_t calc_crc;
	211
	212	/* Align the length up */
02560b13	213	len = ALIGN(len, 4);
832472a9 CM	214
832472a9 CM	215	/* Build header, adding 4 bytes to length to hold the CRC32. */
1d0dc5bc	216	sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4, params);
832472a9 CM	217
	218	/* Calculate and apply the CRC */
	219	calc_crc = ~pbl_crc32(0, (char *)buf, len);
	220
686ed2c2	221	((uint32_t )(buf + len)) = cpu_to_le32(calc_crc);
832472a9 CM	222
	223	if (!pad_64k)
	224	return len + 4;
	225
cece78fa	226	return sfp_pad_size(ver);
832472a9 CM	227	}
	228
	229	/* Verify that the buffer looks sane */
cece78fa	230	static int sfp_verify_buffer(const uint8_t *buf)
832472a9 CM	231	{
	232	int len; /* Including 32bit CRC */
	233	uint32_t calc_crc;
	234	uint32_t buf_crc;
cece78fa	235	uint8_t ver = 0;
832472a9	236
cece78fa	237	len = sfp_verify_header(buf + HEADER_OFFSET, &ver);
832472a9	238	if (len < 0) {
26621799	239	debug("Invalid header\n");
832472a9 CM	240	return -1;
	241	}
	242
cece78fa	243	if (len < HEADER_OFFSET \|\| len > sfp_pad_size(ver)) {
26621799	244	debug("Invalid header length (%i)\n", len);
832472a9 CM	245	return -1;
	246	}
	247
	248	/*
	249	* Adjust length to the base of the CRC.
	250	* Check the CRC.
	251	*/
	252	len -= 4;
	253
	254	calc_crc = ~pbl_crc32(0, (const char *)buf, len);
	255
686ed2c2	256	buf_crc = le32_to_cpu(((uint32_t )(buf + len)));
832472a9 CM	257
	258	if (buf_crc != calc_crc) {
	259	fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
	260	buf_crc, calc_crc);
	261	return -1;
	262	}
	263
	264	return 0;
	265	}
	266
	267	/* mkimage glue functions */
	268	static int socfpgaimage_verify_header(unsigned char *ptr, int image_size,
cece78fa	269	struct image_tool_params *params)
832472a9	270	{
cece78fa	271	if (image_size < 0x80)
832472a9 CM	272	return -1;
832472a9 CM	273
cece78fa	274	return sfp_verify_buffer(ptr);
832472a9 CM	275	}
	276
	277	static void socfpgaimage_print_header(const void *ptr)
	278	{
cece78fa	279	if (sfp_verify_buffer(ptr) == 0)
832472a9 CM	280	printf("Looks like a sane SOCFPGA preloader\n");
	281	else
	282	printf("Not a sane SOCFPGA preloader\n");
	283	}
	284
963e17ab	285	static int socfpgaimage_check_params_v0(struct image_tool_params *params)
832472a9 CM	286	{
	287	/* Not sure if we should be accepting fflags */
	288	return (params->dflag && (params->fflag \|\| params->lflag)) \|\|
	289	(params->fflag && (params->dflag \|\| params->lflag)) \|\|
	290	(params->lflag && (params->dflag \|\| params->fflag));
	291	}
	292
963e17ab LFT	293	static int socfpgaimage_check_params_v1(struct image_tool_params *params)
	294	{
	295	/*
	296	* If the entry point is specified, ensure it is >= ENTRY_POINT_OFFSET
	297	* and it is 4 bytes aligned.
	298	*/
	299	if (params->eflag && (params->ep < ENTRY_POINT_OFFSET \|\|
	300	params->ep % 4 != 0)) {
	301	fprintf(stderr,
	302	"Error: Entry point must be greater than 0x%x.\n",
	303	ENTRY_POINT_OFFSET);
	304	return -1;
	305	}
	306
	307	/* Not sure if we should be accepting fflags */
	308	return (params->dflag && (params->fflag \|\| params->lflag)) \|\|
	309	(params->fflag && (params->dflag \|\| params->lflag)) \|\|
	310	(params->lflag && (params->dflag \|\| params->fflag));
	311	}
	312
cece78fa	313	static int socfpgaimage_check_image_types_v0(uint8_t type)
832472a9 CM	314	{
	315	if (type == IH_TYPE_SOCFPGAIMAGE)
	316	return EXIT_SUCCESS;
	317	return EXIT_FAILURE;
	318	}
	319
cece78fa MV	320	static int socfpgaimage_check_image_types_v1(uint8_t type)
	321	{
	322	if (type == IH_TYPE_SOCFPGAIMAGE_V1)
	323	return EXIT_SUCCESS;
	324	return EXIT_FAILURE;
	325	}
	326
832472a9 CM	327	/*
	328	* To work in with the mkimage framework, we do some ugly stuff...
	329	*
	330	* First, socfpgaimage_vrec_header() is called.
cece78fa	331	* We prepend a fake header big enough to make the file sfp_pad_size().
832472a9 CM	332	* This gives us enough space to do what we want later.
	333	*
	334	* Next, socfpgaimage_set_header() is called.
	335	* We fix up the buffer by moving the image to the start of the buffer.
	336	* We now have some room to do what we need (add CRC and padding).
	337	*/
	338
	339	static int data_size;
832472a9	340
cece78fa MV	341	static int sfp_fake_header_size(unsigned int size, uint8_t ver)
	342	{
	343	return sfp_pad_size(ver) - size;
	344	}
	345
	346	static int sfp_vrec_header(struct image_tool_params *params,
	347	struct image_type_params *tparams, uint8_t ver)
832472a9 CM	348	{
	349	struct stat sbuf;
	350
	351	if (params->datafile &&
	352	stat(params->datafile, &sbuf) == 0 &&
cece78fa	353	sbuf.st_size <= (sfp_pad_size(ver) - sizeof(uint32_t))) {
832472a9	354	data_size = sbuf.st_size;
cece78fa	355	tparams->header_size = sfp_fake_header_size(data_size, ver);
832472a9 CM	356	}
832472a9 CM	357	return 0;
cece78fa	358
832472a9 CM	359	}
832472a9 CM	360
cece78fa MV	361	static int socfpgaimage_vrec_header_v0(struct image_tool_params *params,
	362	struct image_type_params *tparams)
	363	{
	364	return sfp_vrec_header(params, tparams, 0);
	365	}
	366
	367	static int socfpgaimage_vrec_header_v1(struct image_tool_params *params,
	368	struct image_type_params *tparams)
	369	{
	370	return sfp_vrec_header(params, tparams, 1);
	371	}
	372
1d0dc5bc LFT	373	static void sfp_set_header(void *ptr, unsigned char ver,
1d0dc5bc LFT	374	struct image_tool_params *params)
832472a9 CM	375	{
	376	uint8_t buf = (uint8_t )ptr;
	377
	378	/*
	379	* This function is called after vrec_header() has been called.
cece78fa MV	380	* At this stage we have the sfp_fake_header_size() dummy bytes
cece78fa MV	381	* followed by data_size image bytes. Total = sfp_pad_size().
832472a9 CM	382	* We need to fix the buffer by moving the image bytes back to
	383	* the beginning of the buffer, then actually do the signing stuff...
	384	*/
cece78fa MV	385	memmove(buf, buf + sfp_fake_header_size(data_size, ver), data_size);
	386	memset(buf + data_size, 0, sfp_fake_header_size(data_size, ver));
	387
1d0dc5bc	388	sfp_sign_buffer(buf, ver, 0, data_size, 0, params);
cece78fa	389	}
832472a9	390
cece78fa MV	391	static void socfpgaimage_set_header_v0(void ptr, struct stat sbuf, int ifd,
	392	struct image_tool_params *params)
	393	{
1d0dc5bc	394	sfp_set_header(ptr, 0, params);
cece78fa MV	395	}
	396
	397	static void socfpgaimage_set_header_v1(void ptr, struct stat sbuf, int ifd,
	398	struct image_tool_params *params)
	399	{
1d0dc5bc	400	sfp_set_header(ptr, 1, params);
832472a9 CM	401	}
832472a9 CM	402
a93648d1 GMF	403	U_BOOT_IMAGE_TYPE(
a93648d1 GMF	404	socfpgaimage,
cece78fa MV	405	"Altera SoCFPGA Cyclone V / Arria V image support",
	406	0, /* This will be modified by vrec_header() */
	407	(void *)buffer_v0,
963e17ab	408	socfpgaimage_check_params_v0,
cece78fa MV	409	socfpgaimage_verify_header,
	410	socfpgaimage_print_header,
	411	socfpgaimage_set_header_v0,
	412	NULL,
	413	socfpgaimage_check_image_types_v0,
	414	NULL,
	415	socfpgaimage_vrec_header_v0
	416	);
	417
	418	U_BOOT_IMAGE_TYPE(
	419	socfpgaimage_v1,
	420	"Altera SoCFPGA Arria10 image support",
a93648d1	421	0, /* This will be modified by vrec_header() */
cece78fa	422	(void *)buffer_v1,
963e17ab	423	socfpgaimage_check_params_v1,
a93648d1 GMF	424	socfpgaimage_verify_header,
a93648d1 GMF	425	socfpgaimage_print_header,
cece78fa	426	socfpgaimage_set_header_v1,
a93648d1	427	NULL,
cece78fa	428	socfpgaimage_check_image_types_v1,
a93648d1	429	NULL,
cece78fa	430	socfpgaimage_vrec_header_v1
a93648d1	431	);