[J-u-boot.git] / include / configs / pm9261.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuation settings for the RONETIX PM9261 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */

#include <asm/hardware.h>
/* ARM asynchronous clock */

#define MASTER_PLL_DIV		15
#define MASTER_PLL_MUL		162
#define MAIN_PLL_DIV		2
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000

/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_PLLXR_OUT(3) |						\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_MCKR_CSS_SLOW |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_MCKR_CSS_PLLA |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000

/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_3 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (1 <<  8) |		/* Write Recovery Delay */		\
		 (7 << 12) |		/* Row Cycle Delay */			\
		 (3 << 16) |		/* Row Precharge Delay */		\
		 (2 << 20) |		/* Row to Column Delay */		\
		 (5 << 24) |		/* Active to Precharge Delay */		\
		 (1 << 28))		/* Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |					\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

/* SDRAM */
#define PHYS_SDRAM				0x20000000
#define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */

/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)

/* NOR flash */
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1

/* USB */
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		"fbcon=rotate:3 "				\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
32949232 II	2	/*
32949232 II	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <[email protected]>
32949232 II	5	* Lead Tech Design <www.leadtechdesign.com>
	6	* Ilko Iliev <www.ronetix.at>
	7	*
	8	* Configuation settings for the RONETIX PM9261 board.
32949232 II	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
f47316a8 AD	14	/*
	15	* SoC must be defined first, before hardware.h is included.
	16	* In this case SoC is defined in boards.cfg.
	17	*/
	18
	19	#include <asm/hardware.h>
32949232	20	/* ARM asynchronous clock */
32949232	21
32949232 II	22	#define MASTER_PLL_DIV 15
	23	#define MASTER_PLL_MUL 162
	24	#define MAIN_PLL_DIV 2
f47316a8	25	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
7c966a8b	26	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
32949232	27
32949232 II	28	/* clocks */
	29	/* CKGR_MOR - enable main osc. */
	30	#define CONFIG_SYS_MOR_VAL \
e3150c77	31	(AT91_PMC_MOR_MOSCEN \| \
32949232 II	32	(255 << 8)) /* Main Oscillator Start-up Time */
32949232 II	33	#define CONFIG_SYS_PLLAR_VAL \
e3150c77 AD	34	(AT91_PMC_PLLAR_29 \| /* Bit 29 must be 1 when prog */ \
e3150c77 AD	35	AT91_PMC_PLLXR_OUT(3) \| \
32949232 II	36	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	37
	38	/* PCK/2 = MCK Master Clock from PLLA */
	39	#define CONFIG_SYS_MCKR1_VAL \
e3150c77 AD	40	(AT91_PMC_MCKR_CSS_SLOW \| \
e3150c77 AD	41	AT91_PMC_MCKR_PRES_1 \| \
7ac2e7c1	42	AT91_PMC_MCKR_MDIV_2)
32949232 II	43
	44	/* PCK/2 = MCK Master Clock from PLLA */
	45	#define CONFIG_SYS_MCKR2_VAL \
e3150c77 AD	46	(AT91_PMC_MCKR_CSS_PLLA \| \
e3150c77 AD	47	AT91_PMC_MCKR_PRES_1 \| \
7ac2e7c1	48	AT91_PMC_MCKR_MDIV_2)
32949232 II	49
	50	/* define PDC[31:16] as DATA[31:16] */
	51	#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
	52	/* no pull-up for D[31:16] */
	53	#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
	54
	55	/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
	56	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
e3150c77	57	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_EBI_CS1A)
32949232 II	58
	59	/* SDRAM */
	60	/* SDRAMC_MR Mode register */
	61	#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
	62	/* SDRAMC_TR - Refresh Timer register */
	63	#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
	64	/* SDRAMC_CR - Configuration register*/
	65	#define CONFIG_SYS_SDRC_CR_VAL \
	66	(AT91_SDRAMC_NC_9 \| \
	67	AT91_SDRAMC_NR_13 \| \
	68	AT91_SDRAMC_NB_4 \| \
	69	AT91_SDRAMC_CAS_3 \| \
	70	AT91_SDRAMC_DBW_32 \| \
	71	(1 << 8) \| /* Write Recovery Delay */ \
	72	(7 << 12) \| /* Row Cycle Delay */ \
	73	(3 << 16) \| /* Row Precharge Delay */ \
	74	(2 << 20) \| /* Row to Column Delay */ \
	75	(5 << 24) \| /* Active to Precharge Delay */ \
	76	(1 << 28)) /* Exit Self Refresh to Active Delay */
	77
	78	/* Memory Device Register -> SDRAM */
	79	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	80	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
	81	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
	82	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
	83	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	84	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	85	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	86	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	87	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	88	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	89	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	90	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
	91	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
	92	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
	93	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
	94	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	95	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	96	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	97
	98	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
	99	#define CONFIG_SYS_SMC0_SETUP0_VAL \
e3150c77 AD	100	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
e3150c77 AD	101	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
32949232	102	#define CONFIG_SYS_SMC0_PULSE0_VAL \
e3150c77 AD	103	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
e3150c77 AD	104	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
32949232	105	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
e3150c77	106	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
32949232	107	#define CONFIG_SYS_SMC0_MODE0_VAL \
e3150c77 AD	108	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	109	AT91_SMC_MODE_DBW_16 \| \
	110	AT91_SMC_MODE_TDF \| \
	111	AT91_SMC_MODE_TDF_CYCLE(6))
32949232 II	112
	113	/* user reset enable */
	114	#define CONFIG_SYS_RSTC_RMR_VAL \
	115	(AT91_RSTC_KEY \| \
e3150c77 AD	116	AT91_RSTC_CR_PROCRST \| \
	117	AT91_RSTC_MR_ERSTL(1) \| \
	118	AT91_RSTC_MR_ERSTL(2))
32949232 II	119
	120	/* Disable Watchdog */
	121	#define CONFIG_SYS_WDTC_WDMR_VAL \
e3150c77 AD	122	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	123	AT91_WDT_MR_WDV(0xfff) \| \
	124	AT91_WDT_MR_WDDIS \| \
	125	AT91_WDT_MR_WDD(0xfff))
32949232	126
32949232	127	/* SDRAM */
32949232 II	128	#define PHYS_SDRAM 0x20000000
	129	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	130
32949232	131	/* NAND flash */
32949232 II	132	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	133	#define CONFIG_SYS_NAND_BASE 0x40000000
	134	#define CONFIG_SYS_NAND_DBW_8 1
	135	/* our ALE is AD22 */
	136	#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
	137	/* our CLE is AD21 */
	138	#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
ac45bb16 AB	139	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
ac45bb16 AB	140	#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
32949232	141
32949232	142	/* NOR flash */
32949232 II	143	#define PHYS_FLASH_1 0x10000000
32949232 II	144	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
32949232	145
32949232	146	/* USB */
32949232	147	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
32949232	148
32949232	149	#define CONFIG_EXTRA_ENV_SETTINGS \
32949232 II	150	"partition=nand0,0\0" \
	151	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	152	"nfsargs=setenv bootargs root=/dev/nfs rw " \
36a4dae1	153	"fbcon=rotate:3 " \
32949232 II	154	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	155	"addip=setenv bootargs $(bootargs) " \
	156	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	157	":$(hostname):eth0:off\0" \
	158	"ramboot=tftpboot 0x22000000 vmImage;" \
	159	"run ramargs;run addip;bootm 22000000\0" \
	160	"nfsboot=tftpboot 0x22000000 vmImage;" \
	161	"run nfsargs;run addip;bootm 22000000\0" \
	162	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	163	""
32949232	164
4f81bf43	165	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
4f81bf43	166
32949232	167	#endif