[J-u-boot.git] / include / fsl_mdio.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
 *	Jun-jie Zhang <[email protected]>
 *	Mingkai Hu <[email protected]>
 */

#ifndef __FSL_PHY_H__
#define __FSL_PHY_H__

#include <net.h>
#include <miiphy.h>

struct tsec_mii_mng {
	u32 miimcfg;		/* MII management configuration reg */
	u32 miimcom;		/* MII management command reg */
	u32 miimadd;		/* MII management address reg */
	u32 miimcon;		/* MII management control reg */
	u32 miimstat;		/* MII management status reg  */
	u32 miimind;		/* MII management indication reg */
	u32 ifstat;		/* Interface Status Register */
};

int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);

/* PHY register offsets */
#define PHY_EXT_PAGE_ACCESS	0x1f

/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT		0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT	0x00000007
#define MIIMCFG_INIT_VALUE		0x00000003

/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE	0x00000001
#define MIIMCOM_SCAN_CYCLE	0x00000002

/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT	8

/* MII Management Indicator Register */
#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004

void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
		int dev_addr, int reg, int value);
int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
		int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
		u16 value);
int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum, u16 value);
int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum);
int memac_mdio_reset(struct mii_dev *bus);

struct fsl_pq_mdio_data {
	u32 mdio_regs_off;
};

struct fsl_pq_mdio_info {
	struct tsec_mii_mng __iomem *regs;
	char *name;
};
int fsl_pq_mdio_init(struct bd_info *bis, struct fsl_pq_mdio_info *info);

#endif /* __FSL_PHY_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
063c1263	2	/*
5be00a01	3	* Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
063c1263 AF	4	* Jun-jie Zhang <[email protected]>
063c1263 AF	5	* Mingkai Hu <[email protected]>
063c1263	6	*/
9872b736	7
063c1263 AF	8	#ifndef __FSL_PHY_H__
	9	#define __FSL_PHY_H__
	10
	11	#include <net.h>
	12	#include <miiphy.h>
93f26f13 CM	13
	14	struct tsec_mii_mng {
	15	u32 miimcfg; /* MII management configuration reg */
	16	u32 miimcom; /* MII management command reg */
	17	u32 miimadd; /* MII management address reg */
	18	u32 miimcon; /* MII management control reg */
	19	u32 miimstat; /* MII management status reg */
	20	u32 miimind; /* MII management indication reg */
	21	u32 ifstat; /* Interface Status Register */
	22	};
	23
	24	int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
063c1263 AF	25
	26	/* PHY register offsets */
	27	#define PHY_EXT_PAGE_ACCESS 0x1f
	28
	29	/* MII Management Configuration Register */
9872b736 BM	30	#define MIIMCFG_RESET_MGMT 0x80000000
	31	#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
	32	#define MIIMCFG_INIT_VALUE 0x00000003
063c1263 AF	33
	34	/* MII Management Command Register */
	35	#define MIIMCOM_READ_CYCLE 0x00000001
	36	#define MIIMCOM_SCAN_CYCLE 0x00000002
	37
	38	/* MII Management Address Register */
	39	#define MIIMADD_PHY_ADDR_SHIFT 8
	40
	41	/* MII Management Indicator Register */
	42	#define MIIMIND_BUSY 0x00000001
	43	#define MIIMIND_NOTVALID 0x00000004
	44
5be00a01	45	void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
063c1263	46	int dev_addr, int reg, int value);
5be00a01	47	int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
063c1263 AF	48	int dev_addr, int regnum);
	49	int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
	50	int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
	51	u16 value);
111fd19e RZ	52	int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
	53	int regnum, u16 value);
	54	int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
	55	int regnum);
6eb32a03	56	int memac_mdio_reset(struct mii_dev *bus);
063c1263	57
16c53ce7 HZ	58	struct fsl_pq_mdio_data {
	59	u32 mdio_regs_off;
	60	};
	61
063c1263	62	struct fsl_pq_mdio_info {
5be00a01	63	struct tsec_mii_mng __iomem *regs;
063c1263 AF	64	char *name;
063c1263 AF	65	};
b75d8dc5	66	int fsl_pq_mdio_init(struct bd_info bis, struct fsl_pq_mdio_info info);
063c1263 AF	67
063c1263 AF	68	#endif /* __FSL_PHY_H__ */