[J-u-boot.git] / arch / arm / dts / meson-gxl-mali.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 BayLibre SAS
 * Author: Neil Armstrong <[email protected]>
 */

&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_GP0_PLL>,
				  <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <0>, /* Do Nothing */
					 <&clkc CLKID_GP0_PLL>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <744000000>,
				       <0>, /* Do Nothing */
				       <744000000>,
				       <0>; /* Do Nothing */
	};
};
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
48622156 NA	2	/*
	3	* Copyright (c) 2017 BayLibre SAS
	4	* Author: Neil Armstrong <[email protected]>
48622156 NA	5	*/
	6
	7	&apb {
	8	mali: gpu@c0000 {
8973d816	9	compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
48622156 NA	10	reg = <0x0 0xc0000 0x0 0x40000>;
	11	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	12	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	13	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	14	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	15	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	16	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	17	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	18	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	19	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	20	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	21	interrupt-names = "gp", "gpmmu", "pp", "pmu",
	22	"pp0", "ppmmu0", "pp1", "ppmmu1",
	23	"pp2", "ppmmu2";
	24	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
	25	clock-names = "bus", "core";
	26
	27	/*
	28	* Mali clocking is provided by two identical clock paths
	29	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	30	* free mux to safely change frequency while running.
	31	*/
5b3da7fa NA	32	assigned-clocks = <&clkc CLKID_GP0_PLL>,
5b3da7fa NA	33	<&clkc CLKID_MALI_0_SEL>,
48622156 NA	34	<&clkc CLKID_MALI_0>,
48622156 NA	35	<&clkc CLKID_MALI>; /* Glitch free mux */
5b3da7fa NA	36	assigned-clock-parents = <0>, /* Do Nothing */
5b3da7fa NA	37	<&clkc CLKID_GP0_PLL>,
48622156 NA	38	<0>, /* Do Nothing */
48622156 NA	39	<&clkc CLKID_MALI_0>;
5b3da7fa NA	40	assigned-clock-rates = <744000000>,
	41	<0>, /* Do Nothing */
	42	<744000000>,
48622156 NA	43	<0>; /* Do Nothing */
	44	};
	45	};