projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 11504cf5 | 1 | CONFIG_ARM=y |
| abf8d963 | 2 | CONFIG_COUNTER_FREQUENCY=25000000 |
| 11504cf5 MT |
3 | CONFIG_TARGET_LS1046AFRWY=y |
| 4 | CONFIG_TFABOOT=y | |
| 98463903 | 5 | CONFIG_TEXT_BASE=0x82000000 |
| 9802154a | 6 | CONFIG_SYS_MALLOC_LEN=0x102000 |
| 554e5514 | 7 | CONFIG_NR_DRAM_BANKS=2 |
| 11504cf5 | 8 | CONFIG_ENV_SIZE=0x2000 |
| f7d0ae9c | 9 | CONFIG_DM_GPIO=y |
| 2bba7807 | 10 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" |
| 11504cf5 | 11 | CONFIG_QSPI_AHB_INIT=y |
| 11504cf5 MT |
12 | CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y |
| 13 | CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y | |
| 14 | CONFIG_AHCI=y | |
| a552ffc9 TR |
15 | CONFIG_NXP_ESBC=y |
| 16 | CONFIG_LAYERSCAPE_NS_ACCESS=y | |
| 3dc2987f TR |
17 | CONFIG_PCIE1=y |
| 18 | CONFIG_PCIE2=y | |
| 19 | CONFIG_PCIE3=y | |
| a552ffc9 | 20 | CONFIG_FSL_USE_PCA9547_MUX=y |
| 11504cf5 | 21 | CONFIG_DISTRO_DEFAULTS=y |
| a8c281d4 | 22 | CONFIG_REMAKE_ELF=y |
| 54c5c2b8 | 23 | CONFIG_MP=y |
| 11504cf5 MT |
24 | CONFIG_FIT_VERBOSE=y |
| 25 | CONFIG_OF_BOARD_SETUP=y | |
| 26 | CONFIG_USE_BOOTARGS=y | |
| 27 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" | |
| 28 | CONFIG_MISC_INIT_R=y | |
| cf493582 | 29 | CONFIG_SYS_MAXARGS=64 |
| d0ee7f29 | 30 | CONFIG_SYS_PBSIZE=532 |
| 88cd7d0e | 31 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 |
| 11504cf5 MT |
32 | CONFIG_CMD_GPT=y |
| 33 | CONFIG_CMD_I2C=y | |
| 34 | CONFIG_CMD_MMC=y | |
| 35 | CONFIG_CMD_NAND=y | |
| 36 | CONFIG_CMD_PCI=y | |
| 37 | CONFIG_CMD_USB=y | |
| 38 | CONFIG_CMD_CACHE=y | |
| 11504cf5 MT |
39 | CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" |
| 40 | CONFIG_OF_CONTROL=y | |
| 7679afbf | 41 | CONFIG_ENV_OVERWRITE=y |
| 11504cf5 | 42 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 0e14cdfa TR |
43 | CONFIG_USE_ETHPRIME=y |
| 44 | CONFIG_ETHPRIME="FM1@DTSEC3" | |
| 6edb5dd3 | 45 | CONFIG_SATA=y |
| 11504cf5 | 46 | CONFIG_SATA_CEVA=y |
| 95372165 | 47 | # CONFIG_DDR_SPD is not set |
| f76750d1 | 48 | CONFIG_MPC8XXX_GPIO=y |
| f7d0ae9c | 49 | CONFIG_DM_I2C=y |
| fc8d3b9a | 50 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
| c9f85187 | 51 | CONFIG_SYS_FSL_SEC_MON_BE=y |
| 88cd7d0e | 52 | CONFIG_SYS_I2C_EEPROM_ADDR=0x52 |
| 11504cf5 MT |
53 | CONFIG_FSL_ESDHC=y |
| 54 | CONFIG_MTD=y | |
| 55 | CONFIG_MTD_RAW_NAND=y | |
| 53f06134 | 56 | CONFIG_NAND_FSL_IFC=y |
| c0ad62c5 | 57 | CONFIG_SYS_NAND_ONFI_DETECTION=y |
| 11504cf5 MT |
58 | # CONFIG_SPI_FLASH_BAR is not set |
| 59 | CONFIG_SPI_FLASH_STMICRO=y | |
| 60 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set | |
| 61 | CONFIG_PHYLIB=y | |
| 62 | CONFIG_PHY_VITESSE=y | |
| 63 | CONFIG_PHY_GIGE=y | |
| 64 | CONFIG_E1000=y | |
| 7d080773 | 65 | CONFIG_FMAN_ENET=y |
| 380e32b1 | 66 | CONFIG_SYS_FMAN_FW_ADDR=0x900000 |
| 11504cf5 | 67 | CONFIG_PCI=y |
| 11504cf5 | 68 | CONFIG_DM_PCI_COMPAT=y |
| 11504cf5 | 69 | CONFIG_DM_SCSI=y |
| 9591b635 | 70 | CONFIG_SYS_NS16550_SERIAL=y |
| 11504cf5 MT |
71 | CONFIG_SPI=y |
| 72 | CONFIG_DM_SPI=y | |
| 73 | CONFIG_FSL_QSPI=y | |
| 74 | CONFIG_USB=y | |
| 11504cf5 MT |
75 | CONFIG_USB_XHCI_HCD=y |
| 76 | CONFIG_USB_XHCI_DWC3=y | |
| 77 | CONFIG_USB_HOST_ETHER=y | |
| 78 | CONFIG_USB_ETHER_ASIX=y | |
| 79 | CONFIG_USB_ETHER_ASIX88179=y | |
| 80 | CONFIG_USB_ETHER_RTL8152=y | |
| 11504cf5 | 81 | CONFIG_RSA=y |