projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9d7ed339 | 1 | CONFIG_ARM=y |
| a2ac2b96 | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| abf8d963 | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| 9d7ed339 | 4 | CONFIG_ARCH_ROCKCHIP=y |
| 98463903 | 5 | CONFIG_TEXT_BASE=0x00200000 |
| 554e5514 | 6 | CONFIG_NR_DRAM_BANKS=1 |
| 052170c6 | 7 | CONFIG_ENV_OFFSET=0x3F8000 |
| 2bba7807 | 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb" |
| 9d7ed339 | 9 | CONFIG_ROCKCHIP_RK3368=y |
| 32a238df | 10 | CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds" |
| 259afb16 KY |
11 | CONFIG_TPL_LIBCOMMON_SUPPORT=y |
| 12 | CONFIG_TPL_LIBGENERIC_SUPPORT=y | |
| 9ca00684 | 13 | CONFIG_SPL_DRIVERS_MISC=y |
| 9d7ed339 | 14 | CONFIG_TARGET_EVB_PX5=y |
| 259afb16 KY |
15 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| 16 | CONFIG_SPL=y | |
| 358b6a20 TR |
17 | CONFIG_DEBUG_UART_BASE=0xFF1c0000 |
| 18 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
| 259afb16 | 19 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| ea2ca7e1 | 20 | CONFIG_SPL_SPI=y |
| 49c8ef0e | 21 | CONFIG_SYS_LOAD_ADDR=0x800800 |
| d46e86d2 | 22 | CONFIG_DEBUG_UART=y |
| eaf6ea6a TR |
23 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 24 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 | |
| df35f453 | 25 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 259afb16 KY |
26 | CONFIG_FIT=y |
| 27 | CONFIG_FIT_VERBOSE=y | |
| 28 | CONFIG_SPL_LOAD_FIT=y | |
| 259afb16 KY |
29 | CONFIG_BOOTSTAGE=y |
| 30 | CONFIG_SPL_BOOTSTAGE=y | |
| 31 | CONFIG_BOOTSTAGE_REPORT=y | |
| 32 | CONFIG_BOOTSTAGE_FDT=y | |
| a2a5053a | 33 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" |
| 9d7ed339 | 34 | # CONFIG_DISPLAY_CPUINFO is not set |
| 78eba69d | 35 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 9d7ed339 | 36 | CONFIG_ARCH_EARLY_INIT_R=y |
| ca8a329a TR |
37 | CONFIG_SPL_MAX_SIZE=0x40000 |
| 38 | CONFIG_SPL_PAD_TO=0x7f8000 | |
| 6600b355 TR |
39 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 40 | CONFIG_SPL_BSS_START_ADDR=0x400000 | |
| 9b5f9aeb | 41 | CONFIG_SPL_BSS_MAX_SIZE=0x20000 |
| 259afb16 | 42 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 861e48e8 | 43 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| f113d7d3 TR |
44 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 45 | CONFIG_SPL_STACK=0x188000 | |
| 259afb16 KY |
46 | CONFIG_SPL_STACK_R=y |
| 47 | CONFIG_SPL_ATF=y | |
| 48 | CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y | |
| 49 | CONFIG_TPL=y | |
| 41e47b42 | 50 | CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
| 9d7ed339 AY |
51 | CONFIG_CMD_MMC=y |
| 52 | CONFIG_CMD_CACHE=y | |
| 259afb16 KY |
53 | CONFIG_SPL_OF_CONTROL=y |
| 54 | CONFIG_TPL_OF_CONTROL=y | |
| 55 | CONFIG_OF_LIVE=y | |
| 259afb16 KY |
56 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" |
| 57 | CONFIG_TPL_OF_PLATDATA=y | |
| 58 | CONFIG_ENV_IS_IN_MMC=y | |
| 8d8ee47e | 59 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 1b8114ac | 60 | # CONFIG_NET is not set |
| 259afb16 | 61 | CONFIG_TPL_DM=y |
| 9d7ed339 | 62 | CONFIG_REGMAP=y |
| 259afb16 KY |
63 | CONFIG_SPL_REGMAP=y |
| 64 | CONFIG_TPL_REGMAP=y | |
| 9d7ed339 | 65 | CONFIG_SYSCON=y |
| 259afb16 KY |
66 | CONFIG_SPL_SYSCON=y |
| 67 | CONFIG_TPL_SYSCON=y | |
| 9d7ed339 | 68 | CONFIG_CLK=y |
| 259afb16 KY |
69 | CONFIG_SPL_CLK=y |
| 70 | CONFIG_TPL_CLK=y | |
| 9d7ed339 AY |
71 | CONFIG_MMC_DW=y |
| 72 | CONFIG_MMC_DW_ROCKCHIP=y | |
| 73 | CONFIG_PINCTRL=y | |
| 259afb16 | 74 | CONFIG_SPL_PINCTRL=y |
| 9d7ed339 | 75 | CONFIG_RAM=y |
| 259afb16 KY |
76 | CONFIG_SPL_RAM=y |
| 77 | CONFIG_TPL_RAM=y | |
| 78 | CONFIG_DM_RESET=y | |
| 9d7ed339 | 79 | CONFIG_DEBUG_UART_SHIFT=2 |
| 9d7ed339 | 80 | CONFIG_DEBUG_UART_SKIP_INIT=y |
| 9591b635 | 81 | CONFIG_SYS_NS16550_MEM32=y |
| 9d7ed339 | 82 | CONFIG_SYSRESET=y |
| 259afb16 KY |
83 | CONFIG_PANIC_HANG=y |
| 84 | CONFIG_SPL_TINY_MEMSET=y | |
| 85 | CONFIG_TPL_TINY_MEMSET=y | |
| 9d7ed339 | 86 | CONFIG_ERRNO_STR=y |