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4ceb5c6d MW |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | ||
3 | #ifndef __SL28_H | |
4 | #define __SL28_H | |
5 | ||
6 | #include <asm/arch/stream_id_lsch3.h> | |
7 | #include <asm/arch/config.h> | |
8 | #include <asm/arch/soc.h> | |
9 | ||
10 | /* we don't use hwconfig but this has to be defined.. */ | |
11 | #define HWCONFIG_BUFFER_SIZE 256 | |
12 | ||
13 | /* we don't have secure memory unless we have a BL31 */ | |
14 | #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT | |
15 | #undef CONFIG_SYS_MEM_RESERVE_SECURE | |
16 | #endif | |
17 | ||
18 | /* DDR */ | |
4ceb5c6d MW |
19 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
20 | ||
21 | #define CONFIG_VERY_BIG_RAM | |
22 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
23 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
24 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
25 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
26 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
27 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL | |
28 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 | |
29 | ||
30 | /* early stack pointer */ | |
31 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) | |
32 | ||
33 | /* memtest command */ | |
34 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
35 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
36 | ||
37 | /* SMP */ | |
38 | #define CPU_RELEASE_ADDR secondary_boot_addr | |
39 | ||
40 | /* generic timer */ | |
41 | #define COUNTER_FREQUENCY 25000000 | |
42 | ||
43 | /* size of malloc() pool */ | |
44 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) | |
45 | ||
46 | /* early heap for SPL DM */ | |
47 | #define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE | |
48 | ||
49 | /* serial port */ | |
4ceb5c6d MW |
50 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) |
51 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
52 | ||
53 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
4ceb5c6d MW |
54 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) |
55 | ||
4ceb5c6d MW |
56 | /* ethernet */ |
57 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
58 | ||
59 | /* SPL */ | |
60 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
61 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 | |
62 | #define CONFIG_SPL_MAX_SIZE 0x20000 | |
63 | #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) | |
64 | ||
65 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 | |
66 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
67 | #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) | |
68 | ||
69 | /* environment */ | |
70 | /* see include/configs/ti_armv7_common.h */ | |
71 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
72 | #define ENV_MEM_LAYOUT_SETTINGS \ | |
73 | "loadaddr=0x82000000\0" \ | |
74 | "kernel_addr_r=0x82000000\0" \ | |
75 | "fdt_addr_r=0x88000000\0" \ | |
76 | "bootm_size=0x10000000\0" \ | |
77 | "pxefile_addr_r=0x80100000\0" \ | |
78 | "scriptaddr=0x80000000\0" \ | |
79 | "ramdisk_addr_r=0x88080000\0" | |
80 | ||
81 | #define BOOT_TARGET_DEVICES(func) \ | |
4ceb5c6d | 82 | func(MMC, mmc, 0) \ |
e668bec9 | 83 | func(MMC, mmc, 1) \ |
4ceb5c6d MW |
84 | func(NVME, nvme, 0) \ |
85 | func(USB, usb, 0) \ | |
805b2423 | 86 | func(SCSI, scsi, 0) \ |
4ceb5c6d MW |
87 | func(DHCP, dhcp, 0) \ |
88 | func(PXE, pxe, 0) | |
89 | #include <config_distro_bootcmd.h> | |
90 | ||
91 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
92 | "env_addr=0x203e0004\0" \ | |
93 | "envload=env import -d -b ${env_addr}\0" \ | |
94 | "install_rcw=source 20200000\0" \ | |
95 | "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \ | |
96 | ENV_MEM_LAYOUT_SETTINGS \ | |
97 | BOOTENV | |
98 | ||
99 | #endif /* __SL28_H */ |