[J-u-boot.git] / drivers / net / pch_gbe.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2015, Bin Meng <[email protected]>
 *
 * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
 * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
 */

#ifndef _PCH_GBE_H_
#define _PCH_GBE_H_

#define PCH_GBE_TIMEOUT		(3 * CONFIG_SYS_HZ)

#define PCH_GBE_DESC_NUM	4
#define PCH_GBE_ALIGN_SIZE	64

/*
 * Topcliff GBE MAC supports receiving ethernet frames with normal frame size
 * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
 * register bit to turn off receiving 'jumbo frame', so we have to allocate
 * our own buffer to store the received frames instead of using U-Boot's own.
 */
#define PCH_GBE_RX_FRAME_LEN	ROUND(10318, PCH_GBE_ALIGN_SIZE)

/* Interrupt Status */
/* Interrupt Status Hold */
/* Interrupt Enable */
#define PCH_GBE_INT_RX_DMA_CMPLT	0x00000001
#define PCH_GBE_INT_RX_VALID		0x00000002
#define PCH_GBE_INT_RX_FRAME_ERR	0x00000004
#define PCH_GBE_INT_RX_FIFO_ERR		0x00000008
#define PCH_GBE_INT_RX_DMA_ERR		0x00000010
#define PCH_GBE_INT_RX_DSC_EMP		0x00000020
#define PCH_GBE_INT_TX_CMPLT		0x00000100
#define PCH_GBE_INT_TX_DMA_CMPLT	0x00000200
#define PCH_GBE_INT_TX_FIFO_ERR		0x00000400
#define PCH_GBE_INT_TX_DMA_ERR		0x00000800
#define PCH_GBE_INT_PAUSE_CMPLT		0x00001000
#define PCH_GBE_INT_MIIM_CMPLT		0x00010000
#define PCH_GBE_INT_PHY_INT		0x00100000
#define PCH_GBE_INT_WOL_DET		0x01000000
#define PCH_GBE_INT_TCPIP_ERR		0x10000000

/* Mode */
#define PCH_GBE_MODE_MII_ETHER		0x00000000
#define PCH_GBE_MODE_GMII_ETHER		0x80000000
#define PCH_GBE_MODE_HALF_DUPLEX	0x00000000
#define PCH_GBE_MODE_FULL_DUPLEX	0x40000000
#define PCH_GBE_MODE_FR_BST		0x04000000

/* Reset */
#define PCH_GBE_ALL_RST			0x80000000
#define PCH_GBE_TX_RST			0x00008000
#define PCH_GBE_RX_RST			0x00004000

/* TCP/IP Accelerator Control */
#define PCH_GBE_EX_LIST_EN		0x00000008
#define PCH_GBE_RX_TCPIPACC_OFF		0x00000004
#define PCH_GBE_TX_TCPIPACC_EN		0x00000002
#define PCH_GBE_RX_TCPIPACC_EN		0x00000001

/* MAC RX Enable */
#define PCH_GBE_MRE_MAC_RX_EN		0x00000001

/* RX Flow Control */
#define PCH_GBE_FL_CTRL_EN		0x80000000

/* RX Mode */
#define PCH_GBE_ADD_FIL_EN		0x80000000
#define PCH_GBE_MLT_FIL_EN		0x40000000
#define PCH_GBE_RH_ALM_EMP_4		0x00000000
#define PCH_GBE_RH_ALM_EMP_8		0x00004000
#define PCH_GBE_RH_ALM_EMP_16		0x00008000
#define PCH_GBE_RH_ALM_EMP_32		0x0000c000
#define PCH_GBE_RH_ALM_FULL_4		0x00000000
#define PCH_GBE_RH_ALM_FULL_8		0x00001000
#define PCH_GBE_RH_ALM_FULL_16		0x00002000
#define PCH_GBE_RH_ALM_FULL_32		0x00003000
#define PCH_GBE_RH_RD_TRG_4		0x00000000
#define PCH_GBE_RH_RD_TRG_8		0x00000200
#define PCH_GBE_RH_RD_TRG_16		0x00000400
#define PCH_GBE_RH_RD_TRG_32		0x00000600
#define PCH_GBE_RH_RD_TRG_64		0x00000800
#define PCH_GBE_RH_RD_TRG_128		0x00000a00
#define PCH_GBE_RH_RD_TRG_256		0x00000c00
#define PCH_GBE_RH_RD_TRG_512		0x00000e00

/* TX Mode */
#define PCH_GBE_TM_NO_RTRY		0x80000000
#define PCH_GBE_TM_LONG_PKT		0x40000000
#define PCH_GBE_TM_ST_AND_FD		0x20000000
#define PCH_GBE_TM_SHORT_PKT		0x10000000
#define PCH_GBE_TM_LTCOL_RETX		0x08000000
#define PCH_GBE_TM_TH_TX_STRT_4		0x00000000
#define PCH_GBE_TM_TH_TX_STRT_8		0x00004000
#define PCH_GBE_TM_TH_TX_STRT_16	0x00008000
#define PCH_GBE_TM_TH_TX_STRT_32	0x0000c000
#define PCH_GBE_TM_TH_ALM_EMP_4		0x00000000
#define PCH_GBE_TM_TH_ALM_EMP_8		0x00000800
#define PCH_GBE_TM_TH_ALM_EMP_16	0x00001000
#define PCH_GBE_TM_TH_ALM_EMP_32	0x00001800
#define PCH_GBE_TM_TH_ALM_EMP_64	0x00002000
#define PCH_GBE_TM_TH_ALM_EMP_128	0x00002800
#define PCH_GBE_TM_TH_ALM_EMP_256	0x00003000
#define PCH_GBE_TM_TH_ALM_EMP_512	0x00003800
#define PCH_GBE_TM_TH_ALM_FULL_4	0x00000000
#define PCH_GBE_TM_TH_ALM_FULL_8	0x00000200
#define PCH_GBE_TM_TH_ALM_FULL_16	0x00000400
#define PCH_GBE_TM_TH_ALM_FULL_32	0x00000600

/* MAC Address Mask */
#define PCH_GBE_BUSY			0x80000000

/* MIIM  */
#define PCH_GBE_MIIM_OPER_WRITE		0x04000000
#define PCH_GBE_MIIM_OPER_READ		0x00000000
#define PCH_GBE_MIIM_OPER_READY		0x04000000
#define PCH_GBE_MIIM_PHY_ADDR_SHIFT	21
#define PCH_GBE_MIIM_REG_ADDR_SHIFT	16

/* RGMII Control */
#define PCH_GBE_CRS_SEL			0x00000010
#define PCH_GBE_RGMII_RATE_125M		0x00000000
#define PCH_GBE_RGMII_RATE_25M		0x00000008
#define PCH_GBE_RGMII_RATE_2_5M		0x0000000c
#define PCH_GBE_RGMII_MODE_GMII		0x00000000
#define PCH_GBE_RGMII_MODE_RGMII	0x00000002
#define PCH_GBE_CHIP_TYPE_EXTERNAL	0x00000000
#define PCH_GBE_CHIP_TYPE_INTERNAL	0x00000001

/* DMA Control */
#define PCH_GBE_RX_DMA_EN		0x00000002
#define PCH_GBE_TX_DMA_EN		0x00000001

/* Receive Descriptor bit definitions */
#define PCH_GBE_RXD_ACC_STAT_BCAST	0x00000400
#define PCH_GBE_RXD_ACC_STAT_MCAST	0x00000200
#define PCH_GBE_RXD_ACC_STAT_UCAST	0x00000100
#define PCH_GBE_RXD_ACC_STAT_TCPIPOK	0x000000c0
#define PCH_GBE_RXD_ACC_STAT_IPOK	0x00000080
#define PCH_GBE_RXD_ACC_STAT_TCPOK	0x00000040
#define PCH_GBE_RXD_ACC_STAT_IP6ERR	0x00000020
#define PCH_GBE_RXD_ACC_STAT_OFLIST	0x00000010
#define PCH_GBE_RXD_ACC_STAT_TYPEIP	0x00000008
#define PCH_GBE_RXD_ACC_STAT_MACL	0x00000004
#define PCH_GBE_RXD_ACC_STAT_PPPOE	0x00000002
#define PCH_GBE_RXD_ACC_STAT_VTAGT	0x00000001
#define PCH_GBE_RXD_GMAC_STAT_PAUSE	0x0200
#define PCH_GBE_RXD_GMAC_STAT_MARBR	0x0100
#define PCH_GBE_RXD_GMAC_STAT_MARMLT	0x0080
#define PCH_GBE_RXD_GMAC_STAT_MARIND	0x0040
#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT	0x0020
#define PCH_GBE_RXD_GMAC_STAT_TLONG	0x0010
#define PCH_GBE_RXD_GMAC_STAT_TSHRT	0x0008
#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL	0x0004
#define PCH_GBE_RXD_GMAC_STAT_NBLERR	0x0002
#define PCH_GBE_RXD_GMAC_STAT_CRCERR	0x0001

/* Transmit Descriptor bit definitions */
#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF	0x0008
#define PCH_GBE_TXD_CTRL_ITAG		0x0004
#define PCH_GBE_TXD_CTRL_ICRC		0x0002
#define PCH_GBE_TXD_CTRL_APAD		0x0001
#define PCH_GBE_TXD_WORDS_SHIFT		2
#define PCH_GBE_TXD_GMAC_STAT_CMPLT	0x2000
#define PCH_GBE_TXD_GMAC_STAT_ABT	0x1000
#define PCH_GBE_TXD_GMAC_STAT_EXCOL	0x0800
#define PCH_GBE_TXD_GMAC_STAT_SNGCOL	0x0400
#define PCH_GBE_TXD_GMAC_STAT_MLTCOL	0x0200
#define PCH_GBE_TXD_GMAC_STAT_CRSER	0x0100
#define PCH_GBE_TXD_GMAC_STAT_TLNG	0x0080
#define PCH_GBE_TXD_GMAC_STAT_TSHRT	0x0040
#define PCH_GBE_TXD_GMAC_STAT_LTCOL	0x0020
#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW	0x0010

/**
 * struct pch_gbe_rx_desc - Receive Descriptor
 * @buffer_addr:	RX Frame Buffer Address
 * @tcp_ip_status:	TCP/IP Accelerator Status
 * @rx_words_eob:	RX word count and Byte position
 * @gbec_status:	GMAC Status
 * @dma_status:		DMA Status
 * @reserved1:		Reserved
 * @reserved2:		Reserved
 */
struct pch_gbe_rx_desc {
	u32 buffer_addr;
	u32 tcp_ip_status;
	u16 rx_words_eob;
	u16 gbec_status;
	u8 dma_status;
	u8 reserved1;
	u16 reserved2;
};

/**
 * struct pch_gbe_tx_desc - Transmit Descriptor
 * @buffer_addr:	TX Frame Buffer Address
 * @length:		Data buffer length
 * @reserved1:		Reserved
 * @tx_words_eob:	TX word count and Byte position
 * @tx_frame_ctrl:	TX Frame Control
 * @dma_status:		DMA Status
 * @reserved2:		Reserved
 * @gbec_status:	GMAC Status
 */
struct pch_gbe_tx_desc {
	u32 buffer_addr;
	u16 length;
	u16 reserved1;
	u16 tx_words_eob;
	u16 tx_frame_ctrl;
	u8 dma_status;
	u8 reserved2;
	u16 gbec_status;
};

/**
 * pch_gbe_regs_mac_adr - structure holding values of mac address registers
 *
 * @high	Denotes the 1st to 4th byte from the initial of MAC address
 * @low		Denotes the 5th to 6th byte from the initial of MAC address
 */
struct pch_gbe_regs_mac_adr {
	u32 high;
	u32 low;
};

/**
 * pch_gbe_regs - structure holding values of MAC registers
 */
struct pch_gbe_regs {
	u32 int_st;
	u32 int_en;
	u32 mode;
	u32 reset;
	u32 tcpip_acc;
	u32 ex_list;
	u32 int_st_hold;
	u32 phy_int_ctrl;
	u32 mac_rx_en;
	u32 rx_fctrl;
	u32 pause_req;
	u32 rx_mode;
	u32 tx_mode;
	u32 rx_fifo_st;
	u32 tx_fifo_st;
	u32 tx_fid;
	u32 tx_result;
	u32 pause_pkt1;
	u32 pause_pkt2;
	u32 pause_pkt3;
	u32 pause_pkt4;
	u32 pause_pkt5;
	u32 reserve[2];
	struct pch_gbe_regs_mac_adr mac_adr[16];
	u32 addr_mask;
	u32 miim;
	u32 mac_addr_load;
	u32 rgmii_st;
	u32 rgmii_ctrl;
	u32 reserve3[3];
	u32 dma_ctrl;
	u32 reserve4[3];
	u32 rx_dsc_base;
	u32 rx_dsc_size;
	u32 rx_dsc_hw_p;
	u32 rx_dsc_hw_p_hld;
	u32 rx_dsc_sw_p;
	u32 reserve5[3];
	u32 tx_dsc_base;
	u32 tx_dsc_size;
	u32 tx_dsc_hw_p;
	u32 tx_dsc_hw_p_hld;
	u32 tx_dsc_sw_p;
	u32 reserve6[3];
	u32 rx_dma_st;
	u32 tx_dma_st;
	u32 reserve7[2];
	u32 wol_st;
	u32 wol_ctrl;
	u32 wol_addr_mask;
};

struct pch_gbe_priv {
	struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
	struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
	char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
	struct phy_device *phydev;
	struct mii_dev *bus;
	struct pch_gbe_regs *mac_regs;
	struct udevice *dev;
	int rx_idx;
	int tx_idx;
};

#endif /* _PCH_GBE_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8ee443b8 BM	2	/*
	3	* Copyright (C) 2015, Bin Meng <[email protected]>
	4	*
	5	* Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
	6	* Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
8ee443b8 BM	7	*/
	8
	9	#ifndef _PCH_GBE_H_
	10	#define _PCH_GBE_H_
	11
	12	#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ)
	13
	14	#define PCH_GBE_DESC_NUM 4
	15	#define PCH_GBE_ALIGN_SIZE 64
	16
	17	/*
	18	* Topcliff GBE MAC supports receiving ethernet frames with normal frame size
	19	* (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
	20	* register bit to turn off receiving 'jumbo frame', so we have to allocate
	21	* our own buffer to store the received frames instead of using U-Boot's own.
	22	*/
	23	#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE)
	24
	25	/* Interrupt Status */
	26	/* Interrupt Status Hold */
	27	/* Interrupt Enable */
	28	#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
	29	#define PCH_GBE_INT_RX_VALID 0x00000002
	30	#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
	31	#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
	32	#define PCH_GBE_INT_RX_DMA_ERR 0x00000010
	33	#define PCH_GBE_INT_RX_DSC_EMP 0x00000020
	34	#define PCH_GBE_INT_TX_CMPLT 0x00000100
	35	#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
	36	#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
	37	#define PCH_GBE_INT_TX_DMA_ERR 0x00000800
	38	#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
	39	#define PCH_GBE_INT_MIIM_CMPLT 0x00010000
	40	#define PCH_GBE_INT_PHY_INT 0x00100000
	41	#define PCH_GBE_INT_WOL_DET 0x01000000
	42	#define PCH_GBE_INT_TCPIP_ERR 0x10000000
	43
	44	/* Mode */
	45	#define PCH_GBE_MODE_MII_ETHER 0x00000000
	46	#define PCH_GBE_MODE_GMII_ETHER 0x80000000
	47	#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
	48	#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
	49	#define PCH_GBE_MODE_FR_BST 0x04000000
	50
	51	/* Reset */
	52	#define PCH_GBE_ALL_RST 0x80000000
	53	#define PCH_GBE_TX_RST 0x00008000
	54	#define PCH_GBE_RX_RST 0x00004000
	55
	56	/* TCP/IP Accelerator Control */
	57	#define PCH_GBE_EX_LIST_EN 0x00000008
	58	#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
	59	#define PCH_GBE_TX_TCPIPACC_EN 0x00000002
	60	#define PCH_GBE_RX_TCPIPACC_EN 0x00000001
	61
	62	/* MAC RX Enable */
	63	#define PCH_GBE_MRE_MAC_RX_EN 0x00000001
	64
	65	/* RX Flow Control */
	66	#define PCH_GBE_FL_CTRL_EN 0x80000000
	67
	68	/* RX Mode */
	69	#define PCH_GBE_ADD_FIL_EN 0x80000000
	70	#define PCH_GBE_MLT_FIL_EN 0x40000000
71	#define PCH_GBE_RH_ALM_EMP_4 0x00000000
72	#define PCH_GBE_RH_ALM_EMP_8 0x00004000
73	#define PCH_GBE_RH_ALM_EMP_16 0x00008000
74	#define PCH_GBE_RH_ALM_EMP_32 0x0000c000
75	#define PCH_GBE_RH_ALM_FULL_4 0x00000000
76	#define PCH_GBE_RH_ALM_FULL_8 0x00001000
77	#define PCH_GBE_RH_ALM_FULL_16 0x00002000
78	#define PCH_GBE_RH_ALM_FULL_32 0x00003000
79	#define PCH_GBE_RH_RD_TRG_4 0x00000000
80	#define PCH_GBE_RH_RD_TRG_8 0x00000200
81	#define PCH_GBE_RH_RD_TRG_16 0x00000400
82	#define PCH_GBE_RH_RD_TRG_32 0x00000600
83	#define PCH_GBE_RH_RD_TRG_64 0x00000800
84	#define PCH_GBE_RH_RD_TRG_128 0x00000a00
85	#define PCH_GBE_RH_RD_TRG_256 0x00000c00
86	#define PCH_GBE_RH_RD_TRG_512 0x00000e00
87
88	/* TX Mode */
89	#define PCH_GBE_TM_NO_RTRY 0x80000000
90	#define PCH_GBE_TM_LONG_PKT 0x40000000
91	#define PCH_GBE_TM_ST_AND_FD 0x20000000
92	#define PCH_GBE_TM_SHORT_PKT 0x10000000
93	#define PCH_GBE_TM_LTCOL_RETX 0x08000000
94	#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
95	#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
96	#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
97	#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000
98	#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
99	#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
100	#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
101	#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
102	#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
103	#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
104	#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
105	#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
106	#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
107	#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
108	#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
109	#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
110
111	/* MAC Address Mask */
112	#define PCH_GBE_BUSY 0x80000000
113
114	/* MIIM */
115	#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
116	#define PCH_GBE_MIIM_OPER_READ 0x00000000
117	#define PCH_GBE_MIIM_OPER_READY 0x04000000
118	#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
119	#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
120
121	/* RGMII Control */
122	#define PCH_GBE_CRS_SEL 0x00000010
123	#define PCH_GBE_RGMII_RATE_125M 0x00000000
124	#define PCH_GBE_RGMII_RATE_25M 0x00000008
125	#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c
126	#define PCH_GBE_RGMII_MODE_GMII 0x00000000
127	#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
128	#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
129	#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
130
131	/* DMA Control */
132	#define PCH_GBE_RX_DMA_EN 0x00000002
133	#define PCH_GBE_TX_DMA_EN 0x00000001
134
135	/* Receive Descriptor bit definitions */
136	#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
137	#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
138	#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
139	#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0
140	#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
141	#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
142	#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
143	#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
144	#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
145	#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
146	#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
147	#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
148	#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
149	#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
150	#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
151	#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
152	#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
153	#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
154	#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
155	#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
156	#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
157	#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
158
159	/* Transmit Descriptor bit definitions */
160	#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
161	#define PCH_GBE_TXD_CTRL_ITAG 0x0004
162	#define PCH_GBE_TXD_CTRL_ICRC 0x0002
163	#define PCH_GBE_TXD_CTRL_APAD 0x0001
164	#define PCH_GBE_TXD_WORDS_SHIFT 2
165	#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
166	#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
167	#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
168	#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
169	#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
170	#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
171	#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
172	#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
173	#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
174	#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
175
176	/**
177	* struct pch_gbe_rx_desc - Receive Descriptor
178	* @buffer_addr: RX Frame Buffer Address
179	* @tcp_ip_status: TCP/IP Accelerator Status
180	* @rx_words_eob: RX word count and Byte position
181	* @gbec_status: GMAC Status
182	* @dma_status: DMA Status
183	* @reserved1: Reserved
184	* @reserved2: Reserved
185	*/
186	struct pch_gbe_rx_desc {
187	u32 buffer_addr;
188	u32 tcp_ip_status;
189	u16 rx_words_eob;
190	u16 gbec_status;
191	u8 dma_status;
192	u8 reserved1;
193	u16 reserved2;
194	};
195
196	/**
197	* struct pch_gbe_tx_desc - Transmit Descriptor
198	* @buffer_addr: TX Frame Buffer Address
199	* @length: Data buffer length
200	* @reserved1: Reserved
201	* @tx_words_eob: TX word count and Byte position
202	* @tx_frame_ctrl: TX Frame Control
203	* @dma_status: DMA Status
204	* @reserved2: Reserved
205	* @gbec_status: GMAC Status
206	*/
207	struct pch_gbe_tx_desc {
208	u32 buffer_addr;
209	u16 length;
210	u16 reserved1;
211	u16 tx_words_eob;
212	u16 tx_frame_ctrl;
213	u8 dma_status;
214	u8 reserved2;
215	u16 gbec_status;
216	};
217
218	/**
219	* pch_gbe_regs_mac_adr - structure holding values of mac address registers
220	*
221	* @high Denotes the 1st to 4th byte from the initial of MAC address
222	* @low Denotes the 5th to 6th byte from the initial of MAC address
223	*/
224	struct pch_gbe_regs_mac_adr {
225	u32 high;
226	u32 low;
227	};
228
229	/**
230	* pch_gbe_regs - structure holding values of MAC registers
231	*/
232	struct pch_gbe_regs {
233	u32 int_st;
234	u32 int_en;
235	u32 mode;
236	u32 reset;
237	u32 tcpip_acc;
238	u32 ex_list;
239	u32 int_st_hold;
240	u32 phy_int_ctrl;
241	u32 mac_rx_en;
242	u32 rx_fctrl;
243	u32 pause_req;
244	u32 rx_mode;
245	u32 tx_mode;
246	u32 rx_fifo_st;
247	u32 tx_fifo_st;
248	u32 tx_fid;
249	u32 tx_result;
250	u32 pause_pkt1;
251	u32 pause_pkt2;
252	u32 pause_pkt3;
253	u32 pause_pkt4;
254	u32 pause_pkt5;
255	u32 reserve[2];
256	struct pch_gbe_regs_mac_adr mac_adr[16];
257	u32 addr_mask;
258	u32 miim;
259	u32 mac_addr_load;
260	u32 rgmii_st;
261	u32 rgmii_ctrl;
262	u32 reserve3[3];
263	u32 dma_ctrl;
264	u32 reserve4[3];
265	u32 rx_dsc_base;
266	u32 rx_dsc_size;
267	u32 rx_dsc_hw_p;
268	u32 rx_dsc_hw_p_hld;
269	u32 rx_dsc_sw_p;
270	u32 reserve5[3];
271	u32 tx_dsc_base;
272	u32 tx_dsc_size;
273	u32 tx_dsc_hw_p;
274	u32 tx_dsc_hw_p_hld;
275	u32 tx_dsc_sw_p;
276	u32 reserve6[3];
277	u32 rx_dma_st;
278	u32 tx_dma_st;
279	u32 reserve7[2];
280	u32 wol_st;
281	u32 wol_ctrl;
282	u32 wol_addr_mask;
283	};
284
285	struct pch_gbe_priv {
286	struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
287	struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
288	char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
8ee443b8 BM	289	struct phy_device *phydev;
	290	struct mii_dev *bus;
	291	struct pch_gbe_regs *mac_regs;
c52ac3f9	292	struct udevice *dev;
8ee443b8 BM	293	int rx_idx;
	294	int tx_idx;
	295	};
	296
	297	#endif /* _PCH_GBE_H_ */