[J-u-boot.git] / include / configs / hcu5.h

/*
 * (C) Copyright 2007 Netstal Maschinen AG
 * Niklaus Giger ([email protected])
 *
 * (C) Copyright 2006-2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2006
 * Jacqueline Pira-Ferriol, AMCC/IBM, [email protected]
 * Alain Saurel,            AMCC/IBM, [email protected]
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_HCU5		1		/* Board is HCU5	*/
#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
#define CONFIG_440		1		/* ... PPC440 family	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#define CFG_BOOT_BASE_ADDR	0xfff00000
#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CFG_FLASH_BASE		0xfff80000	/* start of FLASH	*/
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000

/* Don't change either of these */
#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/

#define CFG_USB2D0_BASE		0xe0000100
#define CFG_USB_DEVICE		0xe0000000
#define CFG_USB_HOST		0xe0000400

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer
 *----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/

#define CFG_INIT_RAM_END	(4 << 10)
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
#define CONFIG_BAUDRATE		9600
#undef CONFIG_SERIAL_MULTI            /* needed to be able to define
	CONFIG_SERIAL_SOFTWARE_FIFO, but
	CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
/* Size (bytes) of interrupt driven serial port buffer.
 * Set to 0 to use polling instead of interrupts.
 * Setting to 0 will also disable RTS/CTS handshaking.
 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/

#undef	CFG_ENV_IS_IN_NVRAM
#undef  CFG_ENV_IS_IN_FLASH
#define	CFG_ENV_IS_IN_EEPROM
#undef  CFG_ENV_IS_NOWHERE

#ifdef  CFG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM and bootstrap configuration */
#define PROM_SIZE 	2048
#define CFG_BOOSTRAP_OPTION_OFFSET	 512
#define CFG_ENV_OFFSET	 (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
#define CFG_ENV_SIZE	(PROM_SIZE-CFG_ENV_OFFSET)
#endif

#ifdef CFG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM        (128)		/* 128 MB or 256 MB  		*/
#define CFG_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
#undef  CONFIG_DDR_DATA_EYE			/* Do not use DDR2 optimization	*/
#define CONFIG_DDR_ECC		1		/* enable ECC			*/

/*-----------------------------------------------------------------------
 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
 * the second internal I2C controller of the PPC440EPx
 *----------------------------------------------------------------------*/
#define CFG_SPD_BUS_NUM		1

#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

/* This is the 7bit address of the device, not including P. */
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1

/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#undef CFG_I2C_MULTI_EEPROMS


#define CONFIG_PREBOOT	"echo;"						\
	"echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
	"echo"

#undef	CONFIG_BOOTARGS

/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME		hcu5
#define CONFIG_IPADDR		172.25.1.42
#define CONFIG_ETHADDR      	00:60:13:00:00:00   /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP		172.25.1.3

#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"loadaddr=0x01000000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" 	\
		"bootm\0"						\
		"bootfile=hcu5/uImage\0" 				\
		"rootpath=/home/hcu/eldk/ppc_4xxFP\0"		 	\
		"load=tftp 100000 hcu5/u-boot.bin\0"		 	\
	"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;"	\
		"cp.b 100000 FFFa0000 60000\0"			        \
	"upd=run load;run update\0"					\
	"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" 			\
	"setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " 	 	\
		" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
	"bootvx ${loadaddr}\0" \
	""
#define CONFIG_BOOTCOMMAND	"run vx"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_M88E1111_PHY	1
#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */

#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NET_MULTI	1
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY1_ADDR	1

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_USB

#define CONFIG_SUPPORT_VFAT

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CFG_FLASH		CFG_FLASH_BASE
#define CFG_CS_1		0xC8000000 /* CAN */
#define CFG_CS_2		0xCC000000 /* CPLD and IMC-Bus Standard */
#define CFG_CPLD		CFG_CS_2
#define CFG_CS_3		0xCD000000 /* CPLD and IMC-Bus Fast  */

/*-----------------------------------------------------------------------
 * FLASH organization
 * Memory Bank 0 (BOOT-FLASH) initialization
 */
#define CFG_BOOTFLASH_CS		0	/* Boot Flash chip connected to CSx	*/
#define CFG_EBC_PB0AP		0x02005400
#define CFG_EBC_PB0CR		0xFFF18000 /* (CFG_FLASH | 0xda000)  */
#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/


#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* Memory Bank 1 CAN-Chips initialization						*/
#define CFG_EBC_PB1AP		0x02054500
#define CFG_EBC_PB1CR		0xC8018000

/* Memory Bank 2 CPLD/IMC-Bus standard initialization						*/
#define CFG_EBC_PB2AP		0x01840300
#define CFG_EBC_PB2CR		0xCC0BA000

/* Memory Bank 3 IMC-Bus fast mode initialization						*/
#define CFG_EBC_PB3AP		0x01800300
#define CFG_EBC_PB3CR		0xCE0BA000

/* Memory Bank 4 (not used) initialization						*/
#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR

/* Memory Bank 5 (not used) initialization						*/
#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR

#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
#define HCU_HW_VERSION_REGISTER   ( CFG_CPLD + 0x1400000 )

/*-----------------------------------------------------------------------
 * Cache Configuration
 *----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	      /* ...			            */
#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CFG_HUSH_PARSER                 /* use "hush" command parser    */
#ifdef  CFG_HUSH_PARSER
	#define CFG_PROMPT_HUSH_PS2     "> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
137fdd9f NG	1	/*
	2	* (C) Copyright 2007 Netstal Maschinen AG
	3	* Niklaus Giger ([email protected])
	4	*
	5	* (C) Copyright 2006-2007
	6	* Stefan Roese, DENX Software Engineering, [email protected].
	7	*
	8	* (C) Copyright 2006
	9	* Jacqueline Pira-Ferriol, AMCC/IBM, [email protected]
	10	* Alain Saurel, AMCC/IBM, [email protected]
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	/************************************************************************
	29	* hcu5.h - configuration for HCU5 board (derived from sequoia.h)
	30	***********************************************************************/
	31
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/*-----------------------------------------------------------------------
	36	* High Level Configuration Options
	37	----------------------------------------------------------------------/
	38	#define CONFIG_HCU5 1 /* Board is HCU5 */
	39	#define CONFIG_440EPX 1 /* Specific PPC440EPx */
	40	#define CONFIG_440 1 /* ... PPC440 family */
	41	#define CONFIG_4xx 1 /* ... PPC4xx family */
	42	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	43
	44	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	45	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
137fdd9f NG	46
	47	/*-----------------------------------------------------------------------
	48	* Base addresses -- Note these are effective addresses where the
	49	* actual resources get mapped (not physical addresses)
	50	----------------------------------------------------------------------/
	51	#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
	52	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	53
	54	#define CFG_BOOT_BASE_ADDR 0xfff00000
	55	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	56	#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
	57	#define CFG_MONITOR_BASE TEXT_BASE
	58	#define CFG_OCM_BASE 0xe0010000 /* ocm */
	59	#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
	60	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	61	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	62	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	63	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
	64
	65	/* Don't change either of these */
	66	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
	67
	68	#define CFG_USB2D0_BASE 0xe0000100
	69	#define CFG_USB_DEVICE 0xe0000000
	70	#define CFG_USB_HOST 0xe0000400
	71
	72	/*-----------------------------------------------------------------------
	73	* Initial RAM & stack pointer
	74	----------------------------------------------------------------------/
	75	/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
	76	#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
	77	#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
	78
	79	#define CFG_INIT_RAM_END (4 << 10)
	80	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
	81	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	82	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	83
	84	/*-----------------------------------------------------------------------
	85	* Serial Port
	86	----------------------------------------------------------------------/
	87	#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
	88	#define CONFIG_BAUDRATE 9600
	89	#undef CONFIG_SERIAL_MULTI /* needed to be able to define
	90	CONFIG_SERIAL_SOFTWARE_FIFO, but
	91	CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
	92	/* Size (bytes) of interrupt driven serial port buffer.
	93	* Set to 0 to use polling instead of interrupts.
	94	* Setting to 0 will also disable RTS/CTS handshaking.
	95	*/
	96	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	97	#undef CONFIG_UART1_CONSOLE
	98
	99	#define CFG_BAUDRATE_TABLE \
	100	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	101
	102	/*-----------------------------------------------------------------------
	103	* Environment
	104	----------------------------------------------------------------------/
	105
	106	#undef CFG_ENV_IS_IN_NVRAM
	107	#undef CFG_ENV_IS_IN_FLASH
	108	#define CFG_ENV_IS_IN_EEPROM
	109	#undef CFG_ENV_IS_NOWHERE
110
111	#ifdef CFG_ENV_IS_IN_EEPROM
112	/* Put the environment after the SDRAM and bootstrap configuration */
113	#define PROM_SIZE 2048
114	#define CFG_BOOSTRAP_OPTION_OFFSET 512
115	#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
116	#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
117	#endif
118
119	#ifdef CFG_ENV_IS_IN_FLASH
120	/* Put the environment in Flash */
121	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
122	#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
123	#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
124
125	/* Address and size of Redundant Environment Sector */
126	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
127	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
128	#endif
129
130	/*-----------------------------------------------------------------------
131	* DDR SDRAM
132	----------------------------------------------------------------------/
133	#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
134	#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
135	#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
136	#define CONFIG_DDR_ECC 1 /* enable ECC */
137
138	/*-----------------------------------------------------------------------
139	* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
140	* the second internal I2C controller of the PPC440EPx
141	----------------------------------------------------------------------/
142	#define CFG_SPD_BUS_NUM 1
143
144	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
145	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
146	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
147	#define CFG_I2C_SLAVE 0x7F
148
149	/* This is the 7bit address of the device, not including P. */
150	#define CFG_I2C_EEPROM_ADDR 0x50
151	#define CFG_I2C_EEPROM_ADDR_LEN 1
152
153	/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
154	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
155	#define CFG_EEPROM_PAGE_WRITE_BITS 4
156	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
157	#define CFG_EEPROM_PAGE_WRITE_ENABLE
158	#undef CFG_I2C_MULTI_EEPROMS
159
160
161	#define CONFIG_PREBOOT "echo;" \
162	"echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
163	"echo"
164
165	#undef CONFIG_BOOTARGS
166
167	/* Setup some board specific values for the default environment variables */
168	#define CONFIG_HOSTNAME hcu5
169	#define CONFIG_IPADDR 172.25.1.42
170	#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
171	#define CONFIG_OVERWRITE_ETHADDR_ONCE
172	#define CONFIG_SERVERIP 172.25.1.3
173
174	#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
175
176	#define CONFIG_EXTRA_ENV_SETTINGS \
177	"netdev=eth0\0" \
178	"loadaddr=0x01000000\0" \
179	"nfsargs=setenv bootargs root=/dev/nfs rw " \
180	"nfsroot=${serverip}:${rootpath}\0" \
181	"ramargs=setenv bootargs root=/dev/ram rw\0" \
182	"addip=setenv bootargs ${bootargs} " \
183	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
184	":${hostname}:${netdev}:off panic=1\0" \
185	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
186	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
187	"bootm\0" \
188	"bootfile=hcu5/uImage\0" \
189	"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
190	"load=tftp 100000 hcu5/u-boot.bin\0" \
191	"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
192	"cp.b 100000 FFFa0000 60000\0" \
193	"upd=run load;run update\0" \
194	"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
195	"setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
196	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
197	"bootvx ${loadaddr}\0" \
198	""
199	#define CONFIG_BOOTCOMMAND "run vx"
200
201	#if 0
202	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
203	#else
204	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
205	#endif
206
207	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
208	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
209
210	#define CONFIG_M88E1111_PHY 1
211	#define CONFIG_IBM_EMAC4_V4 1
212	#define CONFIG_MII 1 /* MII PHY management */
213	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
214
215	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
216
217	#define CONFIG_HAS_ETH0
218	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
219
220	#define CONFIG_NET_MULTI 1
221	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
222	#define CONFIG_PHY1_ADDR 1
223
224	/* USB */
225	#define CONFIG_USB_OHCI
226	#define CONFIG_USB_STORAGE
227
228	/* Comment this out to enable USB 1.1 device */
229	#define USB_2_0_DEVICE
230
137fdd9f NG	231	/* Partitions */
	232	#define CONFIG_MAC_PARTITION
	233	#define CONFIG_DOS_PARTITION
	234	#define CONFIG_ISO_PARTITION
	235
3b3bff4c SR	236	/*
	237	* BOOTP options
	238	*/
	239	#define CONFIG_BOOTP_BOOTFILESIZE
	240	#define CONFIG_BOOTP_BOOTPATH
	241	#define CONFIG_BOOTP_GATEWAY
	242	#define CONFIG_BOOTP_HOSTNAME
137fdd9f	243
3b3bff4c SR	244	/*
	245	* Command line configuration.
	246	*/
	247	#include <config_cmd_default.h>
	248
	249	#define CONFIG_CMD_ASKENV
	250	#define CONFIG_CMD_BSP
	251	#define CONFIG_CMD_DHCP
	252	#define CONFIG_CMD_DIAG
	253	#define CONFIG_CMD_EEPROM
	254	#define CONFIG_CMD_ELF
	255	#define CONFIG_CMD_FLASH
	256	#define CONFIG_CMD_FAT
	257	#define CONFIG_CMD_I2C
	258	#define CONFIG_CMD_IMMAP
	259	#define CONFIG_CMD_IRQ
	260	#define CONFIG_CMD_MII
	261	#define CONFIG_CMD_NET
	262	#define CONFIG_CMD_NFS
	263	#define CONFIG_CMD_PING
	264	#define CONFIG_CMD_REGINFO
	265	#define CONFIG_CMD_SDRAM
	266	#define CONFIG_CMD_USB
137fdd9f	267
3b3bff4c	268	#define CONFIG_SUPPORT_VFAT
137fdd9f NG	269
	270	/*-----------------------------------------------------------------------
	271	* Miscellaneous configurable options
	272	----------------------------------------------------------------------/
	273	#define CFG_LONGHELP /* undef to save memory */
	274	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
3b3bff4c	275	#if defined(CONFIG_CMD_KGDB)
137fdd9f NG	276	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	277	#else
	278	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	279	#endif
	280	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	281	#define CFG_MAXARGS 16 /* max number of command args */
	282	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	283
	284	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	285	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	286
	287	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	288	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	289
	290	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	291
	292	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	293	#define CONFIG_LOOPW 1 /* enable loopw command */
	294	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	295	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	296	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	297
	298	/*-----------------------------------------------------------------------
	299	* PCI stuff
	300	----------------------------------------------------------------------/
	301	/* General PCI */
	302	#define CONFIG_PCI /* include pci support */
	303	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
	304	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	305	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
	306
	307	/* Board-specific PCI */
137fdd9f NG	308	#define CFG_PCI_TARGET_INIT
	309	#define CFG_PCI_MASTER_INIT
	310
	311	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
	312	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
	313
	314	/*
	315	* For booting Linux, the board info and command line data
	316	* have to be in the first 8 MB of memory, since this is
	317	* the maximum mapped by the Linux kernel during initialization.
	318	*/
	319	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	320
	321	/*-----------------------------------------------------------------------
	322	* External Bus Controller (EBC) Setup
	323	----------------------------------------------------------------------/
	324	#define CFG_FLASH CFG_FLASH_BASE
	325	#define CFG_CS_1 0xC8000000 /* CAN */
	326	#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
	327	#define CFG_CPLD CFG_CS_2
	328	#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
	329
	330	/*-----------------------------------------------------------------------
	331	* FLASH organization
	332	* Memory Bank 0 (BOOT-FLASH) initialization
	333	*/
	334	#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
	335	#define CFG_EBC_PB0AP 0x02005400
	336	#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH \| 0xda000) */
	337	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	338	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	339	#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
	340
	341
	342	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	343	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	344
	345	/* Memory Bank 1 CAN-Chips initialization */
	346	#define CFG_EBC_PB1AP 0x02054500
	347	#define CFG_EBC_PB1CR 0xC8018000
	348
	349	/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
	350	#define CFG_EBC_PB2AP 0x01840300
	351	#define CFG_EBC_PB2CR 0xCC0BA000
	352
	353	/* Memory Bank 3 IMC-Bus fast mode initialization */
	354	#define CFG_EBC_PB3AP 0x01800300
	355	#define CFG_EBC_PB3CR 0xCE0BA000
	356
	357	/* Memory Bank 4 (not used) initialization */
	358	#undef CFG_EBC_PB4AP
	359	#undef CFG_EBC_PB4CR
	360
	361	/* Memory Bank 5 (not used) initialization */
	362	#undef CFG_EBC_PB5AP
	363	#undef CFG_EBC_PB5CR
	364
	365	#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
	366	#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
	367
	368	/*-----------------------------------------------------------------------
	369	* Cache Configuration
	370	----------------------------------------------------------------------/
	371	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
372	#define CFG_CACHELINE_SIZE 32 /* ... */
137fdd9f	373	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
137fdd9f NG	374
	375	/*
	376	* Internal Definitions
	377	*
	378	* Boot Flags
	379	*/
	380	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	381	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	382
	383	#define CFG_HUSH_PARSER /* use "hush" command parser */
	384	#ifdef CFG_HUSH_PARSER
	385	#define CFG_PROMPT_HUSH_PS2 "> "
	386	#endif
	387
3b3bff4c	388	#if defined(CONFIG_CMD_KGDB)
137fdd9f NG	389	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	390	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	391	#endif
	392	#endif /* __CONFIG_H */