projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| dc17fb6d WD |
1 | /* |
| 2 | * (C) Copyright 2004 | |
| 3 | * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __CONFIG_H | |
| 25 | #define __CONFIG_H | |
| 26 | ||
| 27 | /* | |
| 28 | * High Level Configuration Options | |
| 29 | * (easy to change) | |
| 30 | */ | |
| 31 | #define CONFIG_MPC8220 1 | |
| 32 | #define CONFIG_YUKON8220 1 /* ... on Yukon board */ | |
| 33 | ||
| 34 | /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to | |
| 35 | determine the CPU speed. */ | |
| 36 | #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ | |
| 37 | #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ | |
| 38 | ||
| 39 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 40 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 41 | ||
| dc17fb6d WD |
42 | /* |
| 43 | * Serial console configuration | |
| 44 | */ | |
| 45 | ||
| 46 | /* Define this for PSC console | |
| 47 | #define CONFIG_PSC_CONSOLE 1 | |
| 48 | */ | |
| 49 | ||
| 50 | #define CONFIG_EXTUART_CONSOLE 1 | |
| 51 | ||
| 52 | #ifdef CONFIG_EXTUART_CONSOLE | |
| 53 | # define CONFIG_CONS_INDEX 1 | |
| 54 | # define CFG_NS16550_SERIAL | |
| 55 | # define CFG_NS16550 | |
| 56 | # define CFG_NS16550_REG_SIZE 1 | |
| 57 | # define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) | |
| 58 | # define CFG_NS16550_CLK 18432000 | |
| 59 | #endif | |
| 60 | ||
| 61 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
| 62 | ||
| 63 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
| 64 | ||
| 65 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
| 66 | ||
| a5562901 | 67 | |
| a1aa0bb5 JL |
68 | /* |
| 69 | * BOOTP options | |
| 70 | */ | |
| 71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 72 | #define CONFIG_BOOTP_BOOTPATH | |
| 73 | #define CONFIG_BOOTP_GATEWAY | |
| 74 | #define CONFIG_BOOTP_HOSTNAME | |
| 75 | ||
| 76 | ||
| dc17fb6d | 77 | /* |
| a5562901 | 78 | * Command line configuration. |
| dc17fb6d | 79 | */ |
| a5562901 JL |
80 | #include <config_cmd_default.h> |
| 81 | ||
| 82 | #define CONFIG_CMD_BOOTD | |
| 83 | #define CONFIG_CMD_CACHE | |
| 84 | #define CONFIG_CMD_DHCP | |
| 85 | #define CONFIG_CMD_DIAG | |
| 86 | #define CONFIG_CMD_EEPROM | |
| 87 | #define CONFIG_CMD_ELF | |
| 88 | #define CONFIG_CMD_I2C | |
| 89 | #define CONFIG_CMD_NET | |
| 90 | #define CONFIG_CMD_NFS | |
| 91 | #define CONFIG_CMD_PCI | |
| 92 | #define CONFIG_CMD_PING | |
| 93 | #define CONFIG_CMD_REGINFO | |
| 94 | #define CONFIG_CMD_SDRAM | |
| 95 | #define CONFIG_CMD_SNTP | |
| 96 | ||
| dc17fb6d WD |
97 | |
| 98 | #define CONFIG_NET_MULTI | |
| 63ff004c | 99 | #define CONFIG_MII |
| dc17fb6d | 100 | |
| dc17fb6d WD |
101 | /* |
| 102 | * Autobooting | |
| 103 | */ | |
| 104 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 105 | #define CONFIG_BOOTARGS "root=/dev/ram rw" | |
| 106 | #define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 | |
| 107 | #define CONFIG_HAS_ETH1 | |
| 108 | #define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 | |
| 109 | #define CONFIG_IPADDR 192.162.1.2 | |
| 110 | #define CONFIG_NETMASK 255.255.255.0 | |
| 111 | #define CONFIG_SERVERIP 192.162.1.1 | |
| 112 | #define CONFIG_GATEWAYIP 192.162.1.1 | |
| 113 | #define CONFIG_HOSTNAME yukon | |
| 114 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
| 115 | ||
| 116 | ||
| 117 | /* | |
| 118 | * I2C configuration | |
| 119 | */ | |
| 120 | #define CONFIG_HARD_I2C 1 | |
| 121 | #define CFG_I2C_MODULE 1 | |
| 122 | ||
| 123 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
| 124 | #define CFG_I2C_SLAVE 0x7F | |
| 125 | ||
| 126 | /* | |
| 127 | * EEPROM configuration | |
| 128 | */ | |
| 129 | #define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ | |
| 130 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
| 131 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
| 132 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
| 133 | /* | |
| 134 | #define CFG_ENV_IS_IN_EEPROM 1 | |
| 135 | #define CFG_ENV_OFFSET 0 | |
| 136 | #define CFG_ENV_SIZE 256 | |
| 137 | */ | |
| 138 | ||
| 139 | /* If CFG_AMD_BOOT is defined, the the system will boot from AMD. | |
| 140 | else undefined it will boot from Intel Strata flash */ | |
| 141 | #define CFG_AMD_BOOT 1 | |
| 142 | ||
| 143 | /* | |
| 144 | * Flexbus Chipselect configuration | |
| 145 | */ | |
| 146 | #if defined (CFG_AMD_BOOT) | |
| 147 | #define CFG_CS0_BASE 0xfff0 | |
| 148 | #define CFG_CS0_MASK 0x00080000 /* 512 KB */ | |
| 149 | #define CFG_CS0_CTRL 0x003f0d40 | |
| 150 | ||
| 151 | #define CFG_CS1_BASE 0xfe00 | |
| 152 | #define CFG_CS1_MASK 0x01000000 /* 16 MB */ | |
| 153 | #define CFG_CS1_CTRL 0x003f1540 | |
| 154 | #else | |
| 155 | #define CFG_CS0_BASE 0xff00 | |
| 156 | #define CFG_CS0_MASK 0x01000000 /* 16 MB */ | |
| 157 | #define CFG_CS0_CTRL 0x003f1540 | |
| 158 | ||
| 159 | #define CFG_CS1_BASE 0xfe08 | |
| 160 | #define CFG_CS1_MASK 0x00080000 /* 512 KB */ | |
| 161 | #define CFG_CS1_CTRL 0x003f0d40 | |
| 162 | #endif | |
| 163 | ||
| 164 | #define CFG_CS2_BASE 0xf100 | |
| 165 | #define CFG_CS2_MASK 0x00040000 | |
| 166 | #define CFG_CS2_CTRL 0x003f1140 | |
| 167 | ||
| 168 | #define CFG_CS3_BASE 0xf200 | |
| 169 | #define CFG_CS3_MASK 0x00040000 | |
| 170 | #define CFG_CS3_CTRL 0x003f1100 | |
| 171 | ||
| 172 | ||
| 173 | #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) | |
| 174 | #define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) | |
| 175 | ||
| 176 | #if defined (CFG_AMD_BOOT) | |
| 177 | #define CFG_AMD_BASE CFG_FLASH0_BASE | |
| 178 | #define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 | |
| 179 | #define CFG_FLASH_BASE CFG_AMD_BASE | |
| 180 | #else | |
| 181 | #define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 | |
| 182 | #define CFG_AMD_BASE CFG_FLASH1_BASE | |
| 183 | #define CFG_FLASH_BASE CFG_INTEL_BASE | |
| 184 | #endif | |
| 185 | ||
| 186 | #define CFG_CPLD_BASE (CFG_CS2_BASE << 16) | |
| 187 | #define CFG_FPGA_BASE (CFG_CS3_BASE << 16) | |
| 188 | ||
| 189 | ||
| 190 | #define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ | |
| 191 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| 192 | ||
| 193 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
| 194 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 195 | #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ | |
| 196 | #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ | |
| 197 | #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
| 198 | ||
| 199 | #define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ | |
| 200 | #define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ | |
| 201 | ||
| 202 | #define CFG_FLASH_CHECKSUM | |
| 203 | /* | |
| 204 | * Environment settings | |
| 205 | */ | |
| 206 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 207 | #if defined (CFG_AMD_BOOT) | |
| 208 | #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) | |
| 209 | #define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE | |
| 210 | #define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE | |
| 211 | #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) | |
| 212 | #define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE | |
| 213 | #define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE | |
| 214 | #else | |
| 215 | #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) | |
| 216 | #define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE | |
| 217 | #define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE | |
| 218 | #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) | |
| 219 | #define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE | |
| 220 | #define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE | |
| 221 | #endif | |
| 222 | ||
| 223 | #define CONFIG_ENV_OVERWRITE 1 | |
| 224 | ||
| 225 | #if defined CFG_ENV_IS_IN_FLASH | |
| 226 | #undef CFG_ENV_IS_IN_NVRAM | |
| 227 | #undef CFG_ENV_IS_IN_EEPROM | |
| 228 | #elif defined CFG_ENV_IS_IN_NVRAM | |
| 229 | #undef CFG_ENV_IS_IN_FLASH | |
| 230 | #undef CFG_ENV_IS_IN_EEPROM | |
| 231 | #elif defined CFG_ENV_IS_IN_EEPROM | |
| 232 | #undef CFG_ENV_IS_IN_NVRAM | |
| 233 | #undef CFG_ENV_IS_IN_FLASH | |
| 234 | #endif | |
| 235 | ||
| 236 | #ifndef CFG_JFFS2_FIRST_SECTOR | |
| 237 | #define CFG_JFFS2_FIRST_SECTOR 0 | |
| 238 | #endif | |
| 239 | #ifndef CFG_JFFS2_FIRST_BANK | |
| 240 | #define CFG_JFFS2_FIRST_BANK 0 | |
| 241 | #endif | |
| 242 | #ifndef CFG_JFFS2_NUM_BANKS | |
| 243 | #define CFG_JFFS2_NUM_BANKS 1 | |
| 244 | #endif | |
| 245 | #define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) | |
| 246 | ||
| 247 | /* | |
| 248 | * Memory map | |
| 249 | */ | |
| 250 | #define CFG_MBAR 0xF0000000 | |
| 251 | #define CFG_SDRAM_BASE 0x00000000 | |
| 252 | #define CFG_DEFAULT_MBAR 0x80000000 | |
| 253 | #define CFG_SRAM_BASE (CFG_MBAR + 0x20000) | |
| 254 | #define CFG_SRAM_SIZE 0x8000 | |
| 255 | ||
| 256 | /* Use SRAM until RAM will be available */ | |
| 257 | #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) | |
| 258 | #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ | |
| 259 | ||
| 260 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
| 261 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 262 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 263 | ||
| 264 | #define CFG_MONITOR_BASE TEXT_BASE | |
| 265 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 266 | # define CFG_RAMBOOT 1 | |
| 267 | #endif | |
| 268 | ||
| 269 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 270 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 271 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 272 | ||
| 273 | /* SDRAM configuration */ | |
| 274 | #define CFG_SDRAM_TOTAL_BANKS 2 | |
| 275 | #define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ | |
| 276 | #define CFG_SDRAM_SPD_SIZE 0x40 | |
| 277 | #define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ | |
| 278 | ||
| 279 | /* SDRAM drive strength register */ | |
| 280 | #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ | |
| 281 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ | |
| 282 | (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ | |
| 283 | (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ | |
| 284 | (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) | |
| 285 | ||
| 286 | /* | |
| 287 | * Ethernet configuration | |
| 288 | */ | |
| 289 | #define CONFIG_MPC8220_FEC 1 | |
| 290 | #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ | |
| 291 | #define CONFIG_PHY_ADDR 0x18 | |
| 292 | ||
| 293 | ||
| 294 | /* | |
| 295 | * Miscellaneous configurable options | |
| 296 | */ | |
| 297 | #define CFG_LONGHELP /* undef to save memory */ | |
| 298 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| a5562901 | 299 | #if defined(CONFIG_CMD_KGDB) |
| dc17fb6d WD |
300 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 301 | #else | |
| 302 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 303 | #endif | |
| 304 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 305 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 306 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 307 | ||
| 308 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
| 309 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
| 310 | ||
| 311 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 312 | ||
| 313 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 314 | ||
| a5562901 JL |
315 | #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ |
| 316 | #if defined(CONFIG_CMD_KGDB) | |
| 317 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 318 | #endif | |
| 319 | ||
| dc17fb6d WD |
320 | /* |
| 321 | * Various low-level settings | |
| 322 | */ | |
| 323 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
| 324 | #define CFG_HID0_FINAL HID0_ICE | |
| 325 | ||
| 326 | #endif /* __CONFIG_H */ |