[J-u-boot.git] / include / configs / MUSENKI.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the MUSENKI board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_MUSENKI		1


#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_BOOTDELAY	5


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * Miscellaneous configurable options
 */
#undef CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

/* Print Buffer Size
 */
#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS	8		/* Max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI      		/* include pci support          */
#undef CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

#define CONFIG_TULIP

#define PCI_ENET0_IOADDR		0x80000000
#define PCI_ENET0_MEMADDR		0x80000000
#define PCI_ENET1_IOADDR		0x81000000
#define PCI_ENET1_MEMADDR		0x81000000


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE	    0x00000000

#define CFG_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
#define CFG_FLASH_BASE  CFG_FLASH_BASE0_PRELIM

/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
 * reset vector is actually located at FFB00100, but the 8245
 * takes care of us.
 */
#define CFG_RESET_ADDRESS   0xFFF00100

#define CFG_EUMB_ADDR	    0xFC000000

#define CFG_MONITOR_BASE    TEXT_BASE
#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CFG_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */


#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

/* #define CFG_MONITOR_BASE        TEXT_BASE */
/*#define CFG_GBL_DATA_SIZE    256*/
#define CFG_GBL_DATA_SIZE      128
#define CFG_INIT_RAM_ADDR     0x40000000
#define CFG_INIT_RAM_END      0x1000
#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)


/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
#define CFG_HZ		     1000

	/* Bit-field values for MCCR1.
	 */
#define CFG_ROMNAL	    7
#define CFG_ROMFAL	    11
#define CFG_DBUS_SIZE       0x3

	/* Bit-field values for MCCR2.
	 */
#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CFG_BSTOPRE	    121

	/* Bit-field values for MCCR3.
	 */
#define CFG_REFREC	    8	    /* Refresh to activate interval */

	/* Bit-field values for MCCR4.
	 */
#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
#define CFG_ACTORW	    3		/* FIXME was 2 */
#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM	    1
#define CFG_REGDIMM	    0

#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/

#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START	    0x00000000
#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE    1
#define CFG_BANK1_START	    0x3ff00000
#define CFG_BANK1_END	    0x3fffffff
#define CFG_BANK1_ENABLE    0
#define CFG_BANK2_START	    0x3ff00000
#define CFG_BANK2_END	    0x3fffffff
#define CFG_BANK2_ENABLE    0
#define CFG_BANK3_START	    0x3ff00000
#define CFG_BANK3_END	    0x3fffffff
#define CFG_BANK3_ENABLE    0
#define CFG_BANK4_START	    0x3ff00000
#define CFG_BANK4_END	    0x3fffffff
#define CFG_BANK4_ENABLE    0
#define CFG_BANK5_START	    0x3ff00000
#define CFG_BANK5_END	    0x3fffffff
#define CFG_BANK5_ENABLE    0
#define CFG_BANK6_START	    0x3ff00000
#define CFG_BANK6_END	    0x3fffffff
#define CFG_BANK6_ENABLE    0
#define CFG_BANK7_START	    0x3ff00000
#define CFG_BANK7_END	    0x3fffffff
#define CFG_BANK7_ENABLE    0

#define CFG_ODCR	    0xff

#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT0L  CFG_IBAT0L
#define CFG_DBAT0U  CFG_IBAT0U
#define CFG_DBAT1L  CFG_IBAT1L
#define CFG_DBAT1U  CFG_IBAT1U
#define CFG_DBAT2L  CFG_IBAT2L
#define CFG_DBAT2U  CFG_IBAT2U
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */


	/* Warining: environment is not EMBEDDED in the U-Boot code.
	 * It's stored in flash separately.
	 */
#define CFG_ENV_IS_IN_FLASH	    1
#define CFG_ENV_ADDR		0xFFFF0000
#define CFG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
#define CFG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the MUSENKI board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8245 1
	46	#define CONFIG_MUSENKI 1
	47
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
	51	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	52
	53	#define CONFIG_BOOTDELAY 5
	54
c609719b	55
659e2f67 JL	56	/*
	57	* BOOTP options
	58	*/
	59	#define CONFIG_BOOTP_BOOTFILESIZE
	60	#define CONFIG_BOOTP_BOOTPATH
	61	#define CONFIG_BOOTP_GATEWAY
	62	#define CONFIG_BOOTP_HOSTNAME
	63
	64
8353e139 JL	65	/*
	66	* Command line configuration.
	67	*/
	68	#include <config_cmd_default.h>
c609719b WD	69
	70
	71	/*
	72	* Miscellaneous configurable options
	73	*/
	74	#undef CFG_LONGHELP /* undef to save memory */
	75	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	76	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	77
	78	/* Print Buffer Size
	79	*/
	80	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
	81	#define CFG_MAXARGS 8 /* Max number of command args */
	82	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	83	#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
	84
	85	/*-----------------------------------------------------------------------
	86	* PCI stuff
	87	*-----------------------------------------------------------------------
	88	*/
	89	#define CONFIG_PCI /* include pci support */
	90	#undef CONFIG_PCI_PNP
	91
	92	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	93
	94	#define CONFIG_TULIP
	95
	96	#define PCI_ENET0_IOADDR 0x80000000
	97	#define PCI_ENET0_MEMADDR 0x80000000
	98	#define PCI_ENET1_IOADDR 0x81000000
	99	#define PCI_ENET1_MEMADDR 0x81000000
	100
	101
	102	/*-----------------------------------------------------------------------
	103	* Start addresses for the final memory configuration
	104	* (Set up by the startup code)
	105	* Please note that CFG_SDRAM_BASE _must_ start at 0
	106	*/
	107	#define CFG_SDRAM_BASE 0x00000000
	108
	109	#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
	110	#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
	111	#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
	112
	113	/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
	114	* reset vector is actually located at FFB00100, but the 8245
	115	* takes care of us.
	116	*/
	117	#define CFG_RESET_ADDRESS 0xFFF00100
	118
	119	#define CFG_EUMB_ADDR 0xFC000000
	120
	121	#define CFG_MONITOR_BASE TEXT_BASE
	122	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	123	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	124
	125	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
	126	#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
	127
	128	/* Maximum amount of RAM.
	129	*/
	130	#define CFG_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */
	131
	132
133	#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
134	#undef CFG_RAMBOOT
135	#else
136	#define CFG_RAMBOOT
137	#endif
138
139	/*
140	* NS16550 Configuration
141	*/
142	#define CFG_NS16550
143	#define CFG_NS16550_SERIAL
144
145	#define CFG_NS16550_REG_SIZE 1
146
147	#define CFG_NS16550_CLK get_bus_freq(0)
148
149	#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
150	#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
151
152	/*-----------------------------------------------------------------------
153	* Definitions for initial stack pointer and data area
154	*/
155
156	/* #define CFG_MONITOR_BASE TEXT_BASE */
157	/#define CFG_GBL_DATA_SIZE 256/
158	#define CFG_GBL_DATA_SIZE 128
159	#define CFG_INIT_RAM_ADDR 0x40000000
160	#define CFG_INIT_RAM_END 0x1000
161	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
162
163
164	/*
165	* Low Level Configuration Settings
166	* (address mappings, register initial values, etc.)
167	* You should know what you are doing if you make changes here.
168	* For the detail description refer to the MPC8240 user's manual.
169	*/
170
171	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
172	#define CFG_HZ 1000
173
174	/* Bit-field values for MCCR1.
175	*/
176	#define CFG_ROMNAL 7
177	#define CFG_ROMFAL 11
178	#define CFG_DBUS_SIZE 0x3
179
180	/* Bit-field values for MCCR2.
181	*/
182	#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
183	#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
184
185	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
186	*/
187	#define CFG_BSTOPRE 121
188
189	/* Bit-field values for MCCR3.
190	*/
191	#define CFG_REFREC 8 /* Refresh to activate interval */
192
193	/* Bit-field values for MCCR4.
194	*/
195	#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
196	#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
197	#define CFG_ACTORW 3 /* FIXME was 2 */
198	#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
199	#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
200	#define CFG_REGISTERD_TYPE_BUFFER 1
201	#define CFG_EXTROM 1
202	#define CFG_REGDIMM 0
203
204	#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
205
206	#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
207
208	/* Memory bank settings.
209	* Only bits 20-29 are actually used from these vales to set the
210	* start/end addresses. The upper two bits will always be 0, and the lower
211	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
212	* address. Refer to the MPC8240 book.
213	*/
214
215	#define CFG_BANK0_START 0x00000000
216	#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
217	#define CFG_BANK0_ENABLE 1
218	#define CFG_BANK1_START 0x3ff00000
219	#define CFG_BANK1_END 0x3fffffff
220	#define CFG_BANK1_ENABLE 0
221	#define CFG_BANK2_START 0x3ff00000
222	#define CFG_BANK2_END 0x3fffffff
223	#define CFG_BANK2_ENABLE 0
224	#define CFG_BANK3_START 0x3ff00000
225	#define CFG_BANK3_END 0x3fffffff
226	#define CFG_BANK3_ENABLE 0
227	#define CFG_BANK4_START 0x3ff00000
228	#define CFG_BANK4_END 0x3fffffff
229	#define CFG_BANK4_ENABLE 0
230	#define CFG_BANK5_START 0x3ff00000
231	#define CFG_BANK5_END 0x3fffffff
232	#define CFG_BANK5_ENABLE 0
233	#define CFG_BANK6_START 0x3ff00000
234	#define CFG_BANK6_END 0x3fffffff
235	#define CFG_BANK6_ENABLE 0
236	#define CFG_BANK7_START 0x3ff00000
237	#define CFG_BANK7_END 0x3fffffff
238	#define CFG_BANK7_ENABLE 0
239
240	#define CFG_ODCR 0xff
241
242	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
243	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
244
245	#define CFG_IBAT1L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
246	#define CFG_IBAT1U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
247
248	#define CFG_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
249	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
250
251	#define CFG_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
252	#define CFG_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
253
254	#define CFG_DBAT0L CFG_IBAT0L
255	#define CFG_DBAT0U CFG_IBAT0U
256	#define CFG_DBAT1L CFG_IBAT1L
257	#define CFG_DBAT1U CFG_IBAT1U
258	#define CFG_DBAT2L CFG_IBAT2L
259	#define CFG_DBAT2U CFG_IBAT2U
260	#define CFG_DBAT3L CFG_IBAT3L
261	#define CFG_DBAT3U CFG_IBAT3U
262
263	/*
264	* For booting Linux, the board info and command line data
265	* have to be in the first 8 MB of memory, since this is
266	* the maximum mapped by the Linux kernel during initialization.
267	*/
268	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
269
270	/*-----------------------------------------------------------------------
271	* FLASH organization
272	*/
273	#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */
274	#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
275
276	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
277	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
278
279
280	/* Warining: environment is not EMBEDDED in the U-Boot code.
281	* It's stored in flash separately.
282	*/
283	#define CFG_ENV_IS_IN_FLASH 1
284	#define CFG_ENV_ADDR 0xFFFF0000
285	#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */
286	#define CFG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */
287
288	/*-----------------------------------------------------------------------
289	* Cache Configuration
290	*/
291	#define CFG_CACHELINE_SIZE 32
8353e139	292	#if defined(CONFIG_CMD_KGDB)
c609719b WD	293	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	294	#endif
	295
	296	/*
	297	* Internal Definitions
	298	*
	299	* Boot Flags
	300	*/
	301	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	302	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	303
c609719b	304	#endif /* __CONFIG_H */