[J-u-boot.git] / include / configs / GEN860T.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Keith Outwater, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config_GEN860T.h - board specific configuration options
 */

#ifndef __CONFIG_GEN860T_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC860
#define CONFIG_GEN860T

/*
 * Identify the board
 */
#if !defined(CONFIG_SC)
#define CONFIG_IDENT_STRING				" B2"
#else
#define CONFIG_IDENT_STRING				" SC"
#endif

/*
 * Don't depend on the RTC clock to determine clock frequency -
 * the 860's internal rtc uses a 32.768 KHz clock which is
 * generated by the DS1337 - and the DS1337 clock can be turned off.
 */
#if !defined(CONFIG_SC)
#define	CONFIG_8xx_GCLK_FREQ			66600000
#else
#define	CONFIG_8xx_GCLK_FREQ			48000000
#endif

/*
 * The RS-232 console port is on SMC1
 */
#define	CONFIG_8xx_CONS_SMC1
#define CONFIG_BAUDRATE					38400

/*
 * Set allowable console baud rates
 */
#define CFG_BAUDRATE_TABLE				{ 9600,		\
							 		 	  19200,	\
							 		 	  38400,	\
									 	  57600,	\
									 	  115200,	\
										}

/*
 * Print console information
 */
#undef	 CFG_CONSOLE_INFO_QUIET

/*
 * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
 */
#define CONFIG_BOOTDELAY				5

/*
 * Pass the clock frequency to the Linux kernel in units of MHz
 */
#define	CONFIG_CLOCKS_IN_MHZ

#define CONFIG_PREBOOT		\
	"echo;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	\
	"bootp;" \
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm"

/*
 * Turn off echo for serial download by default.  Allow baud rate to be changed
 * for downloads
 */
#undef	CONFIG_LOADS_ECHO
#define	CFG_LOADS_BAUD_CHANGE

/*
 * Set default load address for tftp network downloads
 */
#define	CFG_TFTP_LOADADDR				0x01000000

/*
 * Turn off the watchdog timer
 */
#undef	CONFIG_WATCHDOG

/*
 * Do not reboot if a panic occurs
 */
#define CONFIG_PANIC_HANG

/*
 * Enable the status LED
 */
#define	CONFIG_STATUS_LED

/*
 * Reset address. We pick an address such that when an instruction
 * is executed at that address, a machine check exception occurs
 */
#define CFG_RESET_ADDRESS				((ulong) -1)

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * The GEN860T network interface uses the on-chip 10/100 FEC with
 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 * MII address is hardwired on the board to zero.
 */
#define CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#define CONFIG_MII
#define CONFIG_PHY_ADDR         		0

/*
 * Set default IP stuff just to get bootstrap entries into the
 * environment so that we can autoscript the full default environment.
 */
#define CONFIG_ETHADDR					9a:52:63:15:85:25
#define CONFIG_SERVERIP					10.0.4.201
#define CONFIG_IPADDR					10.0.4.111

/*
 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 * the MPC860T I2C interface.
 */
#define CFG_I2C_EEPROM_ADDR				0x50
#define CFG_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
#define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
#define CFG_ENV_EEPROM_SIZE				(32 * 1024)

/*
 * Enable I2C and select the hardware/software driver
 */
#define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/

#ifdef CONFIG_HARD_I2C
#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
#endif

#ifdef CONFIG_SOFT_I2C
#define PB_SCL				0x00000020		/* PB 26					*/
#define PB_SDA				0x00000010		/* PB 27 					*/
#define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ			((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
								else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
								else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY			udelay(5)		/* 1/4 I2C clock duration	*/
#endif

/*
 * Allow environment overwrites by anyone
 */
#define CONFIG_ENV_OVERWRITE

#if !defined(CONFIG_SC)
/*
 * The MPC860's internal RTC is horribly broken in rev D masks. Three
 * internal MPC860T circuit nodes were inadvertently left floating; this
 * causes KAPWR current in power down mode to be three orders of magnitude
 * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 * reasonable battery can keep that kind RTC running during powerdown for any
 * length of time, so we use an external RTC on the I2C bus instead.
 */
#define CONFIG_RTC_DS1337
#define CFG_I2C_RTC_ADDR				0x68

#else
/*
 * No external RTC on SC variant, so we're stuck with the internal one.
 */
#define	CONFIG_RTC_MPC8xx
#endif

/*
 * Power On Self Test support
 */
#define CONFIG_POST			  ( CFG_POST_CACHE		| \
								CFG_POST_MEMORY		| \
								CFG_POST_CPU		| \
								CFG_POST_UART		| \
								CFG_POST_SPR )


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG

#if !defined(CONFIG_SC)
    #define CONFIG_CMD_DOC
#endif

#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif

/*
 * There is no IDE/PCMCIA hardware support on the board.
 */
#undef  CONFIG_IDE_PCMCIA
#undef  CONFIG_IDE_LED
#undef  CONFIG_IDE_RESET

/*
 * Enable the call to misc_init_r() for miscellaneous platform
 * dependent initialization.
 */
#define CONFIG_MISC_INIT_R

/*
 * Enable call to last_stage_init() so we can twiddle some LEDS :)
 */
#define CONFIG_LAST_STAGE_INIT

/*
 * Virtex2 FPGA configuration support
 */
#define CONFIG_FPGA_COUNT		1
#define CONFIG_FPGA				CFG_XILINX_VIRTEX2
#define CFG_FPGA_PROG_FEEDBACK


#define CFG_NAND_LEGACY

/*
 * Verbose help from command monitor.
 */
#define	CFG_LONGHELP
#if !defined(CONFIG_SC)
#define	CFG_PROMPT			"B2> "
#else
#define	CFG_PROMPT			"SC> "
#endif


/*
 * Use the "hush" command parser
 */
#define	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "

/*
 * Set buffer size for console I/O
 */
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE			1024
#else
#define	CFG_CBSIZE			256
#endif

/*
 * Print buffer size
 */
#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)

/*
 * Maximum number of arguments that a command can accept
 */
#define	CFG_MAXARGS			16

/*
 * Boot argument buffer size
 */
#define CFG_BARGSIZE		CFG_CBSIZE

/*
 * Default memory test range
 */
#define CFG_MEMTEST_START	0x0100000
#define CFG_MEMTEST_END		(CFG_MEMTEST_START  + (128 * 1024))

/*
 * Select the more full-featured memory test
 */
#define	CFG_ALT_MEMTEST

/*
 * Default load address
 */
#define	CFG_LOAD_ADDR		0x01000000

/*
 * Set decrementer frequency (1 ms ticks)
 */
#define	CFG_HZ				1000

/*
 * Device memory map (after SDRAM remap to 0x0):
 *
 * CS		Device				Base Addr	Size
 * ----------------------------------------------------
 * CS0*		Flash				0x40000000	64 M
 * CS1*		SDRAM				0x00000000	16 M
 * CS2*		Disk-On-Chip		0x50000000	32 K
 * CS3*		FPGA				0x60000000	64 M
 * CS4*		SelectMap			0x70000000	32 K
 * CS5*		Mil-Std 1553 I/F	0x80000000	32 K
 * CS6*		Unused
 * CS7*		Unused
 * IMMR		860T Registers		0xfff00000
 */

/*
 * Base addresses and block sizes
 */
#define CFG_IMMR			0xFF000000

#define SDRAM_BASE			0x00000000
#define SDRAM_SIZE			(64 * 1024 * 1024)

#define FLASH_BASE			0x40000000
#define FLASH_SIZE			(16 * 1024 * 1024)

#define DOC_BASE			0x50000000
#define DOC_SIZE			(32 * 1024)

#define FPGA_BASE			0x60000000
#define FPGA_SIZE			(64 * 1024 * 1024)

#define SELECTMAP_BASE		0x70000000
#define SELECTMAP_SIZE		(32 * 1024)

#define M1553_BASE			0x80000000
#define M1553_SIZE			(64 * 1024)

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR		CFG_IMMR
#define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE			SDRAM_BASE

/*
 * FLASH organization
 */
#define CFG_FLASH_BASE			FLASH_BASE
#define CFG_FLASH_SIZE			FLASH_SIZE
#define CFG_FLASH_SECT_SIZE		(128 * 1024)
#define CFG_MAX_FLASH_BANKS		1
#define CFG_MAX_FLASH_SECT		128

/*
 * The timeout values are for an entire chip and are in milliseconds.
 * Yes I know that the write timeout is huge.  Accroding to the
 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 * case VCC and temp after 100K programming cycles.  It works out
 * to 280 minutes (might as well be forever).
 */
#define CFG_FLASH_ERASE_TOUT	(CFG_MAX_FLASH_SECT * 5000)
#define CFG_FLASH_WRITE_TOUT	(CFG_MAX_FLASH_SECT * 128 * 1024 * 1)

/*
 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 */
#define	CFG_DIRECT_FLASH_TFTP

/*
 * Reserve memory for U-Boot.
 */
#define CFG_MAX_UBOOT_SECTS		4
#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
#define CFG_MONITOR_BASE		CFG_FLASH_BASE

/*
 * Select environment placement.  NOTE that u-boot.lds must
 * be edited if this is changed!
 */
#undef	CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_EEPROM

#if defined(CFG_ENV_IS_IN_EEPROM)
#define CFG_ENV_SIZE			(2 * 1024)
#define CFG_ENV_OFFSET			(CFG_ENV_EEPROM_SIZE - (8 * 1024))
#else
#define CFG_ENV_SIZE			0x1000
#define CFG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE

/*
 * This ultimately gets passed right into the linker script, so we have to
 * use a number :(
 */
#define CFG_ENV_OFFSET			0x060000
#endif

/*
 * Reserve memory for malloc()
 */
#define	CFG_MALLOC_LEN		(128 * 1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 * 1024 * 1024)

/*
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
#endif

/*------------------------------------------------------------------------
 * SYPCR - System Protection Control							UM 11-9
 * -----------------------------------------------------------------------
 * SYPCR can only be written once after reset!
 *
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	( SYPCR_SWTC	| \
					  SYPCR_BMT 	| \
					  SYPCR_BME 	| \
					  SYPCR_SWF 	| \
					  SYPCR_SWE 	| \
					  SYPCR_SWRI	| \
					  SYPCR_SWP		  \
					)
#else
#define CFG_SYPCR	( SYPCR_SWTC	| \
					  SYPCR_BMT 	| \
					  SYPCR_BME 	| \
					  SYPCR_SWF 	| \
					  SYPCR_SWP		  \
					)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration							UM 11-6
 *-----------------------------------------------------------------------
 * Set debug pin mux, enable SPKROUT and GPLB5*.
 */
#define CFG_SIUMCR	( SIUMCR_DBGC11 | \
					  SIUMCR_DBPC11 | \
					  SIUMCR_MLRC11	| \
					  SIUMCR_GB5E	  \
					)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control							UM 11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freeze enabled
 */
#define CFG_TBSCR	( TBSCR_REFA | \
					  TBSCR_REFB | \
					  TBSCR_TBF	   \
					)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register			UM 11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	( RTCSC_SEC	| \
					  RTCSC_ALR | \
					  RTCSC_RTF | \
					  RTCSC_RTE	  \
					)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control				UM 11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	( PISCR_PS		| \
					  PISCR_PITF	  \
					)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register			UM 15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit. Set MF for 1:2:1 mode.
 */
#define CFG_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
					  PLPRCR_SPLSS	| \
					  PLPRCR_TEXPS	| \
					  PLPRCR_TMIST	  \
					)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register				UM 15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK   SCCR_EBDF11

#if !defined(CONFIG_SC)
#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
					  SCCR_DFNL000		| \
					  SCCR_DFNH000		  \
					)
#else
#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
					  SCCR_DFNL000		| \
					  SCCR_DFNH000		| \
					  SCCR_RTDIV		| \
					  SCCR_RTSEL		  \
					)
#endif

/*-----------------------------------------------------------------------
 * DER - Debug Enable Register									UM 37-46
 *-----------------------------------------------------------------------
 * Mask all events that can cause entry into debug mode
 */
#define CFG_DER				0

/*
 * Initialize Memory Controller:
 *
 * BR0 and OR0 (FLASH memory)
 */
#define FLASH_BASE0_PRELIM	FLASH_BASE

/*
 * Flash address mask
 */
#define CFG_PRELIM_OR_AM	0xfe000000

/*
 * FLASH timing:
 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 */
#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
							  OR_ACS_DIV2	| \
							  OR_BI			| \
							  OR_SCY_2_CLK	| \
							  OR_TRLX		| \
							  OR_EHTR		  \
							)

#define CFG_OR0_PRELIM	( CFG_PRELIM_OR_AM		| \
						  CFG_OR_TIMING_FLASH	  \
						)

#define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
						  BR_MS_GPCM						| \
						  BR_PS_8							| \
						  BR_V 								  \
						)

/*
 * SDRAM configuration
 */
#define CFG_OR1_AM	0xfc000000
#define CFG_OR1		( (CFG_OR1_AM & OR_AM_MSK)	| \
					  OR_CSNT_SAM				  \
					)

#define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
					  BR_MS_UPMA 				| \
					  BR_PS_32	 				| \
					  BR_V 						  \
					)

/*
 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 * of 256 MBit SDRAM
 */
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16

/*
 * Periodic timer for refresh @ 33 MHz system clock
 */
#define CFG_MAMR_PTA	64

/*
 * MAMR settings for SDRAM
 */
#define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
						  MAMR_PTAE	    			| \
						  MAMR_AMA_TYPE_1			| \
						  MAMR_DSA_1_CYCL 			| \
						  MAMR_G0CLA_A10			| \
						  MAMR_RLFA_1X				| \
						  MAMR_WLFA_1X				| \
						  MAMR_TLFA_4X				  \
						)

/*
 * CS2* configuration for Disk On Chip:
 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 * no burst.
 */
#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \
						  OR_CSNT_SAM				| \
						  OR_ACS_DIV2				| \
						  OR_BI						| \
						  OR_SCY_2_CLK				| \
						  OR_TRLX					| \
						  OR_EHTR					  \
						)

#define CFG_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
						  BR_PS_8					| \
						  BR_MS_GPCM				| \
						  BR_V						  \
						)

/*
 * CS3* configuration for FPGA:
 * 33 MHz bus with SCY=15, no burst.
 * The FPGA uses TA and TEA to terminate bus cycles, but we
 * clear SETA and set the cycle length to a large number so that
 * the cycle will still complete even if there is a configuration
 * error that prevents TA from asserting on FPGA accesss.
 */
#define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
						  OR_SCY_15_CLK				| \
						  OR_BI 					  \
						)

#define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
						  BR_PS_32					| \
						  BR_MS_GPCM				| \
						  BR_V		  				  \
						)
/*
 * CS4* configuration for FPGA SelectMap configuration interface.
 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 * of GCLK1_50
 */
#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \
						  OR_G5LS						| \
						  OR_BI							  \
						)

#define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
						  BR_PS_8						| \
						  BR_MS_UPMB					| \
						  BR_V			  				  \
						)

/*
 * CS5* configuration for Mil-Std 1553 databus interface.
 * 33 MHz bus, GPCM, no burst.
 * The 1553 interface  uses TA and TEA to terminate bus cycles,
 * but we clear SETA and set the cycle length to a large number so that
 * the cycle will still complete even if there is a configuration
 * error that prevents TA from asserting on FPGA accesss.
 */
#define CFG_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
						  OR_SCY_15_CLK				| \
						  OR_EHTR					| \
						  OR_TRLX					| \
						  OR_CSNT_SAM				| \
						  OR_BI						  \
						)

#define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
						  BR_PS_16					| \
						  BR_MS_GPCM				| \
						  BR_V			  			  \
						)

/*
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02	/* Software reboot					*/

/*
 * Disk On Chip (millenium) configuration
 */
#if !defined(CONFIG_SC)
#define CFG_MAX_DOC_DEVICE	1
#undef	CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#undef	CFG_DOC_PASSIVE_PROBE
#endif

/*
 * FEC interrupt assignment
 */
#define FEC_INTERRUPT   SIU_LEVEL1

/*
 * Sanity checks
 */
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#endif	/* __CONFIG_GEN860T_H */

/* vim: set ts=4 tw=78 ai shiftwidth=4: */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	* Keith Outwater, [email protected]
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config_GEN860T.h - board specific configuration options
	27	*/
	28
	29	#ifndef __CONFIG_GEN860T_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	*/
	35	#define CONFIG_MPC860
	36	#define CONFIG_GEN860T
	37
	38	/*
	39	* Identify the board
	40	*/
7aa78614 WD	41	#if !defined(CONFIG_SC)
	42	#define CONFIG_IDENT_STRING " B2"
	43	#else
	44	#define CONFIG_IDENT_STRING " SC"
	45	#endif
5b1d7137 WD	46
	47	/*
	48	* Don't depend on the RTC clock to determine clock frequency -
	49	* the 860's internal rtc uses a 32.768 KHz clock which is
	50	* generated by the DS1337 - and the DS1337 clock can be turned off.
	51	*/
7aa78614	52	#if !defined(CONFIG_SC)
8bde7f77	53	#define CONFIG_8xx_GCLK_FREQ 66600000
7aa78614 WD	54	#else
	55	#define CONFIG_8xx_GCLK_FREQ 48000000
	56	#endif
5b1d7137 WD	57
	58	/*
	59	* The RS-232 console port is on SMC1
	60	*/
	61	#define CONFIG_8xx_CONS_SMC1
	62	#define CONFIG_BAUDRATE 38400
	63
	64	/*
	65	* Set allowable console baud rates
	66	*/
	67	#define CFG_BAUDRATE_TABLE { 9600, \
	68	19200, \
	69	38400, \
	70	57600, \
	71	115200, \
	72	}
	73
	74	/*
	75	* Print console information
	76	*/
	77	#undef CFG_CONSOLE_INFO_QUIET
	78
	79	/*
	80	* Set the autoboot delay in seconds. A delay of -1 disables autoboot
	81	*/
	82	#define CONFIG_BOOTDELAY 5
	83
	84	/*
	85	* Pass the clock frequency to the Linux kernel in units of MHz
	86	*/
	87	#define CONFIG_CLOCKS_IN_MHZ
	88
	89	#define CONFIG_PREBOOT \
	90	"echo;echo"
	91
	92	#undef CONFIG_BOOTARGS
	93	#define CONFIG_BOOTCOMMAND \
	94	"bootp;" \
fe126d8b WD	95	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	96	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
5b1d7137 WD	97	"bootm"
	98
	99	/*
	100	* Turn off echo for serial download by default. Allow baud rate to be changed
	101	* for downloads
	102	*/
	103	#undef CONFIG_LOADS_ECHO
	104	#define CFG_LOADS_BAUD_CHANGE
	105
	106	/*
	107	* Set default load address for tftp network downloads
	108	*/
	109	#define CFG_TFTP_LOADADDR 0x01000000
	110
	111	/*
	112	* Turn off the watchdog timer
	113	*/
	114	#undef CONFIG_WATCHDOG
	115
	116	/*
	117	* Do not reboot if a panic occurs
	118	*/
	119	#define CONFIG_PANIC_HANG
	120
	121	/*
	122	* Enable the status LED
	123	*/
	124	#define CONFIG_STATUS_LED
	125
	126	/*
	127	* Reset address. We pick an address such that when an instruction
	128	* is executed at that address, a machine check exception occurs
	129	*/
	130	#define CFG_RESET_ADDRESS ((ulong) -1)
	131
	132	/*
	133	* BOOTP options
	134	*/
5d2ebe1b JL	135	#define CONFIG_BOOTP_SUBNETMASK
	136	#define CONFIG_BOOTP_GATEWAY
	137	#define CONFIG_BOOTP_HOSTNAME
	138	#define CONFIG_BOOTP_BOOTPATH
	139	#define CONFIG_BOOTP_BOOTFILESIZE
	140
5b1d7137 WD	141
	142	/*
	143	* The GEN860T network interface uses the on-chip 10/100 FEC with
	144	* an Intel LXT971A PHY connected to the 860T's MII. The PHY's
	145	* MII address is hardwired on the board to zero.
	146	*/
	147	#define CONFIG_FEC_ENET
	148	#define CFG_DISCOVER_PHY
	149	#define CONFIG_MII
	150	#define CONFIG_PHY_ADDR 0
	151
	152	/*
	153	* Set default IP stuff just to get bootstrap entries into the
	154	* environment so that we can autoscript the full default environment.
	155	*/
	156	#define CONFIG_ETHADDR 9a:52:63:15:85:25
7aa78614	157	#define CONFIG_SERVERIP 10.0.4.201
5b1d7137 WD	158	#define CONFIG_IPADDR 10.0.4.111
	159
	160	/*
	161	* This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
	162	* the MPC860T I2C interface.
	163	*/
	164	#define CFG_I2C_EEPROM_ADDR 0x50
	165	#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	166	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
	167	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
	168	#define CFG_ENV_EEPROM_SIZE (32 * 1024)
	169
5b1d7137	170	/*
7aa78614	171	* Enable I2C and select the hardware/software driver
5b1d7137	172	*/
7aa78614 WD	173	#define CONFIG_HARD_I2C 1 /* CPM based I2C */
	174	#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
	175
	176	#ifdef CONFIG_HARD_I2C
	177	#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
	178	#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
	179	#endif
	180
	181	#ifdef CONFIG_SOFT_I2C
5b1d7137 WD	182	#define PB_SCL 0x00000020 /* PB 26 */
5b1d7137 WD	183	#define PB_SDA 0x00000010 /* PB 27 */
5b1d7137 WD	184	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	185	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	186	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	187	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	188	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	189	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	190	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	191	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	192	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
7aa78614	193	#endif
5b1d7137 WD	194
	195	/*
	196	* Allow environment overwrites by anyone
	197	*/
	198	#define CONFIG_ENV_OVERWRITE
	199
7aa78614	200	#if !defined(CONFIG_SC)
5b1d7137 WD	201	/*
	202	* The MPC860's internal RTC is horribly broken in rev D masks. Three
	203	* internal MPC860T circuit nodes were inadvertently left floating; this
	204	* causes KAPWR current in power down mode to be three orders of magnitude
	205	* higher than specified in the datasheet (from 10 uA to 10 mA). No
	206	* reasonable battery can keep that kind RTC running during powerdown for any
	207	* length of time, so we use an external RTC on the I2C bus instead.
	208	*/
5b1d7137	209	#define CONFIG_RTC_DS1337
8bde7f77	210	#define CFG_I2C_RTC_ADDR 0x68
5b1d7137	211
7aa78614	212	#else
5b1d7137	213	/*
7aa78614	214	* No external RTC on SC variant, so we're stuck with the internal one.
5b1d7137	215	*/
7aa78614 WD	216	#define CONFIG_RTC_MPC8xx
	217	#endif
	218
	219	/*
	220	* Power On Self Test support
	221	*/
	222	#define CONFIG_POST ( CFG_POST_CACHE \| \
	223	CFG_POST_MEMORY \| \
	224	CFG_POST_CPU \| \
	225	CFG_POST_UART \| \
	226	CFG_POST_SPR )
	227
60a0876b	228
5b1d7137	229	/*
60a0876b JL	230	* Command line configuration.
	231	*/
	232	#include <config_cmd_default.h>
	233
	234	#define CONFIG_CMD_ASKENV
	235	#define CONFIG_CMD_DHCP
	236	#define CONFIG_CMD_I2C
	237	#define CONFIG_CMD_EEPROM
	238	#define CONFIG_CMD_REGINFO
	239	#define CONFIG_CMD_IMMAP
	240	#define CONFIG_CMD_ELF
	241	#define CONFIG_CMD_DATE
	242	#define CONFIG_CMD_FPGA
	243	#define CONFIG_CMD_MII
	244	#define CONFIG_CMD_BEDBUG
7aa78614 WD	245
7aa78614 WD	246	#if !defined(CONFIG_SC)
60a0876b	247	#define CONFIG_CMD_DOC
7aa78614	248	#endif
5b1d7137	249
af075ee9	250	#ifdef CONFIG_POST
cdd917a4	251	#define CONFIG_CMD_DIAG
af075ee9	252	#endif
60a0876b	253
5b1d7137 WD	254	/*
	255	* There is no IDE/PCMCIA hardware support on the board.
	256	*/
	257	#undef CONFIG_IDE_PCMCIA
	258	#undef CONFIG_IDE_LED
	259	#undef CONFIG_IDE_RESET
	260
	261	/*
	262	* Enable the call to misc_init_r() for miscellaneous platform
	263	* dependent initialization.
	264	*/
	265	#define CONFIG_MISC_INIT_R
	266
	267	/*
	268	* Enable call to last_stage_init() so we can twiddle some LEDS :)
	269	*/
	270	#define CONFIG_LAST_STAGE_INIT
	271
	272	/*
	273	* Virtex2 FPGA configuration support
	274	*/
	275	#define CONFIG_FPGA_COUNT 1
	276	#define CONFIG_FPGA CFG_XILINX_VIRTEX2
	277	#define CFG_FPGA_PROG_FEEDBACK
	278
	279
addb2e16 BS	280	#define CFG_NAND_LEGACY
addb2e16 BS	281
5b1d7137 WD	282	/*
	283	* Verbose help from command monitor.
	284	*/
	285	#define CFG_LONGHELP
7aa78614 WD	286	#if !defined(CONFIG_SC)
	287	#define CFG_PROMPT "B2> "
	288	#else
	289	#define CFG_PROMPT "SC> "
	290	#endif
	291
5b1d7137 WD	292
	293	/*
	294	* Use the "hush" command parser
	295	*/
	296	#define CFG_HUSH_PARSER
	297	#define CFG_PROMPT_HUSH_PS2 "> "
	298
	299	/*
	300	* Set buffer size for console I/O
	301	*/
60a0876b	302	#if defined(CONFIG_CMD_KGDB)
5b1d7137 WD	303	#define CFG_CBSIZE 1024
	304	#else
	305	#define CFG_CBSIZE 256
	306	#endif
	307
	308	/*
	309	* Print buffer size
	310	*/
	311	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
	312
	313	/*
	314	* Maximum number of arguments that a command can accept
	315	*/
	316	#define CFG_MAXARGS 16
	317
	318	/*
	319	* Boot argument buffer size
	320	*/
	321	#define CFG_BARGSIZE CFG_CBSIZE
	322
	323	/*
	324	* Default memory test range
	325	*/
	326	#define CFG_MEMTEST_START 0x0100000
	327	#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
	328
	329	/*
	330	* Select the more full-featured memory test
	331	*/
	332	#define CFG_ALT_MEMTEST
	333
	334	/*
	335	* Default load address
	336	*/
	337	#define CFG_LOAD_ADDR 0x01000000
	338
	339	/*
	340	* Set decrementer frequency (1 ms ticks)
	341	*/
	342	#define CFG_HZ 1000
	343
	344	/*
	345	* Device memory map (after SDRAM remap to 0x0):
	346	*
	347	* CS Device Base Addr Size
	348	* ----------------------------------------------------
	349	* CS0* Flash 0x40000000 64 M
	350	* CS1* SDRAM 0x00000000 16 M
	351	* CS2* Disk-On-Chip 0x50000000 32 K
	352	* CS3* FPGA 0x60000000 64 M
	353	* CS4* SelectMap 0x70000000 32 K
	354	* CS5* Mil-Std 1553 I/F 0x80000000 32 K
	355	* CS6* Unused
	356	* CS7* Unused
	357	* IMMR 860T Registers 0xfff00000
	358	*/
	359
	360	/*
	361	* Base addresses and block sizes
	362	*/
	363	#define CFG_IMMR 0xFF000000
	364
	365	#define SDRAM_BASE 0x00000000
	366	#define SDRAM_SIZE (64 * 1024 * 1024)
367
368	#define FLASH_BASE 0x40000000
369	#define FLASH_SIZE (16 * 1024 * 1024)
370
371	#define DOC_BASE 0x50000000
372	#define DOC_SIZE (32 * 1024)
373
374	#define FPGA_BASE 0x60000000
375	#define FPGA_SIZE (64 * 1024 * 1024)
376
377	#define SELECTMAP_BASE 0x70000000
378	#define SELECTMAP_SIZE (32 * 1024)
379
380	#define M1553_BASE 0x80000000
381	#define M1553_SIZE (64 * 1024)
382
383	/*
384	* Definitions for initial stack pointer and data area (in DPRAM)
385	*/
386	#define CFG_INIT_RAM_ADDR CFG_IMMR
387	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
388	#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
389	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
390	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
391
392	/*
393	* Start addresses for the final memory configuration
394	* (Set up by the startup code)
395	* Please note that CFG_SDRAM_BASE _must_ start at 0
396	*/
397	#define CFG_SDRAM_BASE SDRAM_BASE
398
399	/*
400	* FLASH organization
401	*/
402	#define CFG_FLASH_BASE FLASH_BASE
403	#define CFG_FLASH_SIZE FLASH_SIZE
404	#define CFG_FLASH_SECT_SIZE (128 * 1024)
405	#define CFG_MAX_FLASH_BANKS 1
406	#define CFG_MAX_FLASH_SECT 128
407
408	/*
409	* The timeout values are for an entire chip and are in milliseconds.
410	* Yes I know that the write timeout is huge. Accroding to the
411	* datasheet a single byte takes 630 uS (round to 1 ms) max at worst
412	* case VCC and temp after 100K programming cycles. It works out
413	* to 280 minutes (might as well be forever).
414	*/
415	#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
416	#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
417
418	/*
419	* Allow direct writes to FLASH from tftp transfers ( dangerous )
420	*/
421	#define CFG_DIRECT_FLASH_TFTP
422
423	/*
424	* Reserve memory for U-Boot.
425	*/
7aa78614 WD	426	#define CFG_MAX_UBOOT_SECTS 4
	427	#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
	428	#define CFG_MONITOR_BASE CFG_FLASH_BASE
5b1d7137 WD	429
	430	/*
	431	* Select environment placement. NOTE that u-boot.lds must
	432	* be edited if this is changed!
	433	*/
	434	#undef CFG_ENV_IS_IN_FLASH
	435	#define CFG_ENV_IS_IN_EEPROM
	436
	437	#if defined(CFG_ENV_IS_IN_EEPROM)
	438	#define CFG_ENV_SIZE (2 * 1024)
	439	#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
	440	#else
7aa78614 WD	441	#define CFG_ENV_SIZE 0x1000
	442	#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
	443
	444	/*
	445	* This ultimately gets passed right into the linker script, so we have to
	446	* use a number :(
	447	*/
	448	#define CFG_ENV_OFFSET 0x060000
5b1d7137 WD	449	#endif
	450
	451	/*
	452	* Reserve memory for malloc()
	453	*/
	454	#define CFG_MALLOC_LEN (128 * 1024)
	455
	456	/*
	457	* For booting Linux, the board info and command line data
	458	* have to be in the first 8 MB of memory, since this is
	459	* the maximum mapped by the Linux kernel during initialization.
	460	*/
	461	#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
	462
	463	/*
	464	* Cache Configuration
	465	*/
	466	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
60a0876b	467	#if defined(CONFIG_CMD_KGDB)
5b1d7137 WD	468	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
	469	#endif
	470
	471	/*------------------------------------------------------------------------
7aa78614	472	* SYPCR - System Protection Control UM 11-9
5b1d7137 WD	473	* -----------------------------------------------------------------------
	474	* SYPCR can only be written once after reset!
	475	*
	476	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	477	*/
	478	#if defined(CONFIG_WATCHDOG)
	479	#define CFG_SYPCR ( SYPCR_SWTC \| \
	480	SYPCR_BMT \| \
	481	SYPCR_BME \| \
	482	SYPCR_SWF \| \
	483	SYPCR_SWE \| \
	484	SYPCR_SWRI \| \
	485	SYPCR_SWP \
	486	)
	487	#else
	488	#define CFG_SYPCR ( SYPCR_SWTC \| \
	489	SYPCR_BMT \| \
	490	SYPCR_BME \| \
	491	SYPCR_SWF \| \
	492	SYPCR_SWP \
	493	)
	494	#endif
	495
	496	/*-----------------------------------------------------------------------
	497	* SIUMCR - SIU Module Configuration UM 11-6
	498	*-----------------------------------------------------------------------
	499	* Set debug pin mux, enable SPKROUT and GPLB5*.
	500	*/
	501	#define CFG_SIUMCR ( SIUMCR_DBGC11 \| \
	502	SIUMCR_DBPC11 \| \
	503	SIUMCR_MLRC11 \| \
	504	SIUMCR_GB5E \
	505	)
	506
	507	/*-----------------------------------------------------------------------
	508	* TBSCR - Time Base Status and Control UM 11-26
	509	*-----------------------------------------------------------------------
	510	* Clear Reference Interrupt Status, Timebase freeze enabled
	511	*/
	512	#define CFG_TBSCR ( TBSCR_REFA \| \
	513	TBSCR_REFB \| \
	514	TBSCR_TBF \
	515	)
	516
	517	/*-----------------------------------------------------------------------
	518	* RTCSC - Real-Time Clock Status and Control Register UM 11-27
	519	*-----------------------------------------------------------------------
	520	*/
	521	#define CFG_RTCSC ( RTCSC_SEC \| \
	522	RTCSC_ALR \| \
	523	RTCSC_RTF \| \
	524	RTCSC_RTE \
	525	)
	526
	527	/*-----------------------------------------------------------------------
	528	* PISCR - Periodic Interrupt Status and Control UM 11-31
	529	*-----------------------------------------------------------------------
	530	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	531	*/
	532	#define CFG_PISCR ( PISCR_PS \| \
	533	PISCR_PITF \
	534	)
	535
	536	/*-----------------------------------------------------------------------
537	* PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
538	*-----------------------------------------------------------------------
539	* Reset PLL lock status sticky bit, timer expired status bit and timer
540	* interrupt status bit. Set MF for 1:2:1 mode.
541	*/
542	#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) \| \
543	PLPRCR_SPLSS \| \
544	PLPRCR_TEXPS \| \
545	PLPRCR_TMIST \
546	)
547
548	/*-----------------------------------------------------------------------
549	* SCCR - System Clock and reset Control Register UM 15-27
550	*-----------------------------------------------------------------------
551	* Set clock output, timebase and RTC source and divider,
552	* power management and some other internal clocks
553	*/
554	#define SCCR_MASK SCCR_EBDF11
555
7aa78614	556	#if !defined(CONFIG_SC)
5b1d7137 WD	557	#define CFG_SCCR ( SCCR_TBS \| /* timebase = GCLK/2 */ \
	558	SCCR_COM00 \| /* full strength CLKOUT */ \
	559	SCCR_DFSYNC00 \| /* SYNCLK / 1 (normal) */ \
	560	SCCR_DFBRG00 \| /* BRGCLK / 1 (normal) */ \
	561	SCCR_DFNL000 \| \
	562	SCCR_DFNH000 \
	563	)
7aa78614 WD	564	#else
	565	#define CFG_SCCR ( SCCR_TBS \| /* timebase = GCLK/2 */ \
	566	SCCR_COM00 \| /* full strength CLKOUT */ \
	567	SCCR_DFSYNC00 \| /* SYNCLK / 1 (normal) */ \
	568	SCCR_DFBRG00 \| /* BRGCLK / 1 (normal) */ \
	569	SCCR_DFNL000 \| \
	570	SCCR_DFNH000 \| \
	571	SCCR_RTDIV \| \
	572	SCCR_RTSEL \
	573	)
	574	#endif
5b1d7137 WD	575
	576	/*-----------------------------------------------------------------------
	577	* DER - Debug Enable Register UM 37-46
	578	*-----------------------------------------------------------------------
	579	* Mask all events that can cause entry into debug mode
	580	*/
	581	#define CFG_DER 0
	582
	583	/*
	584	* Initialize Memory Controller:
	585	*
	586	* BR0 and OR0 (FLASH memory)
	587	*/
	588	#define FLASH_BASE0_PRELIM FLASH_BASE
	589
	590	/*
	591	* Flash address mask
	592	*/
	593	#define CFG_PRELIM_OR_AM 0xfe000000
	594
	595	/*
	596	* FLASH timing:
	597	* 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
	598	*/
	599	#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM \| \
	600	OR_ACS_DIV2 \| \
	601	OR_BI \| \
	602	OR_SCY_2_CLK \| \
	603	OR_TRLX \| \
	604	OR_EHTR \
	605	)
	606
	607	#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM \| \
	608	CFG_OR_TIMING_FLASH \
	609	)
	610
	611	#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) \| \
	612	BR_MS_GPCM \| \
	613	BR_PS_8 \| \
	614	BR_V \
	615	)
	616
	617	/*
	618	* SDRAM configuration
	619	*/
	620	#define CFG_OR1_AM 0xfc000000
	621	#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) \| \
	622	OR_CSNT_SAM \
	623	)
	624
	625	#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) \| \
	626	BR_MS_UPMA \| \
	627	BR_PS_32 \| \
	628	BR_V \
	629	)
	630
	631	/*
	632	* Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
	633	* of 256 MBit SDRAM
	634	*/
	635	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
	636
	637	/*
	638	* Periodic timer for refresh @ 33 MHz system clock
639	*/
640	#define CFG_MAMR_PTA 64
641
642	/*
643	* MAMR settings for SDRAM
644	*/
645	#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| \
646	MAMR_PTAE \| \
647	MAMR_AMA_TYPE_1 \| \
648	MAMR_DSA_1_CYCL \| \
649	MAMR_G0CLA_A10 \| \
650	MAMR_RLFA_1X \| \
651	MAMR_WLFA_1X \| \
652	MAMR_TLFA_4X \
653	)
654
655	/*
656	* CS2* configuration for Disk On Chip:
657	* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
658	* no burst.
659	*/
660	#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) \| \
661	OR_CSNT_SAM \| \
662	OR_ACS_DIV2 \| \
663	OR_BI \| \
664	OR_SCY_2_CLK \| \
665	OR_TRLX \| \
666	OR_EHTR \
667	)
668
669	#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) \| \
670	BR_PS_8 \| \
671	BR_MS_GPCM \| \
672	BR_V \
673	)
674
675	/*
676	* CS3* configuration for FPGA:
677	* 33 MHz bus with SCY=15, no burst.
678	* The FPGA uses TA and TEA to terminate bus cycles, but we
679	* clear SETA and set the cycle length to a large number so that
680	* the cycle will still complete even if there is a configuration
681	* error that prevents TA from asserting on FPGA accesss.
682	*/
683	#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) \| \
684	OR_SCY_15_CLK \| \
685	OR_BI \
686	)
687
688	#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) \| \
689	BR_PS_32 \| \
690	BR_MS_GPCM \| \
691	BR_V \
692	)
693	/*
694	* CS4* configuration for FPGA SelectMap configuration interface.
695	* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
696	* of GCLK1_50
697	*/
698	#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) \| \
699	OR_G5LS \| \
700	OR_BI \
701	)
702
703	#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) \| \
704	BR_PS_8 \| \
705	BR_MS_UPMB \| \
706	BR_V \
707	)
708
709	/*
710	* CS5* configuration for Mil-Std 1553 databus interface.
711	* 33 MHz bus, GPCM, no burst.
712	* The 1553 interface uses TA and TEA to terminate bus cycles,
713	* but we clear SETA and set the cycle length to a large number so that
714	* the cycle will still complete even if there is a configuration
715	* error that prevents TA from asserting on FPGA accesss.
716	*/
717	#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) \| \
718	OR_SCY_15_CLK \| \
719	OR_EHTR \| \
720	OR_TRLX \| \
721	OR_CSNT_SAM \| \
722	OR_BI \
723	)
724
725	#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) \| \
726	BR_PS_16 \| \
727	BR_MS_GPCM \| \
728	BR_V \
729	)
730
731	/*
732	* Boot Flags
733	*/
734	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
735	#define BOOTFLAG_WARM 0x02 /* Software reboot */
736
737	/*
738	* Disk On Chip (millenium) configuration
739	*/
7aa78614	740	#if !defined(CONFIG_SC)
5b1d7137 WD	741	#define CFG_MAX_DOC_DEVICE 1
	742	#undef CFG_DOC_SUPPORT_2000
	743	#define CFG_DOC_SUPPORT_MILLENNIUM
	744	#undef CFG_DOC_PASSIVE_PROBE
7aa78614	745	#endif
5b1d7137 WD	746
	747	/*
	748	* FEC interrupt assignment
	749	*/
	750	#define FEC_INTERRUPT SIU_LEVEL1
	751
	752	/*
	753	* Sanity checks
	754	*/
	755	#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
	756	#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
	757	#endif
	758
	759	#endif /* __CONFIG_GEN860T_H */
	760
	761	/* vim: set ts=4 tw=78 ai shiftwidth=4: */