[J-u-boot.git] / include / configs / tuxx1.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *                    Dave Liu <[email protected]>
 *
 * Copyright (C) 2007 Logic Product Development, Inc.
 *                    Peter Barada <[email protected]>
 *
 * Copyright (C) 2007 MontaVista Software, Inc.
 *                    Anton Vorontsov <[email protected]>
 *
 * (C) Copyright 2008
 * Heiko Schocher, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2010-2013
 * Lukas Roggli, KEYMILE Ltd, [email protected]
 * Holger Brunck,  Keymile GmbH, [email protected]
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_KM_BOARD_NAME	"tuxx1"
#define CONFIG_HOSTNAME		"tuxx1"

/*
 * High Level Configuration Options
 */
#define CONFIG_QE	/* Has QE */
#define CONFIG_KM8321	/* Keymile PBEC8321 board specific */

#define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"

/* include common defines/options for all Keymile boards */
#include "km/keymile-common.h"
#include "km/km-powerpc.h"

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN		66000000
#define CONFIG_SYS_CLK_FREQ		66000000
#define CONFIG_83XX_PCICLK		66000000

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * Bus Arbitration Configuration Register (ACR)
 */
#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */

#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CFG_83XX_DDR_USES_CS0

/*
 * Manually set up DDR parameters
 */
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE		2048 /* MB */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE		0xF0000000

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

/* Reserve 768 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/*
 * Init Local Bus Memory Controller:
 *
 * Bank Bus     Machine PortSz  Size  Device
 * ---- ---     ------- ------  -----  ------
 *  0   Local   GPCM    16 bit  256MB FLASH
 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 *
 */
/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
				BR_PS_16 | /* 16 bit port size */ \
				BR_MS_GPCM | /* MSEL = GPCM */ \
				BR_V)

#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
				OR_GPCM_SCY_5 | \
				OR_GPCM_TRLX_SET | OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/*
 * PRIO1/PIGGY on the local bus CS1
 */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)

#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
				BR_PS_8 | /* 8 bit port size */ \
				BR_MS_GPCM | /* MSEL = GPCM */ \
				BR_V)
#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
				OR_GPCM_SCY_2 | \
				OR_GPCM_TRLX_SET | OR_GPCM_EAD)

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* GETH1 */
#define UEC_VERBOSE_DEBUG	1

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */

#ifndef CONFIG_SYS_RAMBOOT
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
					CONFIG_SYS_MONITOR_LEN)
#endif
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#ifndef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
#endif

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else /* CFG_SYS_RAMBOOT */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif /* CFG_SYS_RAMBOOT */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_NUM_I2C_BUSES	4
#define CONFIG_SYS_I2C_MAX_HOPS		1
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	200000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	200000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
		{1, {I2C_NULL_HOP} } }

#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/

#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT		0x000000000
#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
					 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2			HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
					| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
				BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
				BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

/*
 * Internal Definitions
 */
#define BOOTFLASH_START	0xF0000000

#define CONFIG_KM_CONSOLE_TTY	"ttyS0"

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif

#ifndef CONFIG_KM_DEF_ARCH
#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_KM_DEF_ENV						\
	CONFIG_KM_DEF_ARCH						\
	"newenv="							\
		"prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "	\
		"era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"		\
	"unlock=yes\0"							\
	""

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS

#define CONFIG_SYS_DDRCDR (\
	DDRCDR_EN | \
	DDRCDR_PZ_MAXZ | \
	DDRCDR_NZ_MAXZ | \
	DDRCDR_M_ODR)

#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
					 SDRAM_CFG_32_BE | \
					 SDRAM_CFG_SREN | \
					 SDRAM_CFG_HSE)

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))

#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
					 CSCONFIG_ODT_WR_CFG | \
					 CSCONFIG_ROW_BIT_13 | \
					 CSCONFIG_COL_BIT_10)

#define CONFIG_SYS_DDR_MODE	0x47860242
#define CONFIG_SYS_DDR_MODE2	0x8080c000

#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
				 (0 << TIMING_CFG0_WWT_SHIFT) | \
				 (0 << TIMING_CFG0_RRT_SHIFT) | \
				 (0 << TIMING_CFG0_WRT_SHIFT) | \
				 (0 << TIMING_CFG0_RWT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
				 (3 << TIMING_CFG1_PRETOACT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
				 (5 << TIMING_CFG2_CPO_SHIFT))

#define CONFIG_SYS_DDR_TIMING_3	0x00000000

#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE	128

/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP	0x80000000
#define CONFIG_SYS_LCRR_EADC	0x00010000
#define CONFIG_SYS_LCRR_CLKDIV	0x00000002

#define CONFIG_SYS_LBC_LBCR	0x00000000

/*
 * MMU Setup
 */
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
#define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
#define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */
#define	CONFIG_SYS_APP2_SIZE	256 /* Megabytes */

/*
 * Init Local Bus Memory Controller:
 *				      Device on board
 * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 * -----------------------------------------------------------------------------
 *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 *
 *				      Device on board (continued)
 * Bank Bus     Machine PortSz Size   KMTEPR2
 * -----------------------------------------------------------------------------
 *  2   Local   GPCM    8 bit  256MB  NVRAM
 *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 */

/*
 * Configuration for C2 on the local bus
 */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
/* Window size: 256 MB */
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
				 BR_PS_8 | \
				 BR_MS_GPCM | \
				 BR_V)

#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
				 OR_GPCM_CSNT | \
				 OR_GPCM_ACS_DIV4 | \
				 OR_GPCM_SCY_2 | \
				 OR_GPCM_TRLX_SET | \
				 OR_GPCM_EHTR_CLEAR | \
				 OR_GPCM_EAD)

/*
 * Configuration for C3 on the local bus
 */
/* Access window base at PINC3 base */
#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
/* Window size: 256 MB */
#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
				 BR_PS_8 |		\
				 BR_MS_GPCM |		\
				 BR_V)

#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
				 OR_GPCM_CSNT |	\
				 OR_GPCM_ACS_DIV2 | \
				 OR_GPCM_SCY_2 | \
				 OR_GPCM_TRLX_SET | \
				 OR_GPCM_EHTR_CLEAR)

#define CONFIG_SYS_MAMR		(MxMR_GPL_x4DIS | \
				 0x0000c000 | \
				 MxMR_WLFx_2X)

/*
 * MMU Setup
 */
/* APP1: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | \
				 BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
/* 512M should also include APP2... */
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | \
				 BATU_BL_256M | \
				 BATU_VS | \
				 BATU_VP)
#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | \
				 BATL_PP_RW | \
				 BATL_CACHEINHIBIT | \
				 BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

/* APP2:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | \
				 BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | \
				 BATU_BL_256M | \
				 BATU_VS | \
				 BATU_VP)
#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | \
				 BATL_PP_RW | \
				 BATL_CACHEINHIBIT | \
				 BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
dc6033ec HS	2	/*
	3	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	4	* Dave Liu <[email protected]>
	5	*
	6	* Copyright (C) 2007 Logic Product Development, Inc.
	7	* Peter Barada <[email protected]>
	8	*
	9	* Copyright (C) 2007 MontaVista Software, Inc.
	10	* Anton Vorontsov <[email protected]>
	11	*
	12	* (C) Copyright 2008
	13	* Heiko Schocher, DENX Software Engineering, [email protected].
	14	*
47f53649	15	* (C) Copyright 2010-2013
dc6033ec	16	* Lukas Roggli, KEYMILE Ltd, [email protected]
5f2a44d5	17	* Holger Brunck, Keymile GmbH, [email protected]
dc6033ec HS	18	*/
	19
	20	#ifndef __CONFIG_H
	21	#define __CONFIG_H
	22
	23	/*
	24	* High Level Configuration Options
	25	*/
7f4bd9a6	26	#define CONFIG_KM_BOARD_NAME "tuxx1"
5bc0543d	27	#define CONFIG_HOSTNAME "tuxx1"
dc6033ec	28
0e890d4c MS	29	/*
	30	* High Level Configuration Options
	31	*/
	32	#define CONFIG_QE /* Has QE */
	33	#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
	34
	35	#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
	36
fb1b099f MS	37	/* include common defines/options for all Keymile boards */
	38	#include "km/keymile-common.h"
	39	#include "km/km-powerpc.h"
	40
	41	/*
	42	* System Clock Setup
	43	*/
	44	#define CONFIG_83XX_CLKIN 66000000
	45	#define CONFIG_SYS_CLK_FREQ 66000000
	46	#define CONFIG_83XX_PCICLK 66000000
	47
	48	/*
	49	* IMMR new address
	50	*/
	51	#define CONFIG_SYS_IMMR 0xE0000000
	52
	53	/*
	54	* Bus Arbitration Configuration Register (ACR)
	55	*/
	56	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
	57	#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
	58	#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
	59	#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
	60
	61	/*
	62	* DDR Setup
	63	*/
	64	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	65	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	66	#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
	67
	68	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	69	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
	70	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	71
	72	#define CFG_83XX_DDR_USES_CS0
	73
	74	/*
	75	* Manually set up DDR parameters
	76	*/
	77	#define CONFIG_DDR_II
	78	#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
	79
	80	/*
	81	* The reserved memory
	82	*/
	83	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	84	#define CONFIG_SYS_FLASH_BASE 0xF0000000
	85
	86	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	87	#define CONFIG_SYS_RAMBOOT
	88	#endif
	89
	90	/* Reserve 768 kB for Mon */
	91	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	92
	93	/*
	94	* Initial RAM Base Address Setup
	95	*/
	96	#define CONFIG_SYS_INIT_RAM_LOCK
	97	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	98	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
	99	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	100	GENERATED_GBL_DATA_SIZE)
101
102	/*
103	* Init Local Bus Memory Controller:
104	*
105	* Bank Bus Machine PortSz Size Device
106	* ---- --- ------- ------ ----- ------
107	* 0 Local GPCM 16 bit 256MB FLASH
108	* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
109	*
110	*/
111	/*
112	* FLASH on the Local Bus
113	*/
114	#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
115
116	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
117	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
118
119	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
120	BR_PS_16 \| /* 16 bit port size */ \
121	BR_MS_GPCM \| /* MSEL = GPCM */ \
122	BR_V)
123
124	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \| \
125	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| \
126	OR_GPCM_SCY_5 \| \
127	OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
128
129	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
130	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
131	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
132
133	/*
134	* PRIO1/PIGGY on the local bus CS1
135	*/
136	/* Window base at flash base */
137	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
138	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_128MB)
139
140	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE \| \
141	BR_PS_8 \| /* 8 bit port size */ \
142	BR_MS_GPCM \| /* MSEL = GPCM */ \
143	BR_V)
144	#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) \| \
145	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| \
146	OR_GPCM_SCY_2 \| \
147	OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
148
149	/*
150	* Serial Port
151	*/
152	#define CONFIG_SYS_NS16550_SERIAL
153	#define CONFIG_SYS_NS16550_REG_SIZE 1
154	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
155
156	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
157	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
158
159	/*
160	* QE UEC ethernet configuration
161	*/
162	#define CONFIG_UEC_ETH
163	#define CONFIG_ETHPRIME "UEC0"
164
165	#define CONFIG_UEC_ETH1 /* GETH1 */
166	#define UEC_VERBOSE_DEBUG 1
167
168	#ifdef CONFIG_UEC_ETH1
169	#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
170	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
171	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
172	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
173	#define CONFIG_SYS_UEC1_PHY_ADDR 0
174	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
175	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
176	#endif
177
178	/*
179	* Environment
180	*/
181
182	#ifndef CONFIG_SYS_RAMBOOT
183	#ifndef CONFIG_ENV_ADDR
184	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
185	CONFIG_SYS_MONITOR_LEN)
186	#endif
187	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
188	#ifndef CONFIG_ENV_OFFSET
189	#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
190	#endif
191
192	/* Address and size of Redundant Environment Sector */
193	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
194	CONFIG_ENV_SECT_SIZE)
195	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
196
197	#else /* CFG_SYS_RAMBOOT */
198	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
199	#define CONFIG_ENV_SIZE 0x2000
200	#endif /* CFG_SYS_RAMBOOT */
201
202	/* I2C */
203	#define CONFIG_SYS_I2C
204	#define CONFIG_SYS_NUM_I2C_BUSES 4
205	#define CONFIG_SYS_I2C_MAX_HOPS 1
206	#define CONFIG_SYS_I2C_FSL
207	#define CONFIG_SYS_FSL_I2C_SPEED 200000
208	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
209	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
210	#define CONFIG_SYS_I2C_OFFSET 0x3000
211	#define CONFIG_SYS_FSL_I2C2_SPEED 200000
212	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
213	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
214	#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
215	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
216	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
217	{1, {I2C_NULL_HOP} } }
218
219	#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
220
221	#if defined(CONFIG_CMD_NAND)
222	#define CONFIG_NAND_KMETER1
223	#define CONFIG_SYS_MAX_NAND_DEVICE 1
224	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
225	#endif
226
227	/*
228	* For booting Linux, the board info and command line data
229	* have to be in the first 8 MB of memory, since this is
230	* the maximum mapped by the Linux kernel during initialization.
231	*/
232	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
233
234	/*
235	* Core HID Setup
236	*/
237	#define CONFIG_SYS_HID0_INIT 0x000000000
238	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
239	HID0_ENABLE_INSTRUCTION_CACHE)
240	#define CONFIG_SYS_HID2 HID2_HBE
241
242	/*
243	* MMU Setup
244	*/
245
fb1b099f MS	246	/* DDR: cache cacheable */
	247	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \
	248	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	249	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| \
	250	BATU_VS \| BATU_VP)
	251	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	252	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	253
	254	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
	255	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \
	256	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	257	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_4M \| BATU_VS \
	258	\| BATU_VP)
	259	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	260	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	261
	262	/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
	263	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \
	264	BATL_MEMCOHERENCE)
	265	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE \| BATU_BL_128M \| \
	266	BATU_VS \| BATU_VP)
	267	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \
	268	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	269	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	270
	271	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	272	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
	273	BATL_MEMCOHERENCE)
	274	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \| BATU_BL_256M \| \
	275	BATU_VS \| BATU_VP)
	276	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
	277	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	278	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	279
	280	/* Stack in dcache: cacheable, no memory coherence */
	281	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
	282	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
	283	BATU_VS \| BATU_VP)
	284	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	285	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	286
	287	/*
	288	* Internal Definitions
	289	*/
	290	#define BOOTFLASH_START 0xF0000000
	291
	292	#define CONFIG_KM_CONSOLE_TTY "ttyS0"
	293
	294	/*
	295	* Environment Configuration
	296	*/
	297	#define CONFIG_ENV_OVERWRITE
	298	#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
	299	#define CONFIG_KM_DEF_ENV "km-common=empty\0"
	300	#endif
	301
	302	#ifndef CONFIG_KM_DEF_ARCH
	303	#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
	304	#endif
	305
	306	#define CONFIG_EXTRA_ENV_SETTINGS \
	307	CONFIG_KM_DEF_ENV \
	308	CONFIG_KM_DEF_ARCH \
	309	"newenv=" \
310	"prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
311	"era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
312	"unlock=yes\0" \
313	""
314
315	#if defined(CONFIG_UEC_ETH)
316	#define CONFIG_HAS_ETH0
317	#endif
0e890d4c MS	318
	319	/*
	320	* System IO Config
	321	*/
	322	#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
	323
0e890d4c MS	324	#define CONFIG_SYS_DDRCDR (\
	325	DDRCDR_EN \| \
	326	DDRCDR_PZ_MAXZ \| \
	327	DDRCDR_NZ_MAXZ \| \
	328	DDRCDR_M_ODR)
	329
	330	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
	331	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \| \
	332	SDRAM_CFG_32_BE \| \
	333	SDRAM_CFG_SREN \| \
	334	SDRAM_CFG_HSE)
	335
	336	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
	337	#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	338	#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \| \
	339	(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
	340
	341	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \| CSCONFIG_AP \| \
	342	CSCONFIG_ODT_WR_CFG \| \
	343	CSCONFIG_ROW_BIT_13 \| \
	344	CSCONFIG_COL_BIT_10)
	345
	346	#define CONFIG_SYS_DDR_MODE 0x47860242
	347	#define CONFIG_SYS_DDR_MODE2 0x8080c000
	348
	349	#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) \| \
	350	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \| \
	351	(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \| \
	352	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \| \
	353	(0 << TIMING_CFG0_WWT_SHIFT) \| \
	354	(0 << TIMING_CFG0_RRT_SHIFT) \| \
	355	(0 << TIMING_CFG0_WRT_SHIFT) \| \
	356	(0 << TIMING_CFG0_RWT_SHIFT))
	357
	358	#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) \| \
	359	(2 << TIMING_CFG1_WRTORD_SHIFT) \| \
	360	(2 << TIMING_CFG1_ACTTOACT_SHIFT) \| \
	361	(3 << TIMING_CFG1_WRREC_SHIFT) \| \
	362	(7 << TIMING_CFG1_REFREC_SHIFT) \| \
	363	(3 << TIMING_CFG1_ACTTORW_SHIFT) \| \
	364	(7 << TIMING_CFG1_ACTTOPRE_SHIFT) \| \
	365	(3 << TIMING_CFG1_PRETOACT_SHIFT))
	366
	367	#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) \| \
	368	(3 << TIMING_CFG2_CKE_PLS_SHIFT) \| \
	369	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \| \
	370	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \| \
	371	(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \| \
	372	(0 << TIMING_CFG2_ADD_LAT_SHIFT) \| \
	373	(5 << TIMING_CFG2_CPO_SHIFT))
	374
	375	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	376
	377	#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
	378	#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
	379
	380	/* EEprom support */
	381	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	382
	383	/*
	384	* Local Bus Configuration & Clock Setup
	385	*/
	386	#define CONFIG_SYS_LCRR_DBYP 0x80000000
	387	#define CONFIG_SYS_LCRR_EADC 0x00010000
388	#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
389
390	#define CONFIG_SYS_LBC_LBCR 0x00000000
391
392	/*
393	* MMU Setup
394	*/
395	#define CONFIG_SYS_IBAT7L (0)
396	#define CONFIG_SYS_IBAT7U (0)
397	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
398	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
dc6033ec	399
dc6033ec HS	400	#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
	401	#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
	402	#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
	403	#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
	404
dc6033ec HS	405	/*
dc6033ec HS	406	* Init Local Bus Memory Controller:
c1e121e4 CD	407	* Device on board
	408	* Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
	409	* -----------------------------------------------------------------------------
	410	* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
	411	* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
dc6033ec	412	*
c1e121e4 CD	413	* Device on board (continued)
	414	* Bank Bus Machine PortSz Size KMTEPR2
	415	* -----------------------------------------------------------------------------
	416	* 2 Local GPCM 8 bit 256MB NVRAM
	417	* 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
dc6033ec HS	418	*/
	419
	420	/*
5f2a44d5	421	* Configuration for C2 on the local bus
dc6033ec HS	422	*/
	423	/* Window base at flash base */
	424	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
	425	/* Window size: 256 MB */
	426	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	427
	428	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE \| \
	429	BR_PS_8 \| \
	430	BR_MS_GPCM \| \
	431	BR_V)
	432
	433	#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) \| \
	434	OR_GPCM_CSNT \| \
	435	OR_GPCM_ACS_DIV4 \| \
	436	OR_GPCM_SCY_2 \| \
7d6a0982 JH	437	OR_GPCM_TRLX_SET \| \
7d6a0982 JH	438	OR_GPCM_EHTR_CLEAR \| \
dc6033ec	439	OR_GPCM_EAD)
c1e121e4	440
dc6033ec	441	/*
5f2a44d5	442	* Configuration for C3 on the local bus
dc6033ec HS	443	*/
	444	/* Access window base at PINC3 base */
	445	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
	446	/* Window size: 256 MB */
	447	#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	448
	449	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE \| \
	450	BR_PS_8 \| \
	451	BR_MS_GPCM \| \
	452	BR_V)
	453
	454	#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) \| \
	455	OR_GPCM_CSNT \| \
7d6a0982 JH	456	OR_GPCM_ACS_DIV2 \| \
	457	OR_GPCM_SCY_2 \| \
	458	OR_GPCM_TRLX_SET \| \
	459	OR_GPCM_EHTR_CLEAR)
dc6033ec HS	460
	461	#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS \| \
	462	0x0000c000 \| \
	463	MxMR_WLFx_2X)
4714f8e4	464
dc6033ec HS	465	/*
	466	* MMU Setup
	467	*/
5f2a44d5	468	/* APP1: icache cacheable, but dcache-inhibit and guarded */
dc6033ec	469	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE \| \
72cd4087	470	BATL_PP_RW \| \
dc6033ec HS	471	BATL_MEMCOHERENCE)
	472	/* 512M should also include APP2... */
	473	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE \| \
	474	BATU_BL_256M \| \
	475	BATU_VS \| \
	476	BATU_VP)
	477	#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE \| \
72cd4087	478	BATL_PP_RW \| \
dc6033ec HS	479	BATL_CACHEINHIBIT \| \
	480	BATL_GUARDEDSTORAGE)
	481	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	482
5f2a44d5	483	/* APP2: icache cacheable, but dcache-inhibit and guarded */
dc6033ec	484	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE \| \
72cd4087	485	BATL_PP_RW \| \
dc6033ec HS	486	BATL_MEMCOHERENCE)
	487	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE \| \
	488	BATU_BL_256M \| \
	489	BATU_VS \| \
	490	BATU_VP)
	491	#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE \| \
72cd4087	492	BATL_PP_RW \| \
dc6033ec HS	493	BATL_CACHEINHIBIT \| \
	494	BATL_GUARDEDSTORAGE)
	495	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	496
	497	#define CONFIG_SYS_IBAT7L (0)
	498	#define CONFIG_SYS_IBAT7U (0)
	499	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	500	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
dc6033ec HS	501
dc6033ec HS	502	#endif /* __CONFIG_H */