[J-u-boot.git] / drivers / mmc / dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <[email protected]>
 * Rajeshawari Shinde <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bouncebuf.h>
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <dwmmc.h>
#include <asm-generic/errno.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
			       struct mmc_data *data,
			       struct dwmci_idmac *cur_idmac,
			       void *bounce_buffer)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end;


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				    (u32)bounce_buffer + (i * PAGE_SIZE));

		if (blk_cnt <= 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	struct dwmci_host *host = mmc->priv;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
	int flags = 0, i;
	unsigned int timeout = 100000;
	u32 retry = 10000;
	u32 mask, ctrl;
	ulong start = get_timer(0);
	struct bounce_buffer bbstate;

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			printf("Timeout on data busy\n");
			return TIMEOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data) {
		if (data->flags == MMC_DATA_READ) {
			bounce_buffer_start(&bbstate, (void*)data->dest,
					    data->blocksize *
					    data->blocks, GEN_BB_WRITE);
		} else {
			bounce_buffer_start(&bbstate, (void*)data->src,
					    data->blocksize *
					    data->blocks, GEN_BB_READ);
		}
		dwmci_prepare_data(host, data, cur_idmac,
				   bbstate.bounce_buffer);
	}

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry)
		return TIMEOUT;

	if (mask & DWMCI_INTMSK_RTO) {
		debug("Response Timeout..\n");
		return TIMEOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("Response Error..\n");
		return -1;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		do {
			mask = dwmci_readl(host, DWMCI_RINTSTS);
			if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
				debug("DATA ERROR!\n");
				return -1;
			}
		} while (!(mask & DWMCI_INTMSK_DTO));

		dwmci_writel(host, DWMCI_RINTSTS, mask);

		ctrl = dwmci_readl(host, DWMCI_CTRL);
		ctrl &= ~(DWMCI_DMA_EN);
		dwmci_writel(host, DWMCI_CTRL, ctrl);

		bounce_buffer_stop(&bbstate);
	}

	udelay(100);

	return 0;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->get_mmc_clk didn't define,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set from user.
	 */
	if (host->get_mmc_clk)
		sclk = host->get_mmc_clk(host);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		printf("Didn't get source clock value..\n");
		return -EINVAL;
	}

	div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			printf("TIMEOUT error!!\n");
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			printf("TIMEOUT error!!\n");
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

static void dwmci_set_ios(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;
	u32 ctype;

	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	if (host->clksel)
		host->clksel(host);
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;

	if (host->board_init)
		host->board_init(host);

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
		return -1;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->cfg->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	if (host->fifoth_val) {
		dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
	}

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

static const struct mmc_ops dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
	.init		= dwmci_init,
};

int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	host->cfg.name = host->name;
	host->cfg.ops = &dwmci_ops;
	host->cfg.f_min = min_clk;
	host->cfg.f_max = max_clk;

	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	host->cfg.host_caps = host->caps;

	if (host->buswidth == 8) {
		host->cfg.host_caps |= MMC_MODE_8BIT;
		host->cfg.host_caps &= ~MMC_MODE_4BIT;
	} else {
		host->cfg.host_caps |= MMC_MODE_4BIT;
		host->cfg.host_caps &= ~MMC_MODE_8BIT;
	}
	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;

	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}
Commit	Line	Data
757bff49 JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <[email protected]>
	4	* Rajeshawari Shinde <[email protected]>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
757bff49 JC	7	*/
757bff49 JC	8
2a7a210e	9	#include <bouncebuf.h>
757bff49 JC	10	#include <common.h>
	11	#include <malloc.h>
	12	#include <mmc.h>
	13	#include <dwmmc.h>
757bff49 JC	14	#include <asm-generic/errno.h>
	15
	16	#define PAGE_SIZE 4096
	17
	18	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	19	{
	20	unsigned long timeout = 1000;
	21	u32 ctrl;
	22
	23	dwmci_writel(host, DWMCI_CTRL, value);
	24
	25	while (timeout--) {
	26	ctrl = dwmci_readl(host, DWMCI_CTRL);
	27	if (!(ctrl & DWMCI_RESET_ALL))
	28	return 1;
	29	}
	30	return 0;
	31	}
	32
	33	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	34	u32 desc0, u32 desc1, u32 desc2)
	35	{
	36	struct dwmci_idmac *desc = idmac;
	37
	38	desc->flags = desc0;
	39	desc->cnt = desc1;
	40	desc->addr = desc2;
	41	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
	42	}
	43
	44	static void dwmci_prepare_data(struct dwmci_host *host,
2a7a210e AB	45	struct mmc_data *data,
	46	struct dwmci_idmac *cur_idmac,
	47	void *bounce_buffer)
757bff49 JC	48	{
	49	unsigned long ctrl;
	50	unsigned int i = 0, flags, cnt, blk_cnt;
2a7a210e	51	ulong data_start, data_end;
757bff49 JC	52
	53
	54	blk_cnt = data->blocks;
	55
	56	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
	57
	58	data_start = (ulong)cur_idmac;
	59	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
	60
757bff49 JC	61	do {
	62	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
	63	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
	64	if (blk_cnt <= 8) {
	65	flags \|= DWMCI_IDMAC_LD;
	66	cnt = data->blocksize * blk_cnt;
	67	} else
	68	cnt = data->blocksize * 8;
	69
	70	dwmci_set_idma_desc(cur_idmac, flags, cnt,
2a7a210e	71	(u32)bounce_buffer + (i * PAGE_SIZE));
757bff49	72
21bd5761	73	if (blk_cnt <= 8)
757bff49 JC	74	break;
	75	blk_cnt -= 8;
	76	cur_idmac++;
	77	i++;
	78	} while(1);
	79
	80	data_end = (ulong)cur_idmac;
	81	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
	82
	83	ctrl = dwmci_readl(host, DWMCI_CTRL);
	84	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
	85	dwmci_writel(host, DWMCI_CTRL, ctrl);
	86
	87	ctrl = dwmci_readl(host, DWMCI_BMOD);
	88	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
	89	dwmci_writel(host, DWMCI_BMOD, ctrl);
	90
	91	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	92	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
	93	}
	94
	95	static int dwmci_set_transfer_mode(struct dwmci_host *host,
	96	struct mmc_data *data)
	97	{
	98	unsigned long mode;
	99
	100	mode = DWMCI_CMD_DATA_EXP;
	101	if (data->flags & MMC_DATA_WRITE)
	102	mode \|= DWMCI_CMD_RW;
	103
	104	return mode;
	105	}
	106
	107	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	108	struct mmc_data *data)
	109	{
93bfd616	110	struct dwmci_host *host = mmc->priv;
2136d226	111	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
21bd5761	112	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
757bff49 JC	113	int flags = 0, i;
	114	unsigned int timeout = 100000;
	115	u32 retry = 10000;
	116	u32 mask, ctrl;
9c50e35f	117	ulong start = get_timer(0);
2a7a210e	118	struct bounce_buffer bbstate;
757bff49 JC	119
757bff49 JC	120	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	121	if (get_timer(start) > timeout) {
757bff49 JC	122	printf("Timeout on data busy\n");
	123	return TIMEOUT;
	124	}
757bff49 JC	125	}
	126
	127	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	128
2a7a210e AB	129	if (data) {
	130	if (data->flags == MMC_DATA_READ) {
	131	bounce_buffer_start(&bbstate, (void*)data->dest,
	132	data->blocksize *
	133	data->blocks, GEN_BB_WRITE);
	134	} else {
	135	bounce_buffer_start(&bbstate, (void*)data->src,
	136	data->blocksize *
	137	data->blocks, GEN_BB_READ);
	138	}
	139	dwmci_prepare_data(host, data, cur_idmac,
	140	bbstate.bounce_buffer);
	141	}
757bff49	142
757bff49 JC	143	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	144
	145	if (data)
	146	flags = dwmci_set_transfer_mode(host, data);
	147
	148	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	149	return -1;
	150
	151	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	152	flags \|= DWMCI_CMD_ABORT_STOP;
	153	else
	154	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	155
	156	if (cmd->resp_type & MMC_RSP_PRESENT) {
	157	flags \|= DWMCI_CMD_RESP_EXP;
	158	if (cmd->resp_type & MMC_RSP_136)
	159	flags \|= DWMCI_CMD_RESP_LENGTH;
	160	}
	161
	162	if (cmd->resp_type & MMC_RSP_CRC)
	163	flags \|= DWMCI_CMD_CHECK_CRC;
	164
	165	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	166
	167	debug("Sending CMD%d\n",cmd->cmdidx);
	168
	169	dwmci_writel(host, DWMCI_CMD, flags);
	170
	171	for (i = 0; i < retry; i++) {
	172	mask = dwmci_readl(host, DWMCI_RINTSTS);
	173	if (mask & DWMCI_INTMSK_CDONE) {
	174	if (!data)
	175	dwmci_writel(host, DWMCI_RINTSTS, mask);
	176	break;
	177	}
	178	}
	179
	180	if (i == retry)
	181	return TIMEOUT;
	182
	183	if (mask & DWMCI_INTMSK_RTO) {
	184	debug("Response Timeout..\n");
	185	return TIMEOUT;
	186	} else if (mask & DWMCI_INTMSK_RE) {
	187	debug("Response Error..\n");
	188	return -1;
	189	}
	190
	191
	192	if (cmd->resp_type & MMC_RSP_PRESENT) {
	193	if (cmd->resp_type & MMC_RSP_136) {
	194	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	195	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	196	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	197	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	198	} else {
	199	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	200	}
	201	}
	202
	203	if (data) {
	204	do {
	205	mask = dwmci_readl(host, DWMCI_RINTSTS);
	206	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
207	debug("DATA ERROR!\n");
208	return -1;
209	}
210	} while (!(mask & DWMCI_INTMSK_DTO));
211
212	dwmci_writel(host, DWMCI_RINTSTS, mask);
213
214	ctrl = dwmci_readl(host, DWMCI_CTRL);
215	ctrl &= ~(DWMCI_DMA_EN);
216	dwmci_writel(host, DWMCI_CTRL, ctrl);
2a7a210e AB	217
2a7a210e AB	218	bounce_buffer_stop(&bbstate);
757bff49 JC	219	}
	220
	221	udelay(100);
	222
	223	return 0;
	224	}
	225
	226	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
	227	{
	228	u32 div, status;
	229	int timeout = 10000;
	230	unsigned long sclk;
	231
9c50e35f	232	if ((freq == host->clock) \|\| (freq == 0))
757bff49	233	return 0;
757bff49	234	/*
b44fe83a	235	* If host->get_mmc_clk didn't define,
757bff49 JC	236	* then assume that host->bus_hz is source clock value.
	237	* host->bus_hz should be set from user.
	238	*/
b44fe83a	239	if (host->get_mmc_clk)
d3e016cc	240	sclk = host->get_mmc_clk(host);
757bff49 JC	241	else if (host->bus_hz)
	242	sclk = host->bus_hz;
	243	else {
	244	printf("Didn't get source clock value..\n");
	245	return -EINVAL;
	246	}
	247
	248	div = DIV_ROUND_UP(sclk, 2 * freq);
	249
	250	dwmci_writel(host, DWMCI_CLKENA, 0);
	251	dwmci_writel(host, DWMCI_CLKSRC, 0);
	252
	253	dwmci_writel(host, DWMCI_CLKDIV, div);
	254	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	255	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	256
	257	do {
	258	status = dwmci_readl(host, DWMCI_CMD);
	259	if (timeout-- < 0) {
	260	printf("TIMEOUT error!!\n");
	261	return -ETIMEDOUT;
	262	}
	263	} while (status & DWMCI_CMD_START);
	264
	265	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	266	DWMCI_CLKEN_LOW_PWR);
	267
	268	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	269	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	270
	271	timeout = 10000;
	272	do {
	273	status = dwmci_readl(host, DWMCI_CMD);
	274	if (timeout-- < 0) {
	275	printf("TIMEOUT error!!\n");
	276	return -ETIMEDOUT;
	277	}
	278	} while (status & DWMCI_CMD_START);
	279
	280	host->clock = freq;
	281
	282	return 0;
	283	}
	284
	285	static void dwmci_set_ios(struct mmc *mmc)
	286	{
93bfd616	287	struct dwmci_host *host = mmc->priv;
757bff49 JC	288	u32 ctype;
	289
	290	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
	291
	292	dwmci_setup_bus(host, mmc->clock);
	293	switch (mmc->bus_width) {
	294	case 8:
	295	ctype = DWMCI_CTYPE_8BIT;
	296	break;
	297	case 4:
	298	ctype = DWMCI_CTYPE_4BIT;
	299	break;
	300	default:
	301	ctype = DWMCI_CTYPE_1BIT;
	302	break;
	303	}
	304
	305	dwmci_writel(host, DWMCI_CTYPE, ctype);
	306
	307	if (host->clksel)
	308	host->clksel(host);
	309	}
	310
	311	static int dwmci_init(struct mmc *mmc)
	312	{
93bfd616	313	struct dwmci_host *host = mmc->priv;
757bff49	314
18ab6755 JC	315	if (host->board_init)
18ab6755 JC	316	host->board_init(host);
6f0b7caa	317
757bff49 JC	318	dwmci_writel(host, DWMCI_PWREN, 1);
	319
	320	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
	321	debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
	322	return -1;
	323	}
	324
9c50e35f	325	/* Enumerate at 400KHz */
93bfd616	326	dwmci_setup_bus(host, mmc->cfg->f_min);
9c50e35f	327
757bff49 JC	328	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	329	dwmci_writel(host, DWMCI_INTMASK, 0);
	330
	331	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	332
	333	dwmci_writel(host, DWMCI_IDINTEN, 0);
	334	dwmci_writel(host, DWMCI_BMOD, 1);
	335
9108b315 AB	336	if (host->fifoth_val) {
9108b315 AB	337	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
9c50e35f	338	}
757bff49 JC	339
	340	dwmci_writel(host, DWMCI_CLKENA, 0);
	341	dwmci_writel(host, DWMCI_CLKSRC, 0);
	342
	343	return 0;
	344	}
	345
ab769f22 PA	346	static const struct mmc_ops dwmci_ops = {
	347	.send_cmd = dwmci_send_cmd,
	348	.set_ios = dwmci_set_ios,
	349	.init = dwmci_init,
	350	};
	351
757bff49 JC	352	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
757bff49 JC	353	{
93bfd616 PA	354	host->cfg.name = host->name;
	355	host->cfg.ops = &dwmci_ops;
	356	host->cfg.f_min = min_clk;
	357	host->cfg.f_max = max_clk;
757bff49	358
93bfd616	359	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
757bff49	360
93bfd616	361	host->cfg.host_caps = host->caps;
757bff49 JC	362
757bff49 JC	363	if (host->buswidth == 8) {
93bfd616 PA	364	host->cfg.host_caps \|= MMC_MODE_8BIT;
93bfd616 PA	365	host->cfg.host_caps &= ~MMC_MODE_4BIT;
757bff49	366	} else {
93bfd616 PA	367	host->cfg.host_caps \|= MMC_MODE_4BIT;
93bfd616 PA	368	host->cfg.host_caps &= ~MMC_MODE_8BIT;
757bff49	369	}
93bfd616 PA	370	host->cfg.host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_HC;
	371
	372	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
757bff49	373
93bfd616 PA	374	host->mmc = mmc_create(&host->cfg, host);
	375	if (host->mmc == NULL)
	376	return -1;
757bff49	377
93bfd616	378	return 0;
757bff49	379	}