[J-u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M52277EVB	/* M52277EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_SPI_CS	2
#endif
#define CONFIG_ENV_OVERWRITE		1

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

#define LDS_BOARD_TEXT \
        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
	arch/m68k/lib/built-in.o            (.text*)

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew ([email protected])
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
1552af70 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M52277EVB_H
	15	#define _M52277EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
1552af70 TL	21	#define CONFIG_M52277EVB /* M52277EVB board */
1552af70 TL	22
1552af70	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
1552af70 TL	25
	26	#undef CONFIG_WATCHDOG
	27
	28	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	29
	30	/*
	31	* BOOTP options
	32	*/
	33	#define CONFIG_BOOTP_BOOTFILESIZE
	34	#define CONFIG_BOOTP_BOOTPATH
	35	#define CONFIG_BOOTP_GATEWAY
	36	#define CONFIG_BOOTP_HOSTNAME
	37
a21d0c2c TL	38	#define CONFIG_HOSTNAME M52277EVB
	39	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	40	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	41	#ifdef CONFIG_SYS_STMICRO_BOOT
	42	/* ST Micro serial flash */
1552af70	43	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	44	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	45	"loadaddr=0x40010000\0" \
	46	"uboot=u-boot.bin\0" \
	47	"load=loadb ${loadaddr} ${baudrate};" \
5368c55d	48	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	49	"upd=run load; run prog\0" \
a21d0c2c TL	50	"prog=sf probe 0:2 10000 1;" \
	51	"sf erase 0 30000;" \
	52	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	53	"save\0" \
1552af70 TL	54	""
a21d0c2c TL	55	#endif
	56	#ifdef CONFIG_SYS_SPANSION_BOOT
	57	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	58	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	59	"loadaddr=0x40010000\0" \
	60	"uboot=u-boot.bin\0" \
	61	"load=loadb ${loadaddr} ${baudrate}\0" \
	62	"upd=run load; run prog\0" \
5368c55d MV	63	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	64	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	65	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	66	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	67	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
a21d0c2c TL	68	" ${filesize}; save\0" \
	69	"updsbf=run loadsbf; run progsbf\0" \
	70	"loadsbf=loadb ${loadaddr} ${baudrate};" \
5368c55d	71	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
a21d0c2c TL	72	"progsbf=sf probe 0:2 10000 1;" \
	73	"sf erase 0 30000;" \
	74	"sf write ${loadaddr} 0 30000;" \
	75	""
	76	#endif
1552af70 TL	77
	78	/* LCD */
	79	#ifdef CONFIG_CMD_BMP
1552af70 TL	80	#define CONFIG_SPLASH_SCREEN
	81	#define CONFIG_LCD_LOGO
	82	#define CONFIG_SHARP_LQ035Q7DH06
	83	#endif
	84
	85	/* USB */
	86	#ifdef CONFIG_CMD_USB
a21d0c2c	87	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	88	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	89	#endif
	90
	91	/* Realtime clock */
	92	#define CONFIG_MCFRTC
	93	#undef RTC_DEBUG
6d0f6bcf	94	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	95
	96	/* Timer */
	97	#define CONFIG_MCFTMR
	98	#undef CONFIG_MCFPIT
	99
	100	/* I2c */
00f792e0 HS	101	#define CONFIG_SYS_I2C
	102	#define CONFIG_SYS_I2C_FSL
	103	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	104	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	105	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
a21d0c2c TL	106	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	107
	108	/* DSPI and Serial Flash */
ee0a8462	109	#define CONFIG_CF_SPI
a21d0c2c TL	110	#define CONFIG_CF_DSPI
a21d0c2c TL	111	#define CONFIG_HARD_SPI
a21d0c2c TL	112	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	113	#ifdef CONFIG_CMD_SPI
	114	# define CONFIG_SYS_DSPI_CS2
a21d0c2c	115
ee0a8462 TL	116	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	117	DSPI_CTAR_PCSSCK_1CLK \| \
	118	DSPI_CTAR_PASC(0) \| \
	119	DSPI_CTAR_PDT(0) \| \
	120	DSPI_CTAR_CSSCK(0) \| \
	121	DSPI_CTAR_ASC(0) \| \
	122	DSPI_CTAR_DT(1))
a21d0c2c	123	#endif
1552af70 TL	124
	125	/* Input, PCI, Flexbus, and VCO */
	126	#define CONFIG_EXTRA_CLOCK
	127
6d0f6bcf	128	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	129
a21d0c2c	130	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	131
6d0f6bcf	132	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1552af70 TL	133
1552af70 TL	134	#if defined(CONFIG_CMD_KGDB)
a21d0c2c	135	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1552af70	136	#else
a21d0c2c	137	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1552af70	138	#endif
a21d0c2c TL	139	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	140	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	141	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1552af70	142
a21d0c2c	143	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	144
6d0f6bcf	145	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	146
	147	/*
	148	* Low Level Configuration Settings
	149	* (address mappings, register initial values, etc.)
	150	* You should know what you are doing if you make changes here.
	151	*/
	152
a21d0c2c	153	/*
1552af70 TL	154	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	155	*/
6d0f6bcf	156	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	157	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
a21d0c2c	158	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	159	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
a21d0c2c	160	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
553f0982	161	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
1552af70	162
a21d0c2c	163	/*
1552af70 TL	164	* Start addresses for the final memory configuration
1552af70 TL	165	* (Set up by the startup code)
6d0f6bcf	166	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	169	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	170	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	171	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	172	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	173	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	174	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	175	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	176
	177	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	178	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	179
a21d0c2c	180	#ifdef CONFIG_CF_SBF
14d0a02a	181	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
a21d0c2c TL	182	#else
	183	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	184	#endif
6d0f6bcf JCPV	185	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	186	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	187	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	188
1552af70 TL	189	/* Initial Memory map for Linux */
6d0f6bcf	190	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	191	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	192
a21d0c2c TL	193	/*
a21d0c2c TL	194	* Configuration for environment
27f7ae70 JJ	195	* Environment is not embedded in u-boot. First time runing may have env
27f7ae70 JJ	196	* crc error warning if there is no correct environment on the flash.
1552af70	197	*/
a21d0c2c	198	#ifdef CONFIG_CF_SBF
a21d0c2c	199	# define CONFIG_ENV_SPI_CS 2
a21d0c2c TL	200	#endif
a21d0c2c TL	201	#define CONFIG_ENV_OVERWRITE 1
1552af70 TL	202
	203	/*-----------------------------------------------------------------------
	204	* FLASH organization
	205	*/
a21d0c2c	206	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462	207	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
27f7ae70	208	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
a21d0c2c TL	209	# define CONFIG_ENV_OFFSET 0x30000
	210	# define CONFIG_ENV_SIZE 0x1000
	211	# define CONFIG_ENV_SECT_SIZE 0x10000
	212	#endif
	213	#ifdef CONFIG_SYS_SPANSION_BOOT
	214	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	215	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
27f7ae70	216	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
a21d0c2c TL	217	# define CONFIG_ENV_SIZE 0x1000
	218	# define CONFIG_ENV_SECT_SIZE 0x8000
	219	#endif
1552af70	220
6d0f6bcf JCPV	221	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	222	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	223	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	224	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	225	# define CONFIG_FLASH_SPANSION_S29WS_N 1
6d0f6bcf JCPV	226	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	227	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	228	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	229	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	230	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	231	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	232	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	233	#endif
1552af70 TL	234
5296cb1d	235	#define LDS_BOARD_TEXT \
	236	arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
	237	arch/m68k/lib/built-in.o (.text*)
	238
1552af70 TL	239	/*
	240	* This is setting for JFFS2 support in u-boot.
	241	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	242	*/
	243	#ifdef CONFIG_CMD_JFFS2
	244	# define CONFIG_JFFS2_DEV "nor0"
	245	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	246	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	247	#endif
	248
	249	/*-----------------------------------------------------------------------
	250	* Cache Configuration
	251	*/
a21d0c2c	252	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70	253
dd9f054e	254	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	255	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	256	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	257	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	258	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	259	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	260	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	261	CF_ACR_EN \| CF_ACR_SM_ALL)
	262	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	263	CF_CACR_DISD \| CF_CACR_INVI \| \
	264	CF_CACR_CEIB \| CF_CACR_DCM \| \
	265	CF_CACR_EUSP)
	266
1552af70 TL	267	/*-----------------------------------------------------------------------
	268	* Memory bank definitions
	269	*/
	270	/*
	271	* CS0 - NOR Flash
	272	* CS1 - Available
	273	* CS2 - Available
	274	* CS3 - Available
	275	* CS4 - Available
	276	* CS5 - Available
	277	*/
	278
a21d0c2c TL	279	#ifdef CONFIG_CF_SBF
	280	#define CONFIG_SYS_CS0_BASE 0x04000000
	281	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	282	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	283	#else
6d0f6bcf JCPV	284	#define CONFIG_SYS_CS0_BASE 0x00000000
	285	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	286	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	287	#endif
1552af70 TL	288
1552af70 TL	289	#endif /* _M52277EVB_H */