]>
Commit | Line | Data |
---|---|---|
2da0fc0d DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, [email protected] | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
2da0fc0d DE |
6 | */ |
7 | ||
8 | #ifndef __GDSYS_FPGA_H | |
9 | #define __GDSYS_FPGA_H | |
10 | ||
255ef4d9 DE |
11 | int init_func_fpga(void); |
12 | ||
2da0fc0d DE |
13 | enum { |
14 | FPGA_STATE_DONE_FAILED = 1 << 0, | |
15 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, | |
255ef4d9 | 16 | FPGA_STATE_PLATFORM = 1 << 2, |
2da0fc0d DE |
17 | }; |
18 | ||
19 | int get_fpga_state(unsigned dev); | |
20 | void print_fpga_state(unsigned dev); | |
21 | ||
aba27acf DE |
22 | int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); |
23 | int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); | |
24 | ||
25 | extern struct ihs_fpga *fpga_ptr[]; | |
26 | ||
27 | #define FPGA_SET_REG(ix, fld, val) \ | |
28 | fpga_set_reg((ix), \ | |
29 | &fpga_ptr[ix]->fld, \ | |
30 | offsetof(struct ihs_fpga, fld), \ | |
31 | val) | |
32 | ||
33 | #define FPGA_GET_REG(ix, fld, val) \ | |
34 | fpga_get_reg((ix), \ | |
35 | &fpga_ptr[ix]->fld, \ | |
36 | offsetof(struct ihs_fpga, fld), \ | |
37 | val) | |
38 | ||
0e60aa85 | 39 | struct ihs_gpio { |
2da0fc0d DE |
40 | u16 read; |
41 | u16 clear; | |
42 | u16 set; | |
0e60aa85 | 43 | }; |
2da0fc0d | 44 | |
0e60aa85 | 45 | struct ihs_i2c { |
b46226bd DE |
46 | u16 interrupt_status; |
47 | u16 interrupt_enable; | |
2da0fc0d | 48 | u16 write_mailbox_ext; |
b46226bd | 49 | u16 write_mailbox; |
2da0fc0d | 50 | u16 read_mailbox_ext; |
b46226bd | 51 | u16 read_mailbox; |
0e60aa85 | 52 | }; |
2da0fc0d | 53 | |
0e60aa85 | 54 | struct ihs_osd { |
2da0fc0d DE |
55 | u16 version; |
56 | u16 features; | |
57 | u16 control; | |
58 | u16 xy_size; | |
52158e36 DE |
59 | u16 xy_scale; |
60 | u16 x_pos; | |
61 | u16 y_pos; | |
0e60aa85 | 62 | }; |
2da0fc0d | 63 | |
50dcf89d DE |
64 | struct ihs_mdio { |
65 | u16 control; | |
66 | u16 address_data; | |
67 | u16 rx_data; | |
68 | }; | |
69 | ||
70 | struct ihs_io_ep { | |
71 | u16 transmit_data; | |
72 | u16 rx_tx_control; | |
73 | u16 receive_data; | |
74 | u16 rx_tx_status; | |
75 | u16 reserved; | |
76 | u16 device_address; | |
77 | u16 target_address; | |
78 | }; | |
79 | ||
6e9e6c36 | 80 | #ifdef CONFIG_NEO |
0e60aa85 | 81 | struct ihs_fpga { |
6e9e6c36 DE |
82 | u16 reflection_low; /* 0x0000 */ |
83 | u16 versions; /* 0x0002 */ | |
84 | u16 fpga_features; /* 0x0004 */ | |
85 | u16 fpga_version; /* 0x0006 */ | |
86 | u16 reserved_0[8187]; /* 0x0008 */ | |
87 | u16 reflection_high; /* 0x3ffe */ | |
0e60aa85 | 88 | }; |
6e9e6c36 DE |
89 | #endif |
90 | ||
2da0fc0d | 91 | #ifdef CONFIG_IO |
0e60aa85 | 92 | struct ihs_fpga { |
2da0fc0d DE |
93 | u16 reflection_low; /* 0x0000 */ |
94 | u16 versions; /* 0x0002 */ | |
95 | u16 fpga_features; /* 0x0004 */ | |
96 | u16 fpga_version; /* 0x0006 */ | |
97 | u16 reserved_0[5]; /* 0x0008 */ | |
98 | u16 quad_serdes_reset; /* 0x0012 */ | |
99 | u16 reserved_1[8181]; /* 0x0014 */ | |
100 | u16 reflection_high; /* 0x3ffe */ | |
0e60aa85 | 101 | }; |
2da0fc0d DE |
102 | #endif |
103 | ||
255ef4d9 | 104 | #ifdef CONFIG_IO64 |
aba27acf DE |
105 | struct ihs_fpga_channel { |
106 | u16 status_int; | |
107 | u16 config_int; | |
108 | u16 switch_connect_config; | |
109 | u16 tx_destination; | |
110 | }; | |
111 | ||
112 | struct ihs_fpga_hicb { | |
113 | u16 status_int; | |
114 | u16 config_int; | |
115 | }; | |
116 | ||
0e60aa85 | 117 | struct ihs_fpga { |
255ef4d9 DE |
118 | u16 reflection_low; /* 0x0000 */ |
119 | u16 versions; /* 0x0002 */ | |
120 | u16 fpga_features; /* 0x0004 */ | |
121 | u16 fpga_version; /* 0x0006 */ | |
122 | u16 reserved_0[5]; /* 0x0008 */ | |
123 | u16 quad_serdes_reset; /* 0x0012 */ | |
124 | u16 reserved_1[502]; /* 0x0014 */ | |
aba27acf DE |
125 | struct ihs_fpga_channel ch[32]; /* 0x0400 */ |
126 | struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ | |
127 | u16 reserved_2[7487]; /* 0x0580 */ | |
255ef4d9 | 128 | u16 reflection_high; /* 0x3ffe */ |
0e60aa85 | 129 | }; |
255ef4d9 DE |
130 | #endif |
131 | ||
2da0fc0d | 132 | #ifdef CONFIG_IOCON |
0e60aa85 | 133 | struct ihs_fpga { |
2da0fc0d DE |
134 | u16 reflection_low; /* 0x0000 */ |
135 | u16 versions; /* 0x0002 */ | |
136 | u16 fpga_version; /* 0x0004 */ | |
137 | u16 fpga_features; /* 0x0006 */ | |
50dcf89d DE |
138 | u16 reserved_0[1]; /* 0x0008 */ |
139 | u16 top_interrupt; /* 0x000a */ | |
140 | u16 reserved_1[4]; /* 0x000c */ | |
141 | struct ihs_gpio gpio; /* 0x0014 */ | |
142 | u16 mpc3w_control; /* 0x001a */ | |
143 | u16 reserved_2[2]; /* 0x001c */ | |
144 | struct ihs_io_ep ep; /* 0x0020 */ | |
145 | u16 reserved_3[9]; /* 0x002e */ | |
071be896 | 146 | struct ihs_i2c i2c0; /* 0x0040 */ |
50dcf89d DE |
147 | u16 reserved_4[10]; /* 0x004c */ |
148 | u16 mc_int; /* 0x0060 */ | |
149 | u16 mc_int_en; /* 0x0062 */ | |
150 | u16 mc_status; /* 0x0064 */ | |
151 | u16 mc_control; /* 0x0066 */ | |
152 | u16 mc_tx_data; /* 0x0068 */ | |
153 | u16 mc_tx_address; /* 0x006a */ | |
154 | u16 mc_tx_cmd; /* 0x006c */ | |
155 | u16 mc_res; /* 0x006e */ | |
156 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
157 | u16 mc_rx_data; /* 0x0072 */ | |
158 | u16 reserved_5[69]; /* 0x0074 */ | |
159 | u16 reflection_high; /* 0x00fe */ | |
7ed45d3d | 160 | struct ihs_osd osd0; /* 0x0100 */ |
50dcf89d | 161 | u16 reserved_6[889]; /* 0x010e */ |
7ed45d3d | 162 | u16 videomem0[2048]; /* 0x0800 */ |
50dcf89d DE |
163 | }; |
164 | #endif | |
165 | ||
166 | #ifdef CONFIG_HRCON | |
167 | struct ihs_fpga { | |
168 | u16 reflection_low; /* 0x0000 */ | |
169 | u16 versions; /* 0x0002 */ | |
170 | u16 fpga_version; /* 0x0004 */ | |
171 | u16 fpga_features; /* 0x0006 */ | |
172 | u16 reserved_0[1]; /* 0x0008 */ | |
173 | u16 top_interrupt; /* 0x000a */ | |
7ed45d3d DE |
174 | u16 reserved_1[2]; /* 0x000c */ |
175 | u16 control; /* 0x0010 */ | |
176 | u16 extended_control; /* 0x0012 */ | |
0e60aa85 | 177 | struct ihs_gpio gpio; /* 0x0014 */ |
2da0fc0d | 178 | u16 mpc3w_control; /* 0x001a */ |
50dcf89d DE |
179 | u16 reserved_2[2]; /* 0x001c */ |
180 | struct ihs_io_ep ep; /* 0x0020 */ | |
181 | u16 reserved_3[9]; /* 0x002e */ | |
071be896 | 182 | struct ihs_i2c i2c0; /* 0x0040 */ |
50dcf89d | 183 | u16 reserved_4[10]; /* 0x004c */ |
e50e8968 DE |
184 | u16 mc_int; /* 0x0060 */ |
185 | u16 mc_int_en; /* 0x0062 */ | |
186 | u16 mc_status; /* 0x0064 */ | |
187 | u16 mc_control; /* 0x0066 */ | |
188 | u16 mc_tx_data; /* 0x0068 */ | |
189 | u16 mc_tx_address; /* 0x006a */ | |
190 | u16 mc_tx_cmd; /* 0x006c */ | |
191 | u16 mc_res; /* 0x006e */ | |
192 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
193 | u16 mc_rx_data; /* 0x0072 */ | |
50dcf89d | 194 | u16 reserved_5[69]; /* 0x0074 */ |
2da0fc0d | 195 | u16 reflection_high; /* 0x00fe */ |
7ed45d3d DE |
196 | struct ihs_osd osd0; /* 0x0100 */ |
197 | #ifdef CONFIG_SYS_OSD_DH | |
198 | u16 reserved_6[57]; /* 0x010e */ | |
199 | struct ihs_osd osd1; /* 0x0180 */ | |
200 | u16 reserved_7[9]; /* 0x018e */ | |
201 | struct ihs_i2c i2c1; /* 0x01a0 */ | |
202 | u16 reserved_8[1834]; /* 0x01ac */ | |
203 | u16 videomem0[2048]; /* 0x1000 */ | |
204 | u16 videomem1[2048]; /* 0x2000 */ | |
205 | #else | |
50dcf89d | 206 | u16 reserved_6[889]; /* 0x010e */ |
7ed45d3d DE |
207 | u16 videomem0[2048]; /* 0x0800 */ |
208 | #endif | |
0e60aa85 | 209 | }; |
2da0fc0d DE |
210 | #endif |
211 | ||
a3f9d6c7 DE |
212 | #ifdef CONFIG_STRIDER_CPU |
213 | struct ihs_fpga { | |
214 | u16 reflection_low; /* 0x0000 */ | |
215 | u16 versions; /* 0x0002 */ | |
216 | u16 fpga_version; /* 0x0004 */ | |
217 | u16 fpga_features; /* 0x0006 */ | |
218 | u16 reserved_0[1]; /* 0x0008 */ | |
219 | u16 top_interrupt; /* 0x000a */ | |
220 | u16 reserved_1[3]; /* 0x000c */ | |
221 | u16 extended_control; /* 0x0012 */ | |
222 | struct ihs_gpio gpio; /* 0x0014 */ | |
223 | u16 mpc3w_control; /* 0x001a */ | |
224 | u16 reserved_2[2]; /* 0x001c */ | |
225 | struct ihs_io_ep ep; /* 0x0020 */ | |
226 | u16 reserved_3[9]; /* 0x002e */ | |
227 | u16 mc_int; /* 0x0040 */ | |
228 | u16 mc_int_en; /* 0x0042 */ | |
229 | u16 mc_status; /* 0x0044 */ | |
230 | u16 mc_control; /* 0x0046 */ | |
231 | u16 mc_tx_data; /* 0x0048 */ | |
232 | u16 mc_tx_address; /* 0x004a */ | |
233 | u16 mc_tx_cmd; /* 0x004c */ | |
234 | u16 mc_res; /* 0x004e */ | |
235 | u16 mc_rx_cmd_status; /* 0x0050 */ | |
236 | u16 mc_rx_data; /* 0x0052 */ | |
237 | u16 reserved_4[62]; /* 0x0054 */ | |
238 | struct ihs_i2c i2c0; /* 0x00d0 */ | |
239 | }; | |
240 | #endif | |
241 | ||
242 | #ifdef CONFIG_STRIDER_CON | |
243 | struct ihs_fpga { | |
244 | u16 reflection_low; /* 0x0000 */ | |
245 | u16 versions; /* 0x0002 */ | |
246 | u16 fpga_version; /* 0x0004 */ | |
247 | u16 fpga_features; /* 0x0006 */ | |
248 | u16 reserved_0[1]; /* 0x0008 */ | |
249 | u16 top_interrupt; /* 0x000a */ | |
250 | u16 reserved_1[4]; /* 0x000c */ | |
251 | struct ihs_gpio gpio; /* 0x0014 */ | |
252 | u16 mpc3w_control; /* 0x001a */ | |
253 | u16 reserved_2[2]; /* 0x001c */ | |
254 | struct ihs_io_ep ep; /* 0x0020 */ | |
255 | u16 reserved_3[9]; /* 0x002e */ | |
256 | struct ihs_i2c i2c0; /* 0x0040 */ | |
257 | u16 reserved_4[10]; /* 0x004c */ | |
258 | u16 mc_int; /* 0x0060 */ | |
259 | u16 mc_int_en; /* 0x0062 */ | |
260 | u16 mc_status; /* 0x0064 */ | |
261 | u16 mc_control; /* 0x0066 */ | |
262 | u16 mc_tx_data; /* 0x0068 */ | |
263 | u16 mc_tx_address; /* 0x006a */ | |
264 | u16 mc_tx_cmd; /* 0x006c */ | |
265 | u16 mc_res; /* 0x006e */ | |
266 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
267 | u16 mc_rx_data; /* 0x0072 */ | |
268 | u16 reserved_5[70]; /* 0x0074 */ | |
7ed45d3d | 269 | struct ihs_osd osd0; /* 0x0100 */ |
a3f9d6c7 | 270 | u16 reserved_6[889]; /* 0x010e */ |
7ed45d3d | 271 | u16 videomem0[2048]; /* 0x0800 */ |
a3f9d6c7 DE |
272 | }; |
273 | #endif | |
274 | ||
2da0fc0d | 275 | #ifdef CONFIG_DLVISION_10G |
0e60aa85 | 276 | struct ihs_fpga { |
2da0fc0d DE |
277 | u16 reflection_low; /* 0x0000 */ |
278 | u16 versions; /* 0x0002 */ | |
279 | u16 fpga_version; /* 0x0004 */ | |
280 | u16 fpga_features; /* 0x0006 */ | |
281 | u16 reserved_0[10]; /* 0x0008 */ | |
282 | u16 extended_interrupt; /* 0x001c */ | |
b46226bd | 283 | u16 reserved_1[29]; /* 0x001e */ |
7749c84e | 284 | u16 mpc3w_control; /* 0x0058 */ |
b46226bd | 285 | u16 reserved_2[3]; /* 0x005a */ |
071be896 DE |
286 | struct ihs_i2c i2c0; /* 0x0060 */ |
287 | u16 reserved_3[2]; /* 0x006c */ | |
288 | struct ihs_i2c i2c1; /* 0x0070 */ | |
289 | u16 reserved_4[194]; /* 0x007c */ | |
7ed45d3d | 290 | struct ihs_osd osd0; /* 0x0200 */ |
071be896 | 291 | u16 reserved_5[761]; /* 0x020e */ |
7ed45d3d | 292 | u16 videomem0[2048]; /* 0x0800 */ |
0e60aa85 | 293 | }; |
2da0fc0d DE |
294 | #endif |
295 | ||
296 | #endif |