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Commit | Line | Data |
---|---|---|
8e2e601c | 1 | CONFIG_ARM=y |
a2ac2b96 | 2 | CONFIG_SPL_SKIP_LOWLEVEL_INIT=y |
f76750d1 | 3 | CONFIG_SYS_ARCH_TIMER=y |
7ba79f26 | 4 | # CONFIG_SPL_USE_ARCH_MEMCPY is not set |
8e2e601c MP |
5 | CONFIG_ARCH_ROCKCHIP=y |
6 | CONFIG_SYS_TEXT_BASE=0x00100000 | |
554e5514 | 7 | CONFIG_NR_DRAM_BANKS=1 |
2bba7807 | 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" |
c5a6e9f8 | 9 | CONFIG_SPL_TEXT_BASE=0xff704000 |
8e2e601c | 10 | CONFIG_ROCKCHIP_RK3288=y |
103c5f18 | 11 | # CONFIG_SPL_MMC is not set |
8e2e601c | 12 | CONFIG_TARGET_CHROMEBOOK_SPEEDY=y |
d168bcb6 | 13 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
8e2e601c MP |
14 | CONFIG_DEBUG_UART_BASE=0xff690000 |
15 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
8e2e601c | 16 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
ea2ca7e1 | 17 | CONFIG_SPL_SPI=y |
d46e86d2 | 18 | CONFIG_SYS_LOAD_ADDR=0x800800 |
556fd590 | 19 | CONFIG_SPL_PAYLOAD="u-boot.img" |
f7d0ae9c | 20 | CONFIG_DEBUG_UART=y |
eaf6ea6a TR |
21 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
22 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 | |
37304aaf | 23 | CONFIG_USE_PREBOOT=y |
8e2e601c | 24 | CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" |
0817daa7 | 25 | CONFIG_SILENT_CONSOLE=y |
8e2e601c MP |
26 | # CONFIG_DISPLAY_CPUINFO is not set |
27 | CONFIG_DISPLAY_BOARDINFO_LATE=y | |
fffdf729 | 28 | CONFIG_BOARD_EARLY_INIT_R=y |
ca8a329a | 29 | CONFIG_SPL_PAD_TO=0x7f8000 |
9b5f9aeb | 30 | CONFIG_SPL_NO_BSS_LIMIT=y |
7ba79f26 | 31 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
f113d7d3 TR |
32 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
33 | CONFIG_SPL_STACK=0xff718000 | |
8e2e601c MP |
34 | CONFIG_SPL_STACK_R=y |
35 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 | |
7ba79f26 | 36 | # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set |
1e52db67 | 37 | # CONFIG_SPL_CRC32 is not set |
8e2e601c | 38 | CONFIG_SPL_SPI_LOAD=y |
3e5b62f7 | 39 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 |
8e2e601c MP |
40 | CONFIG_CMD_GPIO=y |
41 | CONFIG_CMD_GPT=y | |
42 | CONFIG_CMD_I2C=y | |
43 | CONFIG_CMD_MMC=y | |
8e2e601c MP |
44 | CONFIG_CMD_SF_TEST=y |
45 | CONFIG_CMD_SPI=y | |
46 | CONFIG_CMD_USB=y | |
47 | # CONFIG_CMD_SETEXPR is not set | |
48 | CONFIG_CMD_CACHE=y | |
49 | CONFIG_CMD_TIME=y | |
50 | CONFIG_CMD_PMIC=y | |
51 | CONFIG_CMD_REGULATOR=y | |
52 | # CONFIG_SPL_DOS_PARTITION is not set | |
53 | # CONFIG_SPL_EFI_PARTITION is not set | |
8e2e601c | 54 | CONFIG_SPL_OF_CONTROL=y |
8e2e601c MP |
55 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
56 | CONFIG_SPL_OF_PLATDATA=y | |
8d8ee47e | 57 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
8e2e601c MP |
58 | CONFIG_REGMAP=y |
59 | CONFIG_SPL_REGMAP=y | |
60 | CONFIG_SYSCON=y | |
61 | CONFIG_SPL_SYSCON=y | |
62 | # CONFIG_SPL_SIMPLE_BUS is not set | |
7ba79f26 | 63 | # CONFIG_SPL_BLK is not set |
8e2e601c MP |
64 | CONFIG_CLK=y |
65 | CONFIG_SPL_CLK=y | |
8e2e601c MP |
66 | CONFIG_ROCKCHIP_GPIO=y |
67 | CONFIG_I2C_CROS_EC_TUNNEL=y | |
68 | CONFIG_SYS_I2C_ROCKCHIP=y | |
69 | CONFIG_I2C_MUX=y | |
70 | CONFIG_DM_KEYBOARD=y | |
93e1edff | 71 | CONFIG_KEYBOARD=y |
8e2e601c MP |
72 | CONFIG_CROS_EC_KEYB=y |
73 | CONFIG_CROS_EC=y | |
74 | CONFIG_CROS_EC_SPI=y | |
75 | CONFIG_PWRSEQ=y | |
144d0574 | 76 | CONFIG_MMC_PWRSEQ=y |
7ba79f26 | 77 | # CONFIG_SPL_DM_MMC is not set |
8e2e601c MP |
78 | CONFIG_MMC_DW=y |
79 | CONFIG_MMC_DW_ROCKCHIP=y | |
888f184a | 80 | CONFIG_MTD=y |
7ba79f26 | 81 | CONFIG_SF_DEFAULT_BUS=2 |
14453fbf | 82 | CONFIG_SF_DEFAULT_SPEED=20000000 |
64df512e | 83 | CONFIG_SPI_FLASH_GIGADEVICE=y |
8e2e601c | 84 | CONFIG_PINCTRL=y |
7ba79f26 | 85 | CONFIG_PINCONF=y |
8e2e601c | 86 | CONFIG_SPL_PINCTRL=y |
5e50f878 | 87 | # CONFIG_SPL_PINCTRL_FULL is not set |
8e2e601c MP |
88 | CONFIG_DM_PMIC=y |
89 | # CONFIG_SPL_PMIC_CHILDREN is not set | |
90 | CONFIG_PMIC_RK8XX=y | |
91 | CONFIG_DM_REGULATOR_FIXED=y | |
92 | CONFIG_REGULATOR_RK8XX=y | |
93 | CONFIG_PWM_ROCKCHIP=y | |
94 | CONFIG_RAM=y | |
95 | CONFIG_SPL_RAM=y | |
96 | CONFIG_DEBUG_UART_SHIFT=2 | |
97 | CONFIG_ROCKCHIP_SERIAL=y | |
98 | CONFIG_ROCKCHIP_SPI=y | |
99 | CONFIG_SYSRESET=y | |
100 | CONFIG_USB=y | |
7ba79f26 UR |
101 | # CONFIG_SPL_DM_USB is not set |
102 | CONFIG_USB_DWC2=y | |
8e2e601c | 103 | CONFIG_ROCKCHIP_USB2_PHY=y |
8e2e601c | 104 | CONFIG_DM_VIDEO=y |
8a6ffeda | 105 | # CONFIG_VIDEO_BPP8 is not set |
8e2e601c MP |
106 | CONFIG_CONSOLE_TRUETYPE=y |
107 | CONFIG_DISPLAY=y | |
108 | CONFIG_VIDEO_ROCKCHIP=y | |
109 | CONFIG_DISPLAY_ROCKCHIP_EDP=y | |
110 | CONFIG_DISPLAY_ROCKCHIP_HDMI=y | |
111 | # CONFIG_USE_PRIVATE_LIBGCC is not set | |
7ba79f26 | 112 | CONFIG_SPL_TINY_MEMSET=y |
8e2e601c MP |
113 | CONFIG_CMD_DHRYSTONE=y |
114 | CONFIG_ERRNO_STR=y |