[J-u-boot.git] / board / cpc45 / cpc45.c

/*
 * (C) Copyright 2001
 * Rob Taylor, Flying Pig Systems. [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <i2c.h>
#include <netdev.h>

int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
extern void SPD67290Init(void);

	/* We have to clear the initial data area here. Couldn't have done it
	 * earlier because DRAM had not been initialized.
	 */
int board_early_init_f(void)
{

	/* enable DUAL UART Mode on CPC45 */
	*(uchar*)DUART_DCR |= 0x1;	/* set DCM bit */

	return 0;
}

int checkboard(void)
{
/*
	char  revision = BOARD_REV;
*/
	ulong busfreq  = get_bus_freq(0);
	char  buf[32];

	puts ("CPC45  ");
/*
	printf("Revision %d ", revision);
*/
	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));

	return 0;
}

phys_size_t initdram (int board_type)
{
	int m, row, col, bank, i, ref;
	unsigned long start, end;
	uint32_t mccr1, mccr2;
	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	uint8_t mber = 0;
	unsigned int tmp;

	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	if (i2c_reg_read (0x50, 2) != 0x04)
		return 0;	/* Memory type */

	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
	row = i2c_reg_read (0x50, 3);	/* # of rows */
	col = i2c_reg_read (0x50, 4);	/* # of columns */
	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */

	CONFIG_READ_WORD(MCCR1, mccr1);
	mccr1 &= 0xffff0000;

	CONFIG_READ_WORD(MCCR2, mccr2);
	mccr2 &= 0xffff0000;

	start = CONFIG_SYS_SDRAM_BASE;
	end = start + (1 << (col + row + 3) ) * bank - 1;

	for (i = 0; i < m; i++) {
		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
		if (i < 4) {
			msar1  |= ((start >> 20) & 0xff) << i * 8;
			emsar1 |= ((start >> 28) & 0xff) << i * 8;
			mear1  |= ((end >> 20) & 0xff) << i * 8;
			emear1 |= ((end >> 28) & 0xff) << i * 8;
		} else {
			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
		}
		mber |= 1 << i;
		start += (1 << (col + row + 3) ) * bank;
		end += (1 << (col + row + 3) ) * bank;
	}
	for (; i < 8; i++) {
		if (i < 4) {
			msar1  |= 0xff << i * 8;
			emsar1 |= 0x30 << i * 8;
			mear1  |= 0xff << i * 8;
			emear1 |= 0x30 << i * 8;
		} else {
			msar2  |= 0xff << (i-4) * 8;
			emsar2 |= 0x30 << (i-4) * 8;
			mear2  |= 0xff << (i-4) * 8;
			emear2 |= 0x30 << (i-4) * 8;
		}
	}

	switch(ref) {
		case 0x00:
		case 0x80:
			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
			break;
		case 0x01:
		case 0x81:
			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
			break;
		case 0x02:
		case 0x82:
			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
			break;
		case 0x03:
		case 0x83:
			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
			break;
		case 0x04:
		case 0x84:
			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
			break;
		case 0x05:
		case 0x85:
			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
			break;
		default:
			tmp = 0x512;
			break;
	}

	CONFIG_WRITE_WORD(MCCR1, mccr1);
	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
	CONFIG_WRITE_WORD(MSAR1, msar1);
	CONFIG_WRITE_WORD(EMSAR1, emsar1);
	CONFIG_WRITE_WORD(MEAR1, mear1);
	CONFIG_WRITE_WORD(EMEAR1, emear1);
	CONFIG_WRITE_WORD(MSAR2, msar2);
	CONFIG_WRITE_WORD(EMSAR2, emsar2);
	CONFIG_WRITE_WORD(MEAR2, mear2);
	CONFIG_WRITE_WORD(EMEAR2, emear2);
	CONFIG_WRITE_BYTE(MBER, mber);

	return (1 << (col + row + 3) ) * bank * m;
}


/*
 * Initialize PCI Devices, report devices found.
 */

static struct pci_config_table pci_cpc45_config_table[] = {
#ifndef CONFIG_PCI_PNP
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				       PCI_ENET0_MEMADDR,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
				       PCI_PLX9030_MEMADDR,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
				       PCMCIA_IO_BASE,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
#endif /*CONFIG_PCI_PNP*/
	{ }
};

struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_cpc45_config_table,
#endif
};

void pci_init_board(void)
{
	pci_mpc824x_init(&hose);

	/* init PCI_to_LOCAL Bus BRIDGE */
	Plx9030Init();

	/* Clear Display */
	DISP_CWORD = 0x0;

	sysControlDisplay(0,' ');
	sysControlDisplay(1,'C');
	sysControlDisplay(2,'P');
	sysControlDisplay(3,'C');
	sysControlDisplay(4,' ');
	sysControlDisplay(5,'4');
	sysControlDisplay(6,'5');
	sysControlDisplay(7,' ');

}

/**************************************************************************
*
* sysControlDisplay - controls one of the Alphanum. Display digits.
*
* This routine will write an ASCII character to the display digit requested.
*
* SEE ALSO:
*
* RETURNS: NA
*/

int sysControlDisplay (int digit,	/* number of digit 0..7 */
		       uchar ascii_code	/* ASCII code */
		      )
{
	if ((digit < 0) || (digit > 7))
		return (-1);

	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;

	return (0);
}

#if defined(CONFIG_CMD_PCMCIA)

#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
#endif

int pcmcia_init(void)
{
	u_int rc;

	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");

	rc = i82365_init();

	return rc;
}

#endif

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}
Commit	Line	Data
3bac3513 WD	1	/*
	2	* (C) Copyright 2001
	3	* Rob Taylor, Flying Pig Systems. [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3bac3513 WD	6	*/
	7
	8	#include <common.h>
	9	#include <mpc824x.h>
	10	#include <asm/processor.h>
e2ffd59b	11	#include <asm/io.h>
3bac3513	12	#include <pci.h>
49822e23	13	#include <i2c.h>
10efa024	14	#include <netdev.h>
3bac3513	15
8bde7f77	16	int sysControlDisplay(int digit, uchar ascii_code);
3bac3513	17	extern void Plx9030Init(void);
e2ffd59b	18	extern void SPD67290Init(void);
3bac3513 WD	19
	20	/* We have to clear the initial data area here. Couldn't have done it
	21	* earlier because DRAM had not been initialized.
	22	*/
c837dcb1	23	int board_early_init_f(void)
3bac3513 WD	24	{
	25
	26	/* enable DUAL UART Mode on CPC45 */
	27	(uchar)DUART_DCR \|= 0x1; /* set DCM bit */
	28
	29	return 0;
	30	}
	31
	32	int checkboard(void)
	33	{
	34	/*
	35	char revision = BOARD_REV;
	36	*/
	37	ulong busfreq = get_bus_freq(0);
	38	char buf[32];
	39
d7a04603	40	puts ("CPC45 ");
3bac3513 WD	41	/*
	42	printf("Revision %d ", revision);
	43	*/
	44	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
	45
	46	return 0;
	47	}
	48
9973e3c6	49	phys_size_t initdram (int board_type)
3bac3513	50	{
49822e23 WD	51	int m, row, col, bank, i, ref;
	52	unsigned long start, end;
	53	uint32_t mccr1, mccr2;
	54	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	55	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	56	uint8_t mber = 0;
	57	unsigned int tmp;
	58
6d0f6bcf	59	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
49822e23 WD	60
	61	if (i2c_reg_read (0x50, 2) != 0x04)
	62	return 0; /* Memory type */
	63
	64	m = i2c_reg_read (0x50, 5); /* # of physical banks */
	65	row = i2c_reg_read (0x50, 3); /* # of rows */
	66	col = i2c_reg_read (0x50, 4); /* # of columns */
	67	bank = i2c_reg_read (0x50, 17); /* # of logical banks */
	68	ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
	69
	70	CONFIG_READ_WORD(MCCR1, mccr1);
	71	mccr1 &= 0xffff0000;
	72
	73	CONFIG_READ_WORD(MCCR2, mccr2);
	74	mccr2 &= 0xffff0000;
	75
6d0f6bcf	76	start = CONFIG_SYS_SDRAM_BASE;
49822e23 WD	77	end = start + (1 << (col + row + 3) ) * bank - 1;
	78
	79	for (i = 0; i < m; i++) {
	80	mccr1 \|= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
	81	if (i < 4) {
	82	msar1 \|= ((start >> 20) & 0xff) << i * 8;
	83	emsar1 \|= ((start >> 28) & 0xff) << i * 8;
	84	mear1 \|= ((end >> 20) & 0xff) << i * 8;
	85	emear1 \|= ((end >> 28) & 0xff) << i * 8;
	86	} else {
	87	msar2 \|= ((start >> 20) & 0xff) << (i-4) * 8;
	88	emsar2 \|= ((start >> 28) & 0xff) << (i-4) * 8;
	89	mear2 \|= ((end >> 20) & 0xff) << (i-4) * 8;
	90	emear2 \|= ((end >> 28) & 0xff) << (i-4) * 8;
	91	}
	92	mber \|= 1 << i;
	93	start += (1 << (col + row + 3) ) * bank;
	94	end += (1 << (col + row + 3) ) * bank;
	95	}
	96	for (; i < 8; i++) {
	97	if (i < 4) {
	98	msar1 \|= 0xff << i * 8;
	99	emsar1 \|= 0x30 << i * 8;
	100	mear1 \|= 0xff << i * 8;
	101	emear1 \|= 0x30 << i * 8;
	102	} else {
	103	msar2 \|= 0xff << (i-4) * 8;
	104	emsar2 \|= 0x30 << (i-4) * 8;
	105	mear2 \|= 0xff << (i-4) * 8;
	106	emear2 \|= 0x30 << (i-4) * 8;
	107	}
	108	}
	109
	110	switch(ref) {
	111	case 0x00:
	112	case 0x80:
	113	tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
	114	break;
	115	case 0x01:
	116	case 0x81:
	117	tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
	118	break;
	119	case 0x02:
	120	case 0x82:
	121	tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
	122	break;
	123	case 0x03:
	124	case 0x83:
	125	tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
	126	break;
	127	case 0x04:
	128	case 0x84:
	129	tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
	130	break;
	131	case 0x05:
	132	case 0x85:
	133	tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
	134	break;
	135	default:
	136	tmp = 0x512;
	137	break;
	138	}
	139
	140	CONFIG_WRITE_WORD(MCCR1, mccr1);
141	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
142	CONFIG_WRITE_WORD(MSAR1, msar1);
143	CONFIG_WRITE_WORD(EMSAR1, emsar1);
144	CONFIG_WRITE_WORD(MEAR1, mear1);
145	CONFIG_WRITE_WORD(EMEAR1, emear1);
146	CONFIG_WRITE_WORD(MSAR2, msar2);
147	CONFIG_WRITE_WORD(EMSAR2, emsar2);
148	CONFIG_WRITE_WORD(MEAR2, mear2);
149	CONFIG_WRITE_WORD(EMEAR2, emear2);
150	CONFIG_WRITE_BYTE(MBER, mber);
151
152	return (1 << (col + row + 3) ) * bank * m;
3bac3513 WD	153	}
3bac3513 WD	154
49822e23	155
3bac3513 WD	156	/*
	157	* Initialize PCI Devices, report devices found.
	158	*/
3bac3513	159
49822e23 WD	160	static struct pci_config_table pci_cpc45_config_table[] = {
	161	#ifndef CONFIG_PCI_PNP
	162	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
3bac3513 WD	163	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	164	PCI_ENET0_MEMADDR,
	165	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER }},
49822e23 WD	166	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
	167	pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
	168	PCI_PLX9030_MEMADDR,
	169	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER }},
e2ffd59b WD	170	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
	171	pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
	172	PCMCIA_IO_BASE,
	173	PCI_COMMAND_MEMORY \| PCI_COMMAND_IO }},
49822e23	174	#endif /CONFIG_PCI_PNP/
3bac3513 WD	175	{ }
3bac3513 WD	176	};
3bac3513 WD	177
	178	struct pci_controller hose = {
	179	#ifndef CONFIG_PCI_PNP
49822e23	180	config_table: pci_cpc45_config_table,
3bac3513 WD	181	#endif
	182	};
	183
	184	void pci_init_board(void)
	185	{
	186	pci_mpc824x_init(&hose);
	187
	188	/* init PCI_to_LOCAL Bus BRIDGE */
	189	Plx9030Init();
	190
49822e23 WD	191	/* Clear Display */
	192	DISP_CWORD = 0x0;
	193
3bac3513 WD	194	sysControlDisplay(0,' ');
	195	sysControlDisplay(1,'C');
	196	sysControlDisplay(2,'P');
	197	sysControlDisplay(3,'C');
	198	sysControlDisplay(4,' ');
	199	sysControlDisplay(5,'4');
	200	sysControlDisplay(6,'5');
	201	sysControlDisplay(7,' ');
	202
	203	}
	204
	205	/**************************************************************************
	206	*
	207	* sysControlDisplay - controls one of the Alphanum. Display digits.
	208	*
	209	* This routine will write an ASCII character to the display digit requested.
	210	*
	211	* SEE ALSO:
	212	*
	213	* RETURNS: NA
	214	*/
	215
49822e23 WD	216	int sysControlDisplay (int digit, /* number of digit 0..7 */
	217	uchar ascii_code /* ASCII code */
	218	)
3bac3513 WD	219	{
	220	if ((digit < 0) \|\| (digit > 7))
	221	return (-1);
	222
49822e23	223	((volatile uchar ) (DISP_CHR_RAM + digit)) = ascii_code;
3bac3513 WD	224
	225	return (0);
	226	}
e2ffd59b	227
fcec2eb9	228	#if defined(CONFIG_CMD_PCMCIA)
e2ffd59b	229
6d0f6bcf JCPV	230	#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
6d0f6bcf JCPV	231	volatile unsigned char pcmcia_mem = (unsigned char)CONFIG_SYS_PCMCIA_MEM_ADDR;
e2ffd59b WD	232	#endif
	233
	234	int pcmcia_init(void)
	235	{
	236	u_int rc;
	237
	238	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
	239
	240	rc = i82365_init();
	241
	242	return rc;
	243	}
	244
77a31854	245	#endif
e2ffd59b	246
10efa024 BW	247	int board_eth_init(bd_t *bis)
	248	{
	249	return pci_eth_init(bis);
	250	}