[J-u-boot.git] / include / dwmmc.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <[email protected]>
 */

#ifndef __DWMMC_HW_H
#define __DWMMC_HW_H

#include <asm/cache.h>
#include <asm/io.h>
#include <mmc.h>

#define DWMCI_CTRL		0x000
#define	DWMCI_PWREN		0x004
#define DWMCI_CLKDIV		0x008
#define DWMCI_CLKSRC		0x00C
#define DWMCI_CLKENA		0x010
#define DWMCI_TMOUT		0x014
#define DWMCI_CTYPE		0x018
#define DWMCI_BLKSIZ		0x01C
#define DWMCI_BYTCNT		0x020
#define DWMCI_INTMASK		0x024
#define DWMCI_CMDARG		0x028
#define DWMCI_CMD		0x02C
#define DWMCI_RESP0		0x030
#define DWMCI_RESP1		0x034
#define DWMCI_RESP2		0x038
#define DWMCI_RESP3		0x03C
#define DWMCI_MINTSTS		0x040
#define DWMCI_RINTSTS		0x044
#define DWMCI_STATUS		0x048
#define DWMCI_FIFOTH		0x04C
#define DWMCI_CDETECT		0x050
#define DWMCI_WRTPRT		0x054
#define DWMCI_GPIO		0x058
#define DWMCI_TCMCNT		0x05C
#define DWMCI_TBBCNT		0x060
#define DWMCI_DEBNCE		0x064
#define DWMCI_USRID		0x068
#define DWMCI_VERID		0x06C
#define DWMCI_HCON		0x070
#define DWMCI_UHS_REG		0x074
#define DWMCI_BMOD		0x080
#define DWMCI_PLDMND		0x084
#define DWMCI_DBADDR		0x088
#define DWMCI_IDSTS		0x08C
#define DWMCI_IDINTEN		0x090
#define DWMCI_DSCADDR		0x094
#define DWMCI_BUFADDR		0x098
#define DWMCI_DATA		0x200

/* Interrupt Mask register */
#define DWMCI_INTMSK_ALL	0xffffffff
#define DWMCI_INTMSK_RE		(1 << 1)
#define DWMCI_INTMSK_CDONE	(1 << 2)
#define DWMCI_INTMSK_DTO	(1 << 3)
#define DWMCI_INTMSK_TXDR	(1 << 4)
#define DWMCI_INTMSK_RXDR	(1 << 5)
#define DWMCI_INTMSK_RCRC	(1 << 6)
#define DWMCI_INTMSK_DCRC	(1 << 7)
#define DWMCI_INTMSK_RTO	(1 << 8)
#define DWMCI_INTMSK_DRTO	(1 << 9)
#define DWMCI_INTMSK_HTO	(1 << 10)
#define DWMCI_INTMSK_FRUN	(1 << 11)
#define DWMCI_INTMSK_HLE	(1 << 12)
#define DWMCI_INTMSK_SBE	(1 << 13)
#define DWMCI_INTMSK_ACD	(1 << 14)
#define DWMCI_INTMSK_EBE	(1 << 15)

/* Raw interrupt Regsiter */
#define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
			DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
#define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
/* CTRL register */
#define DWMCI_CTRL_RESET	(1 << 0)
#define DWMCI_CTRL_FIFO_RESET	(1 << 1)
#define DWMCI_CTRL_DMA_RESET	(1 << 2)
#define DWMCI_DMA_EN		(1 << 5)
#define DWMCI_CTRL_SEND_AS_CCSD	(1 << 10)
#define DWMCI_IDMAC_EN		(1 << 25)
#define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
				DWMCI_CTRL_DMA_RESET)

/* CMD register */
#define DWMCI_CMD_RESP_EXP	(1 << 6)
#define DWMCI_CMD_RESP_LENGTH	(1 << 7)
#define DWMCI_CMD_CHECK_CRC	(1 << 8)
#define DWMCI_CMD_DATA_EXP	(1 << 9)
#define DWMCI_CMD_RW		(1 << 10)
#define DWMCI_CMD_SEND_STOP	(1 << 12)
#define DWMCI_CMD_ABORT_STOP	(1 << 14)
#define DWMCI_CMD_PRV_DAT_WAIT	(1 << 13)
#define DWMCI_CMD_UPD_CLK	(1 << 21)
#define DWMCI_CMD_USE_HOLD_REG	(1 << 29)
#define DWMCI_CMD_START		(1 << 31)

/* CLKENA register */
#define DWMCI_CLKEN_ENABLE	(1 << 0)
#define DWMCI_CLKEN_LOW_PWR	(1 << 16)

/* Card-type registe */
#define DWMCI_CTYPE_1BIT	0
#define DWMCI_CTYPE_4BIT	(1 << 0)
#define DWMCI_CTYPE_8BIT	(1 << 16)

/* Status Register */
#define DWMCI_FIFO_EMPTY	(1 << 2)
#define DWMCI_FIFO_FULL		(1 << 3)
#define DWMCI_BUSY		(1 << 9)
#define DWMCI_FIFO_MASK		0x1fff
#define DWMCI_FIFO_SHIFT	17

/* FIFOTH Register */
#define MSIZE(x)		((x) << 28)
#define RX_WMARK(x)		((x) << 16)
#define TX_WMARK(x)		(x)
#define RX_WMARK_SHIFT		16
#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)

#define DWMCI_IDMAC_OWN		(1 << 31)
#define DWMCI_IDMAC_CH		(1 << 4)
#define DWMCI_IDMAC_FS		(1 << 3)
#define DWMCI_IDMAC_LD		(1 << 2)

/*  Bus Mode Register */
#define DWMCI_BMOD_IDMAC_RESET	(1 << 0)
#define DWMCI_BMOD_IDMAC_FB	(1 << 1)
#define DWMCI_BMOD_IDMAC_EN	(1 << 7)

/* UHS register */
#define DWMCI_DDR_MODE	(1 << 16)

/* Internal IDMAC interrupt defines */
#define DWMCI_IDINTEN_RI		BIT(1)
#define DWMCI_IDINTEN_TI		BIT(0)

#define DWMCI_IDINTEN_MASK	(DWMCI_IDINTEN_TI | \
				 DWMCI_IDINTEN_RI)

/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)

/**
 * struct dwmci_host - Information about a designware MMC host
 *
 * @name:	Device name
 * @ioaddr:	Base I/O address of controller
 * @quirks:	Quick flags - see DWMCI_QUIRK_...
 * @caps:	Capabilities - see MMC_MODE_...
 * @bus_hz:	Bus speed in Hz, if @get_mmc_clk() is NULL
 * @div:	Arbitrary clock divider value for use by controller
 * @dev_index:	Arbitrary device index for use by controller
 * @dev_id:	Arbitrary device ID for use by controller
 * @buswidth:	Bus width in bits (8 or 4)
 * @fifoth_val:	Value for FIFOTH register (or 0 to leave unset)
 * @mmc:	Pointer to generic MMC structure for this device
 * @priv:	Private pointer for use by controller
 */
struct dwmci_host {
	const char *name;
	void *ioaddr;
	unsigned int quirks;
	unsigned int caps;
	unsigned int version;
	unsigned int clock;
	unsigned int bus_hz;
	unsigned int div;
	int dev_index;
	int dev_id;
	int buswidth;
	u32 fifoth_val;
	struct mmc *mmc;
	void *priv;

	void (*clksel)(struct dwmci_host *host);
	void (*board_init)(struct dwmci_host *host);

	/**
	 * Get / set a particular MMC clock frequency
	 *
	 * This is used to request the current clock frequency of the clock
	 * that drives the DWMMC peripheral. The caller will then use this
	 * information to work out the divider it needs to achieve the
	 * required MMC bus clock frequency. If you want to handle the
	 * clock external to DWMMC, use @freq to select the frequency and
	 * return that value too. Then DWMMC will put itself in bypass mode.
	 *
	 * @host:	DWMMC host
	 * @freq:	Frequency the host is trying to achieve
	 */
	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
#ifndef CONFIG_BLK
	struct mmc_config cfg;
#endif

	/* use fifo mode to read and write data */
	bool fifo_mode;
};

struct dwmci_idmac {
	u32 flags;
	u32 cnt;
	u32 addr;
	u32 next_addr;
} __aligned(ARCH_DMA_MINALIGN);

static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
	writel(val, host->ioaddr + reg);
}

static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
{
	writew(val, host->ioaddr + reg);
}

static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
{
	writeb(val, host->ioaddr + reg);
}
static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}

#ifdef CONFIG_BLK
/**
 * dwmci_setup_cfg() - Set up the configuration for DWMMC
 *
 * This is used to set up a DWMMC device when you are using CONFIG_BLK.
 *
 * This should be called from your MMC driver's probe() method once you have
 * the information required.
 *
 * Generally your driver will have a platform data structure which holds both
 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 * For example:
 *
 * struct rockchip_mmc_plat {
 *	struct mmc_config cfg;
 *	struct mmc mmc;
 * };
 *
 * ...
 *
 * Inside U_BOOT_DRIVER():
 *	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 *
 * To access platform data:
 *	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 *
 * See rockchip_dw_mmc.c for an example.
 *
 * @cfg:	Configuration structure to fill in (generally &plat->mmc)
 * @host:	DWMMC host
 * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
 * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
 */
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
		u32 max_clk, u32 min_clk);

/**
 * dwmci_bind() - Set up a new MMC block device
 *
 * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
 * It should be called from your driver's bind() method.
 *
 * See rockchip_dw_mmc.c for an example.
 *
 * @dev:	Device to set up
 * @mmc:	Pointer to mmc structure (normally &plat->mmc)
 * @cfg:	Empty configuration structure (generally &plat->cfg). This is
 *		normally all zeroes at this point. The only purpose of passing
 *		this in is to set mmc->cfg to it.
 * @return 0 if OK, -ve if the block device could not be created
 */
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);

#else
/**
 * add_dwmci() - Add a new DWMMC interface
 *
 * This is used when you are not using CONFIG_BLK. Convert your driver over!
 *
 * @host:	DWMMC host structure
 * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
 * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
 * @return 0 if OK, -ve on error
 */
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* !CONFIG_BLK */

#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int dwmci_probe(struct udevice *dev);
extern const struct dm_mmc_ops dm_dwmci_ops;
#endif

#endif	/* __DWMMC_HW_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
757bff49 JC	2	/*
	3	* (C) Copyright 2012 SAMSUNG Electronics
	4	* Jaehoon Chung <[email protected]>
757bff49 JC	5	*/
	6
	7	#ifndef __DWMMC_HW_H
	8	#define __DWMMC_HW_H
	9
90526e9f	10	#include <asm/cache.h>
757bff49 JC	11	#include <asm/io.h>
	12	#include <mmc.h>
	13
	14	#define DWMCI_CTRL 0x000
	15	#define DWMCI_PWREN 0x004
	16	#define DWMCI_CLKDIV 0x008
	17	#define DWMCI_CLKSRC 0x00C
	18	#define DWMCI_CLKENA 0x010
	19	#define DWMCI_TMOUT 0x014
	20	#define DWMCI_CTYPE 0x018
	21	#define DWMCI_BLKSIZ 0x01C
	22	#define DWMCI_BYTCNT 0x020
	23	#define DWMCI_INTMASK 0x024
	24	#define DWMCI_CMDARG 0x028
	25	#define DWMCI_CMD 0x02C
	26	#define DWMCI_RESP0 0x030
	27	#define DWMCI_RESP1 0x034
	28	#define DWMCI_RESP2 0x038
	29	#define DWMCI_RESP3 0x03C
	30	#define DWMCI_MINTSTS 0x040
	31	#define DWMCI_RINTSTS 0x044
	32	#define DWMCI_STATUS 0x048
	33	#define DWMCI_FIFOTH 0x04C
	34	#define DWMCI_CDETECT 0x050
	35	#define DWMCI_WRTPRT 0x054
	36	#define DWMCI_GPIO 0x058
	37	#define DWMCI_TCMCNT 0x05C
	38	#define DWMCI_TBBCNT 0x060
	39	#define DWMCI_DEBNCE 0x064
	40	#define DWMCI_USRID 0x068
	41	#define DWMCI_VERID 0x06C
	42	#define DWMCI_HCON 0x070
	43	#define DWMCI_UHS_REG 0x074
	44	#define DWMCI_BMOD 0x080
	45	#define DWMCI_PLDMND 0x084
	46	#define DWMCI_DBADDR 0x088
	47	#define DWMCI_IDSTS 0x08C
	48	#define DWMCI_IDINTEN 0x090
	49	#define DWMCI_DSCADDR 0x094
	50	#define DWMCI_BUFADDR 0x098
	51	#define DWMCI_DATA 0x200
	52
	53	/* Interrupt Mask register */
	54	#define DWMCI_INTMSK_ALL 0xffffffff
	55	#define DWMCI_INTMSK_RE (1 << 1)
	56	#define DWMCI_INTMSK_CDONE (1 << 2)
	57	#define DWMCI_INTMSK_DTO (1 << 3)
	58	#define DWMCI_INTMSK_TXDR (1 << 4)
	59	#define DWMCI_INTMSK_RXDR (1 << 5)
26cc40d8	60	#define DWMCI_INTMSK_RCRC (1 << 6)
757bff49 JC	61	#define DWMCI_INTMSK_DCRC (1 << 7)
	62	#define DWMCI_INTMSK_RTO (1 << 8)
	63	#define DWMCI_INTMSK_DRTO (1 << 9)
	64	#define DWMCI_INTMSK_HTO (1 << 10)
	65	#define DWMCI_INTMSK_FRUN (1 << 11)
	66	#define DWMCI_INTMSK_HLE (1 << 12)
	67	#define DWMCI_INTMSK_SBE (1 << 13)
	68	#define DWMCI_INTMSK_ACD (1 << 14)
	69	#define DWMCI_INTMSK_EBE (1 << 15)
	70
	71	/* Raw interrupt Regsiter */
	72	#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE \| DWMCI_INTMSK_SBE \| DWMCI_INTMSK_HLE \|\
	73	DWMCI_INTMSK_FRUN \| DWMCI_INTMSK_EBE \| DWMCI_INTMSK_DCRC)
	74	#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO \| DWMCI_INTMSK_DRTO)
	75	/* CTRL register */
	76	#define DWMCI_CTRL_RESET (1 << 0)
	77	#define DWMCI_CTRL_FIFO_RESET (1 << 1)
	78	#define DWMCI_CTRL_DMA_RESET (1 << 2)
	79	#define DWMCI_DMA_EN (1 << 5)
	80	#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
	81	#define DWMCI_IDMAC_EN (1 << 25)
	82	#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET \| DWMCI_CTRL_FIFO_RESET \|\
	83	DWMCI_CTRL_DMA_RESET)
	84
	85	/* CMD register */
	86	#define DWMCI_CMD_RESP_EXP (1 << 6)
	87	#define DWMCI_CMD_RESP_LENGTH (1 << 7)
	88	#define DWMCI_CMD_CHECK_CRC (1 << 8)
	89	#define DWMCI_CMD_DATA_EXP (1 << 9)
	90	#define DWMCI_CMD_RW (1 << 10)
	91	#define DWMCI_CMD_SEND_STOP (1 << 12)
	92	#define DWMCI_CMD_ABORT_STOP (1 << 14)
	93	#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
	94	#define DWMCI_CMD_UPD_CLK (1 << 21)
	95	#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
	96	#define DWMCI_CMD_START (1 << 31)
	97
	98	/* CLKENA register */
	99	#define DWMCI_CLKEN_ENABLE (1 << 0)
	100	#define DWMCI_CLKEN_LOW_PWR (1 << 16)
	101
	102	/* Card-type registe */
	103	#define DWMCI_CTYPE_1BIT 0
	104	#define DWMCI_CTYPE_4BIT (1 << 0)
	105	#define DWMCI_CTYPE_8BIT (1 << 16)
	106
	107	/* Status Register */
05fa06b9 HS	108	#define DWMCI_FIFO_EMPTY (1 << 2)
05fa06b9 HS	109	#define DWMCI_FIFO_FULL (1 << 3)
757bff49	110	#define DWMCI_BUSY (1 << 9)
4587f53a	111	#define DWMCI_FIFO_MASK 0x1fff
a65f51b9	112	#define DWMCI_FIFO_SHIFT 17
757bff49 JC	113
	114	/* FIFOTH Register */
	115	#define MSIZE(x) ((x) << 28)
	116	#define RX_WMARK(x) ((x) << 16)
	117	#define TX_WMARK(x) (x)
a082a2dd A	118	#define RX_WMARK_SHIFT 16
a082a2dd A	119	#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
757bff49 JC	120
	121	#define DWMCI_IDMAC_OWN (1 << 31)
	122	#define DWMCI_IDMAC_CH (1 << 4)
	123	#define DWMCI_IDMAC_FS (1 << 3)
	124	#define DWMCI_IDMAC_LD (1 << 2)
	125
	126	/* Bus Mode Register */
	127	#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
	128	#define DWMCI_BMOD_IDMAC_FB (1 << 1)
	129	#define DWMCI_BMOD_IDMAC_EN (1 << 7)
	130
045bdcd0 JC	131	/* UHS register */
	132	#define DWMCI_DDR_MODE (1 << 16)
	133
7997599e LFT	134	/* Internal IDMAC interrupt defines */
	135	#define DWMCI_IDINTEN_RI BIT(1)
	136	#define DWMCI_IDINTEN_TI BIT(0)
	137
	138	#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI \| \
	139	DWMCI_IDINTEN_RI)
	140
6f0b7caa RS	141	/* quirks */
	142	#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
	143
6dc71410 SG	144	/**
	145	* struct dwmci_host - Information about a designware MMC host
	146	*
	147	* @name: Device name
	148	* @ioaddr: Base I/O address of controller
	149	* @quirks: Quick flags - see DWMCI_QUIRK_...
	150	* @caps: Capabilities - see MMC_MODE_...
	151	* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
	152	* @div: Arbitrary clock divider value for use by controller
	153	* @dev_index: Arbitrary device index for use by controller
	154	* @dev_id: Arbitrary device ID for use by controller
	155	* @buswidth: Bus width in bits (8 or 4)
	156	* @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
	157	* @mmc: Pointer to generic MMC structure for this device
	158	* @priv: Private pointer for use by controller
	159	*/
757bff49	160	struct dwmci_host {
6dc71410	161	const char *name;
757bff49 JC	162	void *ioaddr;
	163	unsigned int quirks;
	164	unsigned int caps;
	165	unsigned int version;
	166	unsigned int clock;
	167	unsigned int bus_hz;
959198f7	168	unsigned int div;
757bff49	169	int dev_index;
959198f7	170	int dev_id;
757bff49 JC	171	int buswidth;
	172	u32 fifoth_val;
	173	struct mmc *mmc;
5dab81ce	174	void *priv;
757bff49 JC	175
757bff49 JC	176	void (clksel)(struct dwmci_host host);
18ab6755	177	void (board_init)(struct dwmci_host host);
e3563f2e SG	178
	179	/**
	180	* Get / set a particular MMC clock frequency
	181	*
	182	* This is used to request the current clock frequency of the clock
	183	* that drives the DWMMC peripheral. The caller will then use this
	184	* information to work out the divider it needs to achieve the
	185	* required MMC bus clock frequency. If you want to handle the
	186	* clock external to DWMMC, use @freq to select the frequency and
	187	* return that value too. Then DWMMC will put itself in bypass mode.
	188	*
	189	* @host: DWMMC host
	190	* @freq: Frequency the host is trying to achieve
	191	*/
	192	unsigned int (get_mmc_clk)(struct dwmci_host host, uint freq);
5e6ff810	193	#ifndef CONFIG_BLK
93bfd616	194	struct mmc_config cfg;
5e6ff810	195	#endif
a65f51b9	196
	197	/* use fifo mode to read and write data */
	198	bool fifo_mode;
757bff49 JC	199	};
	200
	201	struct dwmci_idmac {
	202	u32 flags;
	203	u32 cnt;
	204	u32 addr;
	205	u32 next_addr;
1bf29b3d	206	} __aligned(ARCH_DMA_MINALIGN);
757bff49 JC	207
	208	static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
	209	{
	210	writel(val, host->ioaddr + reg);
	211	}
	212
	213	static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
	214	{
	215	writew(val, host->ioaddr + reg);
	216	}
	217
	218	static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
	219	{
	220	writeb(val, host->ioaddr + reg);
	221	}
	222	static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
	223	{
	224	return readl(host->ioaddr + reg);
	225	}
	226
	227	static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
	228	{
	229	return readw(host->ioaddr + reg);
	230	}
	231
	232	static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
	233	{
	234	return readb(host->ioaddr + reg);
	235	}
	236
e7a773a0 SG	237	#ifdef CONFIG_BLK
	238	/**
	239	* dwmci_setup_cfg() - Set up the configuration for DWMMC
	240	*
	241	* This is used to set up a DWMMC device when you are using CONFIG_BLK.
	242	*
	243	* This should be called from your MMC driver's probe() method once you have
	244	* the information required.
	245	*
	246	* Generally your driver will have a platform data structure which holds both
	247	* the configuration (struct mmc_config) and the MMC device info (struct mmc).
	248	* For example:
	249	*
	250	* struct rockchip_mmc_plat {
	251	* struct mmc_config cfg;
	252	* struct mmc mmc;
	253	* };
	254	*
	255	* ...
	256	*
	257	* Inside U_BOOT_DRIVER():
	258	* .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
	259	*
	260	* To access platform data:
	261	* struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
	262	*
	263	* See rockchip_dw_mmc.c for an example.
	264	*
	265	* @cfg: Configuration structure to fill in (generally &plat->mmc)
e5113c33	266	* @host: DWMMC host
dec0242b JC	267	* @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
dec0242b JC	268	* @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
e7a773a0	269	*/
e5113c33 JC	270	void dwmci_setup_cfg(struct mmc_config cfg, struct dwmci_host host,
e5113c33 JC	271	u32 max_clk, u32 min_clk);
e7a773a0 SG	272
	273	/**
	274	* dwmci_bind() - Set up a new MMC block device
	275	*
	276	* This is used to set up a DWMMC block device when you are using CONFIG_BLK.
	277	* It should be called from your driver's bind() method.
	278	*
	279	* See rockchip_dw_mmc.c for an example.
	280	*
	281	* @dev: Device to set up
	282	* @mmc: Pointer to mmc structure (normally &plat->mmc)
	283	* @cfg: Empty configuration structure (generally &plat->cfg). This is
	284	* normally all zeroes at this point. The only purpose of passing
	285	* this in is to set mmc->cfg to it.
	286	* @return 0 if OK, -ve if the block device could not be created
	287	*/
5e6ff810 SG	288	int dwmci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg);
5e6ff810 SG	289
e7a773a0 SG	290	#else
	291	/**
	292	* add_dwmci() - Add a new DWMMC interface
	293	*
	294	* This is used when you are not using CONFIG_BLK. Convert your driver over!
	295	*
	296	* @host: DWMMC host structure
dec0242b JC	297	* @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
dec0242b JC	298	* @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
e7a773a0 SG	299	* @return 0 if OK, -ve on error
e7a773a0 SG	300	*/
757bff49	301	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
e7a773a0 SG	302	#endif /* !CONFIG_BLK */
e7a773a0 SG	303
e7881d85	304	#ifdef CONFIG_DM_MMC
691272fe	305	/* Export the operations to drivers */
691272fe SG	306	int dwmci_probe(struct udevice *dev);
	307	extern const struct dm_mmc_ops dm_dwmci_ops;
	308	#endif
	309
757bff49	310	#endif /* __DWMMC_HW_H */