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common: Drop net.h from common header
[J-u-boot.git] / drivers / net / mtk_eth.c
CommitLineData
23f17164
WG		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 *
5 * Author: Weijie Gao <[email protected]>
6 * Author: Mark Lee <[email protected]>
7 */
8
9#include <common.h>
1eb69ae4 10#include <cpu_func.h>
23f17164
WG		 11#include <dm.h>
12#include <malloc.h>
13#include <miiphy.h>
90526e9f 14#include <net.h>
23f17164
WG		 15#include <regmap.h>
16#include <reset.h>
17#include <syscon.h>
18#include <wait_bit.h>
90526e9f 19#include <asm/cache.h>
23f17164
WG		 20#include <asm/gpio.h>
21#include <asm/io.h>
336d4615 22#include <dm/device_compat.h>
23f17164
WG		 23#include <linux/err.h>
24#include <linux/ioport.h>
25#include <linux/mdio.h>
26#include <linux/mii.h>
27
28#include "mtk_eth.h"
29
30#define NUM_TX_DESC 24
31#define NUM_RX_DESC 24
32#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
33#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
34#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
35
532de8d9
LC		 36#define MT753X_NUM_PHYS 5
37#define MT753X_NUM_PORTS 7
38#define MT753X_DFL_SMI_ADDR 31
39#define MT753X_SMI_ADDR_MASK 0x1f
23f17164 40
532de8d9 41#define MT753X_PHY_ADDR(base, addr) \
23f17164
WG		 42 (((base) + (addr)) & 0x1f)
43
44#define GDMA_FWD_TO_CPU \
45 (0x20000000 | \
46 GDM_ICS_EN | \
47 GDM_TCS_EN | \
48 GDM_UCS_EN | \
49 STRP_CRC | \
50 (DP_PDMA << MYMAC_DP_S) | \
51 (DP_PDMA << BC_DP_S) | \
52 (DP_PDMA << MC_DP_S) | \
53 (DP_PDMA << UN_DP_S))
54
55#define GDMA_FWD_DISCARD \
56 (0x20000000 | \
57 GDM_ICS_EN | \
58 GDM_TCS_EN | \
59 GDM_UCS_EN | \
60 STRP_CRC | \
61 (DP_DISCARD << MYMAC_DP_S) | \
62 (DP_DISCARD << BC_DP_S) | \
63 (DP_DISCARD << MC_DP_S) | \
64 (DP_DISCARD << UN_DP_S))
65
66struct pdma_rxd_info1 {
67 u32 PDP0;
68};
69
70struct pdma_rxd_info2 {
71 u32 PLEN1 : 14;
72 u32 LS1 : 1;
73 u32 UN_USED : 1;
74 u32 PLEN0 : 14;
75 u32 LS0 : 1;
76 u32 DDONE : 1;
77};
78
79struct pdma_rxd_info3 {
80 u32 PDP1;
81};
82
83struct pdma_rxd_info4 {
84 u32 FOE_ENTRY : 14;
85 u32 CRSN : 5;
86 u32 SP : 3;
87 u32 L4F : 1;
88 u32 L4VLD : 1;
89 u32 TACK : 1;
90 u32 IP4F : 1;
91 u32 IP4 : 1;
92 u32 IP6 : 1;
93 u32 UN_USED : 4;
94};
95
96struct pdma_rxdesc {
97 struct pdma_rxd_info1 rxd_info1;
98 struct pdma_rxd_info2 rxd_info2;
99 struct pdma_rxd_info3 rxd_info3;
100 struct pdma_rxd_info4 rxd_info4;
101};
102
103struct pdma_txd_info1 {
104 u32 SDP0;
105};
106
107struct pdma_txd_info2 {
108 u32 SDL1 : 14;
109 u32 LS1 : 1;
110 u32 BURST : 1;
111 u32 SDL0 : 14;
112 u32 LS0 : 1;
113 u32 DDONE : 1;
114};
115
116struct pdma_txd_info3 {
117 u32 SDP1;
118};
119
120struct pdma_txd_info4 {
121 u32 VLAN_TAG : 16;
122 u32 INS : 1;
123 u32 RESV : 2;
124 u32 UDF : 6;
125 u32 FPORT : 3;
126 u32 TSO : 1;
127 u32 TUI_CO : 3;
128};
129
130struct pdma_txdesc {
131 struct pdma_txd_info1 txd_info1;
132 struct pdma_txd_info2 txd_info2;
133 struct pdma_txd_info3 txd_info3;
134 struct pdma_txd_info4 txd_info4;
135};
136
137enum mtk_switch {
138 SW_NONE,
532de8d9
LC		 139 SW_MT7530,
140 SW_MT7531
23f17164
WG		 141};
142
143enum mtk_soc {
144 SOC_MT7623,
e395717c
M		 145 SOC_MT7629,
146 SOC_MT7622
23f17164
WG		 147};
148
149struct mtk_eth_priv {
150 char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
151
152 struct pdma_txdesc *tx_ring_noc;
153 struct pdma_rxdesc *rx_ring_noc;
154
155 int rx_dma_owner_idx0;
156 int tx_cpu_owner_idx0;
157
158 void __iomem *fe_base;
159 void __iomem *gmac_base;
160 void __iomem *ethsys_base;
b4ef49a9 161 void __iomem *sgmii_base;
23f17164
WG		 162
163 struct mii_dev *mdio_bus;
164 int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
165 int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
166 int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
167 int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
168 u16 val);
169
170 enum mtk_soc soc;
171 int gmac_id;
172 int force_mode;
173 int speed;
174 int duplex;
175
176 struct phy_device *phydev;
177 int phy_interface;
178 int phy_addr;
179
180 enum mtk_switch sw;
181 int (*switch_init)(struct mtk_eth_priv *priv);
532de8d9
LC		 182 u32 mt753x_smi_addr;
183 u32 mt753x_phy_base;
23f17164
WG		 184
185 struct gpio_desc rst_gpio;
186 int mcm;
187
188 struct reset_ctl rst_fe;
189 struct reset_ctl rst_mcm;
190};
191
192static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
193{
194 writel(val, priv->fe_base + PDMA_BASE + reg);
195}
196
197static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
198 u32 set)
199{
200 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
201}
202
203static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
204 u32 val)
205{
206 u32 gdma_base;
207
208 if (no == 1)
209 gdma_base = GDMA2_BASE;
210 else
211 gdma_base = GDMA1_BASE;
212
213 writel(val, priv->fe_base + gdma_base + reg);
214}
215
216static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
217{
218 return readl(priv->gmac_base + reg);
219}
220
221static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
222{
223 writel(val, priv->gmac_base + reg);
224}
225
226static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
227{
228 clrsetbits_le32(priv->gmac_base + reg, clr, set);
229}
230
231static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
232 u32 set)
233{
234 clrsetbits_le32(priv->ethsys_base + reg, clr, set);
235}
236
237/* Direct MDIO clause 22/45 access via SoC */
238static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
239 u32 cmd, u32 st)
240{
241 int ret;
242 u32 val;
243
244 val = (st << MDIO_ST_S) |
245 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
246 (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
247 (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
248
249 if (cmd == MDIO_CMD_WRITE)
250 val |= data & MDIO_RW_DATA_M;
251
252 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
253
254 ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
255 PHY_ACS_ST, 0, 5000, 0);
256 if (ret) {
257 pr_warn("MDIO access timeout\n");
258 return ret;
259 }
260
261 if (cmd == MDIO_CMD_READ) {
262 val = mtk_gmac_read(priv, GMAC_PIAC_REG);
263 return val & MDIO_RW_DATA_M;
264 }
265
266 return 0;
267}
268
269/* Direct MDIO clause 22 read via SoC */
270static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
271{
272 return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
273}
274
275/* Direct MDIO clause 22 write via SoC */
276static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
277{
278 return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
279}
280
281/* Direct MDIO clause 45 read via SoC */
282static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
283{
284 int ret;
285
286 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
287 if (ret)
288 return ret;
289
290 return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
291 MDIO_ST_C45);
292}
293
294/* Direct MDIO clause 45 write via SoC */
295static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
296 u16 reg, u16 val)
297{
298 int ret;
299
300 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
301 if (ret)
302 return ret;
303
304 return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
305 MDIO_ST_C45);
306}
307
308/* Indirect MDIO clause 45 read via MII registers */
309static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
310 u16 reg)
311{
312 int ret;
313
314 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
315 (MMD_ADDR << MMD_CMD_S) |
316 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
317 if (ret)
318 return ret;
319
320 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
321 if (ret)
322 return ret;
323
324 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
325 (MMD_DATA << MMD_CMD_S) |
326 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
327 if (ret)
328 return ret;
329
330 return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
331}
332
333/* Indirect MDIO clause 45 write via MII registers */
334static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
335 u16 reg, u16 val)
336{
337 int ret;
338
339 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
340 (MMD_ADDR << MMD_CMD_S) |
341 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
342 if (ret)
343 return ret;
344
345 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
346 if (ret)
347 return ret;
348
349 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
350 (MMD_DATA << MMD_CMD_S) |
351 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
352 if (ret)
353 return ret;
354
355 return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
356}
357
532de8d9
LC		 358/*
359 * MT7530 Internal Register Address Bits
360 * -------------------------------------------------------------------
361 * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
362 * |----------------------------------------|---------------|--------|
363 * | Page Address | Reg Address | Unused |
364 * -------------------------------------------------------------------
365 */
366
367static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
368{
369 int ret, low_word, high_word;
370
371 /* Write page address */
372 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
373 if (ret)
374 return ret;
375
376 /* Read low word */
377 low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf);
378 if (low_word < 0)
379 return low_word;
380
381 /* Read high word */
382 high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10);
383 if (high_word < 0)
384 return high_word;
385
386 if (data)
387 *data = ((u32)high_word << 16) | (low_word & 0xffff);
388
389 return 0;
390}
391
392static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
393{
394 int ret;
395
396 /* Write page address */
397 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
398 if (ret)
399 return ret;
400
401 /* Write low word */
402 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf,
403 data & 0xffff);
404 if (ret)
405 return ret;
406
407 /* Write high word */
408 return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16);
409}
410
411static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
412 u32 set)
413{
414 u32 val;
415
416 mt753x_reg_read(priv, reg, &val);
417 val &= ~clr;
418 val |= set;
419 mt753x_reg_write(priv, reg, val);
420}
421
422/* Indirect MDIO clause 22/45 access */
423static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data,
424 u32 cmd, u32 st)
425{
426 ulong timeout;
427 u32 val, timeout_ms;
428 int ret = 0;
429
430 val = (st << MDIO_ST_S) |
431 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
432 ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
433 ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
434
435 if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
436 val |= data & MDIO_RW_DATA_M;
437
438 mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
439
440 timeout_ms = 100;
441 timeout = get_timer(0);
442 while (1) {
443 mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
444
445 if ((val & PHY_ACS_ST) == 0)
446 break;
447
448 if (get_timer(timeout) > timeout_ms)
449 return -ETIMEDOUT;
450 }
451
452 if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
453 mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
454 ret = val & MDIO_RW_DATA_M;
455 }
456
457 return ret;
458}
459
460static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
461{
462 u8 phy_addr;
463
464 if (phy >= MT753X_NUM_PHYS)
465 return -EINVAL;
466
467 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
468
469 return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
470 MDIO_ST_C22);
471}
472
473static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
474 u16 val)
475{
476 u8 phy_addr;
477
478 if (phy >= MT753X_NUM_PHYS)
479 return -EINVAL;
480
481 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
482
483 return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
484 MDIO_ST_C22);
485}
486
487int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
488{
489 u8 phy_addr;
490 int ret;
491
492 if (addr >= MT753X_NUM_PHYS)
493 return -EINVAL;
494
495 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
496
497 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
498 MDIO_ST_C45);
499 if (ret)
500 return ret;
501
502 return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
503 MDIO_ST_C45);
504}
505
506static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
507 u16 reg, u16 val)
508{
509 u8 phy_addr;
510 int ret;
511
512 if (addr >= MT753X_NUM_PHYS)
513 return 0;
514
515 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
516
517 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
518 MDIO_ST_C45);
519 if (ret)
520 return ret;
521
522 return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
523 MDIO_ST_C45);
524}
525
23f17164
WG		 526static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
527{
528 struct mtk_eth_priv *priv = bus->priv;
529
530 if (devad < 0)
531 return priv->mii_read(priv, addr, reg);
532 else
533 return priv->mmd_read(priv, addr, devad, reg);
534}
535
536static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
537 u16 val)
538{
539 struct mtk_eth_priv *priv = bus->priv;
540
541 if (devad < 0)
542 return priv->mii_write(priv, addr, reg, val);
543 else
544 return priv->mmd_write(priv, addr, devad, reg, val);
545}
546
547static int mtk_mdio_register(struct udevice *dev)
548{
549 struct mtk_eth_priv *priv = dev_get_priv(dev);
550 struct mii_dev *mdio_bus = mdio_alloc();
551 int ret;
552
553 if (!mdio_bus)
554 return -ENOMEM;
555
556 /* Assign MDIO access APIs according to the switch/phy */
557 switch (priv->sw) {
558 case SW_MT7530:
559 priv->mii_read = mtk_mii_read;
560 priv->mii_write = mtk_mii_write;
561 priv->mmd_read = mtk_mmd_ind_read;
562 priv->mmd_write = mtk_mmd_ind_write;
563 break;
532de8d9
LC		 564 case SW_MT7531:
565 priv->mii_read = mt7531_mii_ind_read;
566 priv->mii_write = mt7531_mii_ind_write;
567 priv->mmd_read = mt7531_mmd_ind_read;
568 priv->mmd_write = mt7531_mmd_ind_write;
569 break;
23f17164
WG		 570 default:
571 priv->mii_read = mtk_mii_read;
572 priv->mii_write = mtk_mii_write;
573 priv->mmd_read = mtk_mmd_read;
574 priv->mmd_write = mtk_mmd_write;
575 }
576
577 mdio_bus->read = mtk_mdio_read;
578 mdio_bus->write = mtk_mdio_write;
579 snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
580
581 mdio_bus->priv = (void *)priv;
582
583 ret = mdio_register(mdio_bus);
584
585 if (ret)
586 return ret;
587
588 priv->mdio_bus = mdio_bus;
589
590 return 0;
591}
592
532de8d9 593static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg)
23f17164 594{
532de8d9 595 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
23f17164 596
532de8d9 597 return priv->mmd_read(priv, phy_addr, 0x1f, reg);
23f17164
WG		 598}
599
532de8d9 600static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
23f17164 601{
532de8d9 602 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
23f17164 603
532de8d9 604 priv->mmd_write(priv, phy_addr, 0x1f, reg, val);
23f17164
WG		 605}
606
607static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
608{
609 u32 ncpo1, ssc_delta;
610
611 switch (mode) {
612 case PHY_INTERFACE_MODE_RGMII:
613 ncpo1 = 0x0c80;
614 ssc_delta = 0x87;
615 break;
616 default:
617 printf("error: xMII mode %d not supported\n", mode);
618 return -EINVAL;
619 }
620
621 /* Disable MT7530 core clock */
532de8d9 622 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
23f17164
WG		 623
624 /* Disable MT7530 PLL */
532de8d9 625 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
23f17164
WG		 626 (2 << RG_GSWPLL_POSDIV_200M_S) |
627 (32 << RG_GSWPLL_FBKDIV_200M_S));
628
629 /* For MT7530 core clock = 500Mhz */
532de8d9 630 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2,
23f17164
WG		 631 (1 << RG_GSWPLL_POSDIV_500M_S) |
632 (25 << RG_GSWPLL_FBKDIV_500M_S));
633
634 /* Enable MT7530 PLL */
532de8d9 635 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
23f17164
WG		 636 (2 << RG_GSWPLL_POSDIV_200M_S) |
637 (32 << RG_GSWPLL_FBKDIV_200M_S) |
638 RG_GSWPLL_EN_PRE);
639
640 udelay(20);
641
532de8d9 642 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
23f17164
WG		 643
644 /* Setup the MT7530 TRGMII Tx Clock */
532de8d9
LC		 645 mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
646 mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0);
647 mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
648 mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
649 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
23f17164
WG		 650 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
651
532de8d9 652 mt753x_core_reg_write(priv, CORE_PLL_GROUP2,
23f17164
WG		 653 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
654 (1 << RG_SYSPLL_POSDIV_S));
655
532de8d9 656 mt753x_core_reg_write(priv, CORE_PLL_GROUP7,
23f17164
WG		 657 RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
658 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
659
660 /* Enable MT7530 core clock */
532de8d9 661 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
23f17164
WG		 662 REG_GSWCK_EN | REG_TRGMIICK_EN);
663
664 return 0;
665}
666
667static int mt7530_setup(struct mtk_eth_priv *priv)
668{
669 u16 phy_addr, phy_val;
670 u32 val;
671 int i;
672
673 /* Select 250MHz clk for RGMII mode */
674 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
675 ETHSYS_TRGMII_CLK_SEL362_5, 0);
676
23f17164 677 /* Modify HWTRAP first to allow direct access to internal PHYs */
532de8d9 678 mt753x_reg_read(priv, HWTRAP_REG, &val);
23f17164
WG		 679 val |= CHG_TRAP;
680 val &= ~C_MDIO_BPS;
532de8d9 681 mt753x_reg_write(priv, MHWTRAP_REG, val);
23f17164
WG		 682
683 /* Calculate the phy base address */
684 val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
532de8d9 685 priv->mt753x_phy_base = (val | 0x7) + 1;
23f17164
WG		 686
687 /* Turn off PHYs */
532de8d9
LC		 688 for (i = 0; i < MT753X_NUM_PHYS; i++) {
689 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
23f17164
WG		 690 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
691 phy_val |= BMCR_PDOWN;
692 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
693 }
694
695 /* Force MAC link down before reset */
532de8d9
LC		 696 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
697 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
23f17164
WG		 698
699 /* MT7530 reset */
532de8d9 700 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
23f17164
WG		 701 udelay(100);
702
532de8d9 703 val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
23f17164
WG		 704 MAC_MODE | FORCE_MODE |
705 MAC_TX_EN | MAC_RX_EN |
706 BKOFF_EN | BACKPR_EN |
707 (SPEED_1000M << FORCE_SPD_S) |
708 FORCE_DPX | FORCE_LINK;
709
710 /* MT7530 Port6: Forced 1000M/FD, FC disabled */
532de8d9 711 mt753x_reg_write(priv, PMCR_REG(6), val);
23f17164
WG		 712
713 /* MT7530 Port5: Forced link down */
532de8d9 714 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
23f17164
WG		 715
716 /* MT7530 Port6: Set to RGMII */
532de8d9 717 mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
23f17164
WG		 718
719 /* Hardware Trap: Enable Port6, Disable Port5 */
532de8d9 720 mt753x_reg_read(priv, HWTRAP_REG, &val);
23f17164
WG		 721 val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
722 (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
723 (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
724 val &= ~(C_MDIO_BPS | P6_INTF_DIS);
532de8d9 725 mt753x_reg_write(priv, MHWTRAP_REG, val);
23f17164
WG		 726
727 /* Setup switch core pll */
728 mt7530_pad_clk_setup(priv, priv->phy_interface);
729
730 /* Lower Tx Driving for TRGMII path */
731 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
532de8d9 732 mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
23f17164
WG		 733 (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
734
735 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
532de8d9
LC		 736 mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
737
738 /* Turn on PHYs */
739 for (i = 0; i < MT753X_NUM_PHYS; i++) {
740 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
741 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
742 phy_val &= ~BMCR_PDOWN;
743 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
744 }
745
746 return 0;
747}
748
749static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm)
750{
751 /* Step 1 : Disable MT7531 COREPLL */
752 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
753
754 /* Step 2: switch to XTAL output */
755 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
756
757 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
758
759 /* Step 3: disable PLLGP and enable program PLLGP */
760 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
761
762 /* Step 4: program COREPLL output frequency to 500MHz */
763 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
764 2 << RG_COREPLL_POSDIV_S);
765 udelay(25);
766
767 /* Currently, support XTAL 25Mhz only */
768 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
769 0x140000 << RG_COREPLL_SDM_PCW_S);
770
771 /* Set feedback divide ratio update signal to high */
772 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
773 RG_COREPLL_SDM_PCW_CHG);
774
775 /* Wait for at least 16 XTAL clocks */
776 udelay(10);
777
778 /* Step 5: set feedback divide ratio update signal to low */
779 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
780
781 /* add enable 325M clock for SGMII */
782 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
783
784 /* add enable 250SSC clock for RGMII */
785 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
786
787 /*Step 6: Enable MT7531 PLL */
788 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
789
790 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
791
792 udelay(25);
793}
794
795static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv,
796 u32 port)
797{
798 if (port != 5 && port != 6) {
799 printf("mt7531: port %d is not a SGMII port\n", port);
800 return -EINVAL;
801 }
802
803 /* Set SGMII GEN2 speed(2.5G) */
804 mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
805 SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
806
807 /* Disable SGMII AN */
808 mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
809 SGMII_AN_ENABLE, 0);
810
811 /* SGMII force mode setting */
812 mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
813
814 /* Release PHYA power down state */
815 mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
816 SGMII_PHYA_PWD, 0);
817
818 return 0;
819}
820
821static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port)
822{
823 u32 val;
824
825 if (port != 5) {
826 printf("error: RGMII mode is not available for port %d\n",
827 port);
828 return -EINVAL;
829 }
830
831 mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
832 val |= GP_CLK_EN;
833 val &= ~GP_MODE_M;
834 val |= GP_MODE_RGMII << GP_MODE_S;
835 val |= TXCLK_NO_REVERSE;
836 val |= RXCLK_NO_DELAY;
837 val &= ~CLK_SKEW_IN_M;
838 val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
839 val &= ~CLK_SKEW_OUT_M;
840 val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
841 mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
842
843 return 0;
844}
845
846static void mt7531_phy_setting(struct mtk_eth_priv *priv)
847{
848 int i;
849 u32 val;
850
851 for (i = 0; i < MT753X_NUM_PHYS; i++) {
852 /* Enable HW auto downshift */
853 priv->mii_write(priv, i, 0x1f, 0x1);
854 val = priv->mii_read(priv, i, PHY_EXT_REG_14);
855 val |= PHY_EN_DOWN_SHFIT;
856 priv->mii_write(priv, i, PHY_EXT_REG_14, val);
857
858 /* PHY link down power saving enable */
859 val = priv->mii_read(priv, i, PHY_EXT_REG_17);
860 val |= PHY_LINKDOWN_POWER_SAVING_EN;
861 priv->mii_write(priv, i, PHY_EXT_REG_17, val);
862
863 val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
864 val &= ~PHY_POWER_SAVING_M;
865 val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
866 priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
867 }
868}
869
870static int mt7531_setup(struct mtk_eth_priv *priv)
871{
872 u16 phy_addr, phy_val;
873 u32 val;
874 u32 pmcr;
875 u32 port5_sgmii;
876 int i;
877
878 priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
879 MT753X_SMI_ADDR_MASK;
880
881 /* Turn off PHYs */
882 for (i = 0; i < MT753X_NUM_PHYS; i++) {
883 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
884 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
885 phy_val |= BMCR_PDOWN;
886 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
887 }
888
889 /* Force MAC link down before reset */
890 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
891 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
892
893 /* Switch soft reset */
894 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
895 udelay(100);
896
897 /* Enable MDC input Schmitt Trigger */
898 mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
899 SMT_IOLB_5_SMI_MDC_EN);
900
901 mt7531_core_pll_setup(priv, priv->mcm);
902
903 mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
904 port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
905
906 /* port5 support either RGMII or SGMII, port6 only support SGMII. */
907 switch (priv->phy_interface) {
908 case PHY_INTERFACE_MODE_RGMII:
909 if (!port5_sgmii)
910 mt7531_port_rgmii_init(priv, 5);
911 break;
912 case PHY_INTERFACE_MODE_SGMII:
913 mt7531_port_sgmii_init(priv, 6);
914 if (port5_sgmii)
915 mt7531_port_sgmii_init(priv, 5);
916 break;
917 default:
918 break;
919 }
920
921 pmcr = MT7531_FORCE_MODE |
922 (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
923 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
924 BKOFF_EN | BACKPR_EN |
925 FORCE_RX_FC | FORCE_TX_FC |
926 (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
927 FORCE_LINK;
928
929 mt753x_reg_write(priv, PMCR_REG(5), pmcr);
930 mt753x_reg_write(priv, PMCR_REG(6), pmcr);
23f17164
WG		 931
932 /* Turn on PHYs */
532de8d9
LC		 933 for (i = 0; i < MT753X_NUM_PHYS; i++) {
934 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
23f17164
WG		 935 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
936 phy_val &= ~BMCR_PDOWN;
937 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
938 }
939
532de8d9
LC		 940 mt7531_phy_setting(priv);
941
942 /* Enable Internal PHYs */
943 val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4);
944 val |= MT7531_BYPASS_MODE;
945 val &= ~MT7531_POWER_ON_OFF;
946 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val);
947
948 return 0;
949}
950
951int mt753x_switch_init(struct mtk_eth_priv *priv)
952{
953 int ret;
954 int i;
955
956 /* Global reset switch */
957 if (priv->mcm) {
958 reset_assert(&priv->rst_mcm);
959 udelay(1000);
960 reset_deassert(&priv->rst_mcm);
961 mdelay(1000);
962 } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
963 dm_gpio_set_value(&priv->rst_gpio, 0);
964 udelay(1000);
965 dm_gpio_set_value(&priv->rst_gpio, 1);
966 mdelay(1000);
967 }
968
969 ret = priv->switch_init(priv);
970 if (ret)
971 return ret;
972
23f17164 973 /* Set port isolation */
532de8d9 974 for (i = 0; i < MT753X_NUM_PORTS; i++) {
23f17164
WG		 975 /* Set port matrix mode */
976 if (i != 6)
532de8d9 977 mt753x_reg_write(priv, PCR_REG(i),
23f17164
WG		 978 (0x40 << PORT_MATRIX_S));
979 else
532de8d9 980 mt753x_reg_write(priv, PCR_REG(i),
23f17164
WG		 981 (0x3f << PORT_MATRIX_S));
982
983 /* Set port mode to user port */
532de8d9 984 mt753x_reg_write(priv, PVC_REG(i),
23f17164
WG		 985 (0x8100 << STAG_VPID_S) |
986 (VLAN_ATTR_USER << VLAN_ATTR_S));
987 }
988
989 return 0;
990}
991
992static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
993{
994 u16 lcl_adv = 0, rmt_adv = 0;
995 u8 flowctrl;
996 u32 mcr;
997
532de8d9 998 mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
23f17164
WG		 999 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
1000 MAC_MODE | FORCE_MODE |
1001 MAC_TX_EN | MAC_RX_EN |
1002 BKOFF_EN | BACKPR_EN;
1003
1004 switch (priv->phydev->speed) {
1005 case SPEED_10:
1006 mcr |= (SPEED_10M << FORCE_SPD_S);
1007 break;
1008 case SPEED_100:
1009 mcr |= (SPEED_100M << FORCE_SPD_S);
1010 break;
1011 case SPEED_1000:
1012 mcr |= (SPEED_1000M << FORCE_SPD_S);
1013 break;
1014 };
1015
1016 if (priv->phydev->link)
1017 mcr |= FORCE_LINK;
1018
1019 if (priv->phydev->duplex) {
1020 mcr |= FORCE_DPX;
1021
1022 if (priv->phydev->pause)
1023 rmt_adv = LPA_PAUSE_CAP;
1024 if (priv->phydev->asym_pause)
1025 rmt_adv |= LPA_PAUSE_ASYM;
1026
1027 if (priv->phydev->advertising & ADVERTISED_Pause)
1028 lcl_adv |= ADVERTISE_PAUSE_CAP;
1029 if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
1030 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1031
1032 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1033
1034 if (flowctrl & FLOW_CTRL_TX)
1035 mcr |= FORCE_TX_FC;
1036 if (flowctrl & FLOW_CTRL_RX)
1037 mcr |= FORCE_RX_FC;
1038
1039 debug("rx pause %s, tx pause %s\n",
1040 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
1041 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
1042 }
1043
1044 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
1045}
1046
1047static int mtk_phy_start(struct mtk_eth_priv *priv)
1048{
1049 struct phy_device *phydev = priv->phydev;
1050 int ret;
1051
1052 ret = phy_startup(phydev);
1053
1054 if (ret) {
1055 debug("Could not initialize PHY %s\n", phydev->dev->name);
1056 return ret;
1057 }
1058
1059 if (!phydev->link) {
1060 debug("%s: link down.\n", phydev->dev->name);
1061 return 0;
1062 }
1063
1064 mtk_phy_link_adjust(priv);
1065
1066 debug("Speed: %d, %s duplex%s\n", phydev->speed,
1067 (phydev->duplex) ? "full" : "half",
1068 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
1069
1070 return 0;
1071}
1072
1073static int mtk_phy_probe(struct udevice *dev)
1074{
1075 struct mtk_eth_priv *priv = dev_get_priv(dev);
1076 struct phy_device *phydev;
1077
1078 phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
1079 priv->phy_interface);
1080 if (!phydev)
1081 return -ENODEV;
1082
1083 phydev->supported &= PHY_GBIT_FEATURES;
1084 phydev->advertising = phydev->supported;
1085
1086 priv->phydev = phydev;
1087 phy_config(phydev);
1088
1089 return 0;
1090}
1091
b4ef49a9
M		 1092static void mtk_sgmii_init(struct mtk_eth_priv *priv)
1093{
1094 /* Set SGMII GEN2 speed(2.5G) */
1095 clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
1096 SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
1097
1098 /* Disable SGMII AN */
1099 clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
1100 SGMII_AN_ENABLE, 0);
1101
1102 /* SGMII force mode setting */
1103 writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
1104
1105 /* Release PHYA power down state */
1106 clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
1107 SGMII_PHYA_PWD, 0);
1108}
1109
23f17164
WG		 1110static void mtk_mac_init(struct mtk_eth_priv *priv)
1111{
1112 int i, ge_mode = 0;
1113 u32 mcr;
1114
1115 switch (priv->phy_interface) {
1116 case PHY_INTERFACE_MODE_RGMII_RXID:
1117 case PHY_INTERFACE_MODE_RGMII:
b4ef49a9
M		 1118 ge_mode = GE_MODE_RGMII;
1119 break;
23f17164
WG		 1120 case PHY_INTERFACE_MODE_SGMII:
1121 ge_mode = GE_MODE_RGMII;
b4ef49a9
M		 1122 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
1123 SYSCFG0_SGMII_SEL(priv->gmac_id));
1124 mtk_sgmii_init(priv);
23f17164
WG		 1125 break;
1126 case PHY_INTERFACE_MODE_MII:
1127 case PHY_INTERFACE_MODE_GMII:
1128 ge_mode = GE_MODE_MII;
1129 break;
1130 case PHY_INTERFACE_MODE_RMII:
1131 ge_mode = GE_MODE_RMII;
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 /* set the gmac to the right mode */
1138 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
1139 SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
1140 ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
1141
1142 if (priv->force_mode) {
532de8d9 1143 mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
23f17164
WG		 1144 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
1145 MAC_MODE | FORCE_MODE |
1146 MAC_TX_EN | MAC_RX_EN |
1147 BKOFF_EN | BACKPR_EN |
1148 FORCE_LINK;
1149
1150 switch (priv->speed) {
1151 case SPEED_10:
1152 mcr |= SPEED_10M << FORCE_SPD_S;
1153 break;
1154 case SPEED_100:
1155 mcr |= SPEED_100M << FORCE_SPD_S;
1156 break;
1157 case SPEED_1000:
1158 mcr |= SPEED_1000M << FORCE_SPD_S;
1159 break;
1160 }
1161
1162 if (priv->duplex)
1163 mcr |= FORCE_DPX;
1164
1165 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
1166 }
1167
1168 if (priv->soc == SOC_MT7623) {
1169 /* Lower Tx Driving for TRGMII path */
1170 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
1171 mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
1172 (8 << TD_DM_DRVP_S) |
1173 (8 << TD_DM_DRVN_S));
1174
1175 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
1176 RX_RST | RXC_DQSISEL);
1177 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
1178 }
1179}
1180
1181static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
1182{
1183 char *pkt_base = priv->pkt_pool;
1184 int i;
1185
1186 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
1187 udelay(500);
1188
1189 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
1190 memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
1191 memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
1192
47b1431d
FW		 1193 flush_dcache_range((ulong)pkt_base,
1194 (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
23f17164
WG		 1195
1196 priv->rx_dma_owner_idx0 = 0;
1197 priv->tx_cpu_owner_idx0 = 0;
1198
1199 for (i = 0; i < NUM_TX_DESC; i++) {
1200 priv->tx_ring_noc[i].txd_info2.LS0 = 1;
1201 priv->tx_ring_noc[i].txd_info2.DDONE = 1;
1202 priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
1203
1204 priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
1205 pkt_base += PKTSIZE_ALIGN;
1206 }
1207
1208 for (i = 0; i < NUM_RX_DESC; i++) {
1209 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
1210 priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
1211 pkt_base += PKTSIZE_ALIGN;
1212 }
1213
1214 mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
1215 virt_to_phys(priv->tx_ring_noc));
1216 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
1217 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
1218
1219 mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
1220 virt_to_phys(priv->rx_ring_noc));
1221 mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
1222 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
1223
1224 mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
1225}
1226
1227static int mtk_eth_start(struct udevice *dev)
1228{
1229 struct mtk_eth_priv *priv = dev_get_priv(dev);
1230 int ret;
1231
1232 /* Reset FE */
1233 reset_assert(&priv->rst_fe);
1234 udelay(1000);
1235 reset_deassert(&priv->rst_fe);
1236 mdelay(10);
1237
1238 /* Packets forward to PDMA */
1239 mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
1240
1241 if (priv->gmac_id == 0)
1242 mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
1243 else
1244 mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
1245
1246 udelay(500);
1247
1248 mtk_eth_fifo_init(priv);
1249
1250 /* Start PHY */
1251 if (priv->sw == SW_NONE) {
1252 ret = mtk_phy_start(priv);
1253 if (ret)
1254 return ret;
1255 }
1256
1257 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
1258 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
1259 udelay(500);
1260
1261 return 0;
1262}
1263
1264static void mtk_eth_stop(struct udevice *dev)
1265{
1266 struct mtk_eth_priv *priv = dev_get_priv(dev);
1267
1268 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
1269 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
1270 udelay(500);
1271
1272 wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
1273 RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
1274}
1275
1276static int mtk_eth_write_hwaddr(struct udevice *dev)
1277{
1278 struct eth_pdata *pdata = dev_get_platdata(dev);
1279 struct mtk_eth_priv *priv = dev_get_priv(dev);
1280 unsigned char *mac = pdata->enetaddr;
1281 u32 macaddr_lsb, macaddr_msb;
1282
1283 macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
1284 macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
1285 ((u32)mac[4] << 8) | (u32)mac[5];
1286
1287 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
1288 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
1289
1290 return 0;
1291}
1292
1293static int mtk_eth_send(struct udevice *dev, void *packet, int length)
1294{
1295 struct mtk_eth_priv *priv = dev_get_priv(dev);
1296 u32 idx = priv->tx_cpu_owner_idx0;
1297 void *pkt_base;
1298
1299 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
1300 debug("mtk-eth: TX DMA descriptor ring is full\n");
1301 return -EPERM;
1302 }
1303
1304 pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
1305 memcpy(pkt_base, packet, length);
47b1431d 1306 flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
23f17164
WG		 1307 roundup(length, ARCH_DMA_MINALIGN));
1308
1309 priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
1310 priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
1311
1312 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
1313 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
1314
1315 return 0;
1316}
1317
1318static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1319{
1320 struct mtk_eth_priv *priv = dev_get_priv(dev);
1321 u32 idx = priv->rx_dma_owner_idx0;
1322 uchar *pkt_base;
1323 u32 length;
1324
1325 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
1326 debug("mtk-eth: RX DMA descriptor ring is empty\n");
1327 return -EAGAIN;
1328 }
1329
1330 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
1331 pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
47b1431d 1332 invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
23f17164
WG		 1333 roundup(length, ARCH_DMA_MINALIGN));
1334
1335 if (packetp)
1336 *packetp = pkt_base;
1337
1338 return length;
1339}
1340
1341static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
1342{
1343 struct mtk_eth_priv *priv = dev_get_priv(dev);
1344 u32 idx = priv->rx_dma_owner_idx0;
1345
1346 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
1347 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
1348 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
1349
1350 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
1351 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
1352
1353 return 0;
1354}
1355
1356static int mtk_eth_probe(struct udevice *dev)
1357{
1358 struct eth_pdata *pdata = dev_get_platdata(dev);
1359 struct mtk_eth_priv *priv = dev_get_priv(dev);
47b1431d 1360 ulong iobase = pdata->iobase;
23f17164
WG		 1361 int ret;
1362
1363 /* Frame Engine Register Base */
1364 priv->fe_base = (void *)iobase;
1365
1366 /* GMAC Register Base */
1367 priv->gmac_base = (void *)(iobase + GMAC_BASE);
1368
1369 /* MDIO register */
1370 ret = mtk_mdio_register(dev);
1371 if (ret)
1372 return ret;
1373
1374 /* Prepare for tx/rx rings */
1375 priv->tx_ring_noc = (struct pdma_txdesc *)
1376 noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
1377 ARCH_DMA_MINALIGN);
1378 priv->rx_ring_noc = (struct pdma_rxdesc *)
1379 noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
1380 ARCH_DMA_MINALIGN);
1381
1382 /* Set MAC mode */
1383 mtk_mac_init(priv);
1384
1385 /* Probe phy if switch is not specified */
1386 if (priv->sw == SW_NONE)
1387 return mtk_phy_probe(dev);
1388
1389 /* Initialize switch */
532de8d9 1390 return mt753x_switch_init(priv);
23f17164
WG		 1391}
1392
1393static int mtk_eth_remove(struct udevice *dev)
1394{
1395 struct mtk_eth_priv *priv = dev_get_priv(dev);
1396
1397 /* MDIO unregister */
1398 mdio_unregister(priv->mdio_bus);
1399 mdio_free(priv->mdio_bus);
1400
1401 /* Stop possibly started DMA */
1402 mtk_eth_stop(dev);
1403
1404 return 0;
1405}
1406
1407static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
1408{
1409 struct eth_pdata *pdata = dev_get_platdata(dev);
1410 struct mtk_eth_priv *priv = dev_get_priv(dev);
1411 struct ofnode_phandle_args args;
1412 struct regmap *regmap;
1413 const char *str;
1414 ofnode subnode;
1415 int ret;
1416
1417 priv->soc = dev_get_driver_data(dev);
1418
1419 pdata->iobase = devfdt_get_addr(dev);
1420
1421 /* get corresponding ethsys phandle */
1422 ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
1423 &args);
1424 if (ret)
1425 return ret;
1426
1427 regmap = syscon_node_to_regmap(args.node);
1428 if (IS_ERR(regmap))
1429 return PTR_ERR(regmap);
1430
1431 priv->ethsys_base = regmap_get_range(regmap, 0);
1432 if (!priv->ethsys_base) {
1433 dev_err(dev, "Unable to find ethsys\n");
1434 return -ENODEV;
1435 }
1436
1437 /* Reset controllers */
1438 ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
1439 if (ret) {
1440 printf("error: Unable to get reset ctrl for frame engine\n");
1441 return ret;
1442 }
1443
1444 priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
1445
1446 /* Interface mode is required */
1447 str = dev_read_string(dev, "phy-mode");
1448 if (str) {
1449 pdata->phy_interface = phy_get_interface_by_name(str);
1450 priv->phy_interface = pdata->phy_interface;
1451 } else {
1452 printf("error: phy-mode is not set\n");
1453 return -EINVAL;
1454 }
1455
1456 /* Force mode or autoneg */
1457 subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
1458 if (ofnode_valid(subnode)) {
1459 priv->force_mode = 1;
1460 priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
1461 priv->duplex = ofnode_read_bool(subnode, "full-duplex");
1462
1463 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
1464 priv->speed != SPEED_1000) {
1465 printf("error: no valid speed set in fixed-link\n");
1466 return -EINVAL;
1467 }
1468 }
1469
b4ef49a9
M		 1470 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1471 /* get corresponding sgmii phandle */
1472 ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
1473 NULL, 0, 0, &args);
1474 if (ret)
1475 return ret;
1476
1477 regmap = syscon_node_to_regmap(args.node);
1478
1479 if (IS_ERR(regmap))
1480 return PTR_ERR(regmap);
1481
1482 priv->sgmii_base = regmap_get_range(regmap, 0);
1483
1484 if (!priv->sgmii_base) {
1485 dev_err(dev, "Unable to find sgmii\n");
1486 return -ENODEV;
1487 }
1488 }
1489
23f17164
WG		 1490 /* check for switch first, otherwise phy will be used */
1491 priv->sw = SW_NONE;
1492 priv->switch_init = NULL;
1493 str = dev_read_string(dev, "mediatek,switch");
1494
1495 if (str) {
1496 if (!strcmp(str, "mt7530")) {
1497 priv->sw = SW_MT7530;
1498 priv->switch_init = mt7530_setup;
532de8d9
LC		 1499 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
1500 } else if (!strcmp(str, "mt7531")) {
1501 priv->sw = SW_MT7531;
1502 priv->switch_init = mt7531_setup;
1503 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
23f17164
WG		 1504 } else {
1505 printf("error: unsupported switch\n");
1506 return -EINVAL;
1507 }
1508
1509 priv->mcm = dev_read_bool(dev, "mediatek,mcm");
1510 if (priv->mcm) {
1511 ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
1512 if (ret) {
1513 printf("error: no reset ctrl for mcm\n");
1514 return ret;
1515 }
1516 } else {
1517 gpio_request_by_name(dev, "reset-gpios", 0,
1518 &priv->rst_gpio, GPIOD_IS_OUT);
1519 }
1520 } else {
ebb97ea8
WG		 1521 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
1522 0, &args);
1523 if (ret) {
23f17164
WG		 1524 printf("error: phy-handle is not specified\n");
1525 return ret;
1526 }
1527
ebb97ea8 1528 priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
23f17164
WG		 1529 if (priv->phy_addr < 0) {
1530 printf("error: phy address is not specified\n");
1531 return ret;
1532 }
1533 }
1534
1535 return 0;
1536}
1537
1538static const struct udevice_id mtk_eth_ids[] = {
1539 { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
1540 { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
e395717c 1541 { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
23f17164
WG		 1542 {}
1543};
1544
1545static const struct eth_ops mtk_eth_ops = {
1546 .start = mtk_eth_start,
1547 .stop = mtk_eth_stop,
1548 .send = mtk_eth_send,
1549 .recv = mtk_eth_recv,
1550 .free_pkt = mtk_eth_free_pkt,
1551 .write_hwaddr = mtk_eth_write_hwaddr,
1552};
1553
1554U_BOOT_DRIVER(mtk_eth) = {
1555 .name = "mtk-eth",
1556 .id = UCLASS_ETH,
1557 .of_match = mtk_eth_ids,
1558 .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
1559 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1560 .probe = mtk_eth_probe,
1561 .remove = mtk_eth_remove,
1562 .ops = &mtk_eth_ops,
1563 .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
1564 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1565};
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