[J-u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 */

#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
	PAD_CTL_ODE)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_SPEED_HIGH   |                                  \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)

#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)

#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)

#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)

#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
	struct udevice *dev;
	int ret, dev_id, rev_id;
	unsigned int reg;

	ret = pmic_get("pfuze3000", &dev);
	if (ret == -ENODEV)
		return 0;
	if (ret != 0)
		return ret;

	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);

	/* disable Low Power Mode during standby mode */
	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
	reg |= 0x1;
	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);

	/* SW1B step ramp up time from 2us to 4us/25mV */
	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);

	/* SW1B mode to APS/PFM */
	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);

	/* SW1B standby voltage set to 0.975V */
	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);

	return 0;
}
#endif

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};


static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FSL_QSPI
static int board_qspi_init(void)
{
	/* Set the clock */
	enable_qspi_clk(0);

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC2_BASE_ADDR, 0, 4},
};

int board_mmc_getcd(struct mmc *mmc)
{
	return 1;
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif

#ifdef CONFIG_USB_EHCI_MX6
#ifndef CONFIG_DM_USB

#define USB_OTHERREGS_OFFSET	0x800
#define UCTRL_PWR_POL		(1 << 9)

static iomux_v3_cfg_t const usb_otg_pads[] = {
	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};

/* At default the 3v3 enables the MIC2026 for VBUS power */
static void setup_usb(void)
{
	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
					 ARRAY_SIZE(usb_otg_pads));
}

int board_usb_phy_mode(int port)
{
	if (port == 1)
		return USB_INIT_HOST;
	else
		return usb_phy_mode(port);
}

int board_ehci_hcd_init(int port)
{
	u32 *usbnc_usb_ctrl;

	if (port > 1)
		return -EINVAL;

	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
				 port * 4);

	/* Set Power polarity */
	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);

	return 0;
}
#endif
#endif

#ifdef CONFIG_FEC_MXC
static int setup_fec(int fec_id)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;

	if (fec_id == 0) {
		/*
		 * Use 50M anatop loopback REF_CLK1 for ENET1,
		 * clear gpr1[13], set gpr1[17].
		 */
		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	} else {
		/*
		 * Use 50M anatop loopback REF_CLK2 for ENET2,
		 * clear gpr1[14], set gpr1[18].
		 */
		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
	}

	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
	if (ret)
		return ret;

	enable_enet_clk(1);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}
#endif

#ifdef CONFIG_DM_VIDEO
static iomux_v3_cfg_t const lcd_pads[] = {
	/* Use GPIO for Brightness adjustment, duty cycle = period. */
	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static int setup_lcd(void)
{
	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);

	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

	/* Reset the LCD */
	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
	udelay(500);
	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);

	/* Set Brightness to high */
	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);

	return 0;
}
#else
static inline int setup_lcd(void) { return 0; }
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef	CONFIG_FEC_MXC
	setup_fec(CONFIG_FEC_ENET_DEV);
#endif

#ifdef CONFIG_USB_EHCI_MX6
#ifndef CONFIG_DM_USB
	setup_usb();
#endif
#endif

#ifdef CONFIG_FSL_QSPI
	board_qspi_init();
#endif

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	env_set("board_name", "EVK");

	if (is_mx6ul_9x9_evk())
		env_set("board_rev", "9X9");
	else
		env_set("board_rev", "14X14");
#endif

	setup_lcd();

	return 0;
}

int checkboard(void)
{
	if (is_mx6ul_9x9_evk())
		puts("Board: MX6UL 9x9 EVK\n");
	else
		puts("Board: MX6UL 14x14 EVK\n");

	return 0;
}

/*
 * Backlight off and reset LCD before OS handover
 */
void board_preboot_os(void)
{
	gpio_set_value(IMX_GPIO_NR(1, 8), 0);
	gpio_set_value(IMX_GPIO_NR(5, 9), 0);
}

#ifdef CONFIG_SPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>


static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
	.grp_addds = 0x00000030,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_ctlds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
	.grp_ddr_type = 0x00080000,
#else
	.grp_ddr_type = 0x000c0000,
#endif
};

#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_ras = 0x00000030,
	.dram_cas = 0x00000030,
	.dram_odt0 = 0x00000000,
	.dram_odt1 = 0x00000000,
	.dram_sdba2 = 0x00000000,
	.dram_sdclk_0 = 0x00000030,
	.dram_sdqs0 = 0x00003030,
	.dram_sdqs1 = 0x00003030,
	.dram_reset = 0x00000030,
};

static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpwldectrl0 = 0x00000000,
	.p0_mpdgctrl0 = 0x20000000,
	.p0_mprddlctl = 0x4040484f,
	.p0_mpwrdlctl = 0x40405247,
	.mpzqlp2ctl = 0x1b4700c7,
};

static struct mx6_lpddr2_cfg mem_ddr = {
	.mem_speed = 800,
	.density = 2,
	.width = 16,
	.banks = 4,
	.rowaddr = 14,
	.coladdr = 10,
	.trcd_lp = 1500,
	.trppb_lp = 1500,
	.trpab_lp = 2000,
	.trasmin = 4250,
};

struct mx6_ddr_sysinfo ddr_sysinfo = {
	.dsize = 0,
	.cs_density = 18,
	.ncs = 1,
	.cs1_mirror = 0,
	.walat = 0,
	.ralat = 5,
	.mif3_mode = 3,
	.bi_on = 1,
	.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
	.rtt_nom = 0,
	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
	.ddr_type = DDR_TYPE_LPDDR2,
	.refsel = 0,	/* Refresh cycles at 64KHz */
	.refr = 3,	/* 4 refresh commands per refresh cycle */
};

#else
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_ras = 0x00000030,
	.dram_cas = 0x00000030,
	.dram_odt0 = 0x00000030,
	.dram_odt1 = 0x00000030,
	.dram_sdba2 = 0x00000000,
	.dram_sdclk_0 = 0x00000030,
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_reset = 0x00000030,
};

static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpwldectrl0 = 0x00000000,
	.p0_mpdgctrl0 = 0x41570155,
	.p0_mprddlctl = 0x4040474A,
	.p0_mpwrdlctl = 0x40405550,
};

struct mx6_ddr_sysinfo ddr_sysinfo = {
	.dsize = 0,
	.cs_density = 20,
	.ncs = 1,
	.cs1_mirror = 0,
	.rtt_wr = 2,
	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
	.walat = 0,		/* Write additional latency */
	.ralat = 5,		/* Read additional latency */
	.mif3_mode = 3,		/* Command prediction working mode */
	.bi_on = 1,		/* Bank interleaving enabled */
	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
	.ddr_type = DDR_TYPE_DDR3,
	.refsel = 0,	/* Refresh cycles at 64KHz */
	.refr = 1,	/* 2 refresh commands per refresh cycle */
};

static struct mx6_ddr3_cfg mem_ddr = {
	.mem_speed = 800,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};
#endif

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0xFFFFFFFF, &ccm->CCGR0);
	writel(0xFFFFFFFF, &ccm->CCGR1);
	writel(0xFFFFFFFF, &ccm->CCGR2);
	writel(0xFFFFFFFF, &ccm->CCGR3);
	writel(0xFFFFFFFF, &ccm->CCGR4);
	writel(0xFFFFFFFF, &ccm->CCGR5);
	writel(0xFFFFFFFF, &ccm->CCGR6);
	writel(0xFFFFFFFF, &ccm->CCGR7);
}

static void spl_dram_init(void)
{
	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	/* iomux and setup of i2c */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f0ff57b0 PF	2	/*
f0ff57b0 PF	3	* Copyright (C) 2015 Freescale Semiconductor, Inc.
f0ff57b0 PF	4	*/
f0ff57b0 PF	5
5255932f	6	#include <init.h>
90526e9f	7	#include <net.h>
f0ff57b0 PF	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/iomux.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/crm_regs.h>
	12	#include <asm/arch/mx6ul_pins.h>
	13	#include <asm/arch/mx6-pins.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/gpio.h>
552a848e SB	16	#include <asm/mach-imx/iomux-v3.h>
	17	#include <asm/mach-imx/boot_mode.h>
	18	#include <asm/mach-imx/mxc_i2c.h>
f0ff57b0 PF	19	#include <asm/io.h>
f0ff57b0 PF	20	#include <common.h>
9fb625ce	21	#include <env.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
f0ff57b0	23	#include <i2c.h>
0d4cdb56	24	#include <miiphy.h>
f0ff57b0 PF	25	#include <linux/sizes.h>
f0ff57b0 PF	26	#include <mmc.h>
0d4cdb56	27	#include <netdev.h>
d9cbb264 PF	28	#include <power/pmic.h>
	29	#include <power/pfuze3000_pmic.h>
	30	#include "../common/pfuze.h"
f0ff57b0	31	#include <usb.h>
e162c6b1	32	#include <usb/ehci-ci.h>
f0ff57b0 PF	33
	34	DECLARE_GLOBAL_DATA_PTR;
	35
	36	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	37	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	38	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	39
f0ff57b0 PF	40	#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	41	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	42	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	43	PAD_CTL_ODE)
	44
0d4cdb56 PF	45	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	46	PAD_CTL_SPEED_HIGH \| \
	47	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
	48
df674904 PF	49	#define LCD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	50	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm)
	51
0d4cdb56 PF	52	#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	53	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_ODE)
	54
	55	#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	56
1a8c0199 YL	57	#define OTG_ID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	58	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	59	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
f0ff57b0	60
1a8c0199 YL	61	#ifdef CONFIG_DM_PMIC
1a8c0199 YL	62	int power_init_board(void)
f0ff57b0	63	{
1a8c0199 YL	64	struct udevice *dev;
	65	int ret, dev_id, rev_id;
	66	unsigned int reg;
	67
	68	ret = pmic_get("pfuze3000", &dev);
	69	if (ret == -ENODEV)
	70	return 0;
	71	if (ret != 0)
	72	return ret;
f0ff57b0	73
1a8c0199 YL	74	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
	75	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
	76	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
f0ff57b0	77
1a8c0199 YL	78	/* disable Low Power Mode during standby mode */
	79	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
	80	reg \|= 0x1;
	81	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
f0ff57b0	82
1a8c0199	83	/* SW1B step ramp up time from 2us to 4us/25mV */
250cf754	84	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
f0ff57b0	85
1a8c0199	86	/* SW1B mode to APS/PFM */
250cf754	87	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
d9cbb264	88
1a8c0199	89	/* SW1B standby voltage set to 0.975V */
250cf754	90	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
d9cbb264 PF	91
	92	return 0;
	93	}
	94	#endif
f0ff57b0 PF	95
	96	int dram_init(void)
	97	{
d9cbb264	98	gd->ram_size = imx_ddr_size();
f0ff57b0 PF	99
	100	return 0;
	101	}
	102
	103	static iomux_v3_cfg_t const uart1_pads[] = {
	104	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	105	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	106	};
	107
f0ff57b0 PF	108
	109	static void setup_iomux_uart(void)
	110	{
	111	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	112	}
	113
	114	#ifdef CONFIG_FSL_QSPI
d547e7ab	115	static int board_qspi_init(void)
f0ff57b0	116	{
f0ff57b0 PF	117	/* Set the clock */
	118	enable_qspi_clk(0);
	119
	120	return 0;
	121	}
	122	#endif
	123
bcc70bc8 FE	124	#ifdef CONFIG_SPL_BUILD
	125
	126	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	127	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	128	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	129
	130	static iomux_v3_cfg_t const usdhc2_pads[] = {
	131	MX6_PAD_NAND_RE_B__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	132	MX6_PAD_NAND_WE_B__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	133	MX6_PAD_NAND_DATA00__USDHC2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	134	MX6_PAD_NAND_DATA01__USDHC2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	135	MX6_PAD_NAND_DATA02__USDHC2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	136	MX6_PAD_NAND_DATA03__USDHC2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
f0ff57b0 PF	137	};
f0ff57b0 PF	138
bcc70bc8 FE	139	static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	140	{USDHC2_BASE_ADDR, 0, 4},
	141	};
f0ff57b0 PF	142
	143	int board_mmc_getcd(struct mmc *mmc)
	144	{
bcc70bc8	145	return 1;
f0ff57b0 PF	146	}
	147
	148	int board_mmc_init(bd_t *bis)
	149	{
bcc70bc8 FE	150	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	151	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	152	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
f0ff57b0 PF	153	}
	154	#endif
	155
	156	#ifdef CONFIG_USB_EHCI_MX6
1a8c0199 YL	157	#ifndef CONFIG_DM_USB
1a8c0199 YL	158
f0ff57b0 PF	159	#define USB_OTHERREGS_OFFSET 0x800
	160	#define UCTRL_PWR_POL (1 << 9)
	161
	162	static iomux_v3_cfg_t const usb_otg_pads[] = {
1a8c0199	163	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID \| MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
f0ff57b0 PF	164	};
	165
	166	/* At default the 3v3 enables the MIC2026 for VBUS power */
	167	static void setup_usb(void)
	168	{
	169	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
	170	ARRAY_SIZE(usb_otg_pads));
	171	}
	172
	173	int board_usb_phy_mode(int port)
	174	{
	175	if (port == 1)
	176	return USB_INIT_HOST;
	177	else
	178	return usb_phy_mode(port);
	179	}
	180
	181	int board_ehci_hcd_init(int port)
	182	{
	183	u32 *usbnc_usb_ctrl;
	184
	185	if (port > 1)
	186	return -EINVAL;
	187
	188	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
	189	port * 4);
	190
	191	/* Set Power polarity */
	192	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
	193
	194	return 0;
	195	}
	196	#endif
1a8c0199	197	#endif
f0ff57b0	198
0d4cdb56	199	#ifdef CONFIG_FEC_MXC
0d4cdb56 PF	200	static int setup_fec(int fec_id)
	201	{
	202	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	203	int ret;
	204
	205	if (fec_id == 0) {
	206	/*
	207	* Use 50M anatop loopback REF_CLK1 for ENET1,
	208	* clear gpr1[13], set gpr1[17].
	209	*/
	210	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
	211	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	212	} else {
	213	/*
	214	* Use 50M anatop loopback REF_CLK2 for ENET2,
	215	* clear gpr1[14], set gpr1[18].
	216	*/
	217	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
	218	IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
	219	}
	220
	221	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
	222	if (ret)
	223	return ret;
	224
	225	enable_enet_clk(1);
	226
	227	return 0;
	228	}
	229
	230	int board_phy_config(struct phy_device *phydev)
	231	{
	232	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
	233
	234	if (phydev->drv->config)
	235	phydev->drv->config(phydev);
	236
	237	return 0;
	238	}
	239	#endif
	240
ae076058	241	#ifdef CONFIG_DM_VIDEO
df674904	242	static iomux_v3_cfg_t const lcd_pads[] = {
df674904 PF	243	/* Use GPIO for Brightness adjustment, duty cycle = period. */
	244	MX6_PAD_GPIO1_IO08__GPIO1_IO08 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	245	};
	246
	247	static int setup_lcd(void)
	248	{
708f6927	249	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
df674904 PF	250
	251	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
	252
	253	/* Reset the LCD */
1a8c0199	254	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
df674904 PF	255	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
	256	udelay(500);
	257	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
	258
	259	/* Set Brightness to high */
1a8c0199	260	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
df674904 PF	261	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
	262
	263	return 0;
	264	}
0a1a45b7 AG	265	#else
0a1a45b7 AG	266	static inline int setup_lcd(void) { return 0; }
df674904 PF	267	#endif
df674904 PF	268
f0ff57b0 PF	269	int board_early_init_f(void)
	270	{
	271	setup_iomux_uart();
	272
	273	return 0;
	274	}
	275
	276	int board_init(void)
	277	{
	278	/* Address of boot parameters */
	279	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	280
0d4cdb56 PF	281	#ifdef CONFIG_FEC_MXC
	282	setup_fec(CONFIG_FEC_ENET_DEV);
	283	#endif
	284
f0ff57b0	285	#ifdef CONFIG_USB_EHCI_MX6
1a8c0199	286	#ifndef CONFIG_DM_USB
f0ff57b0 PF	287	setup_usb();
f0ff57b0 PF	288	#endif
1a8c0199	289	#endif
f0ff57b0 PF	290
	291	#ifdef CONFIG_FSL_QSPI
	292	board_qspi_init();
	293	#endif
	294
	295	return 0;
	296	}
	297
	298	#ifdef CONFIG_CMD_BMODE
	299	static const struct boot_mode board_boot_modes[] = {
	300	/* 4 bit bus width */
	301	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
	302	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	303	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
	304	{NULL, 0},
	305	};
	306	#endif
	307
	308	int board_late_init(void)
	309	{
	310	#ifdef CONFIG_CMD_BMODE
	311	add_board_boot_modes(board_boot_modes);
	312	#endif
	313
d9cbb264	314	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
382bee57	315	env_set("board_name", "EVK");
d9cbb264 PF	316
d9cbb264 PF	317	if (is_mx6ul_9x9_evk())
382bee57	318	env_set("board_rev", "9X9");
d9cbb264	319	else
382bee57	320	env_set("board_rev", "14X14");
d9cbb264 PF	321	#endif
d9cbb264 PF	322
ae076058 PF	323	setup_lcd();
ae076058 PF	324
f0ff57b0 PF	325	return 0;
	326	}
	327
f0ff57b0 PF	328	int checkboard(void)
f0ff57b0 PF	329	{
d9cbb264 PF	330	if (is_mx6ul_9x9_evk())
	331	puts("Board: MX6UL 9x9 EVK\n");
	332	else
	333	puts("Board: MX6UL 14x14 EVK\n");
f0ff57b0 PF	334
	335	return 0;
	336	}
	337
7814abc0 AG	338	/*
	339	* Backlight off and reset LCD before OS handover
	340	*/
	341	void board_preboot_os(void)
	342	{
	343	gpio_set_value(IMX_GPIO_NR(1, 8), 0);
	344	gpio_set_value(IMX_GPIO_NR(5, 9), 0);
	345	}
	346
f0ff57b0	347	#ifdef CONFIG_SPL_BUILD
b08c8c48	348	#include <linux/libfdt.h>
f0ff57b0 PF	349	#include <spl.h>
	350	#include <asm/arch/mx6-ddr.h>
	351
d9cbb264 PF	352
	353	static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
	354	.grp_addds = 0x00000030,
	355	.grp_ddrmode_ctl = 0x00020000,
	356	.grp_b0ds = 0x00000030,
	357	.grp_ctlds = 0x00000030,
	358	.grp_b1ds = 0x00000030,
	359	.grp_ddrpke = 0x00000000,
	360	.grp_ddrmode = 0x00020000,
	361	#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
	362	.grp_ddr_type = 0x00080000,
	363	#else
	364	.grp_ddr_type = 0x000c0000,
	365	#endif
	366	};
	367
	368	#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
	369	static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	370	.dram_dqm0 = 0x00000030,
	371	.dram_dqm1 = 0x00000030,
	372	.dram_ras = 0x00000030,
	373	.dram_cas = 0x00000030,
	374	.dram_odt0 = 0x00000000,
	375	.dram_odt1 = 0x00000000,
	376	.dram_sdba2 = 0x00000000,
	377	.dram_sdclk_0 = 0x00000030,
	378	.dram_sdqs0 = 0x00003030,
	379	.dram_sdqs1 = 0x00003030,
	380	.dram_reset = 0x00000030,
	381	};
	382
	383	static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	384	.p0_mpwldectrl0 = 0x00000000,
	385	.p0_mpdgctrl0 = 0x20000000,
	386	.p0_mprddlctl = 0x4040484f,
	387	.p0_mpwrdlctl = 0x40405247,
	388	.mpzqlp2ctl = 0x1b4700c7,
	389	};
	390
	391	static struct mx6_lpddr2_cfg mem_ddr = {
	392	.mem_speed = 800,
	393	.density = 2,
	394	.width = 16,
	395	.banks = 4,
	396	.rowaddr = 14,
	397	.coladdr = 10,
	398	.trcd_lp = 1500,
	399	.trppb_lp = 1500,
	400	.trpab_lp = 2000,
	401	.trasmin = 4250,
	402	};
	403
	404	struct mx6_ddr_sysinfo ddr_sysinfo = {
	405	.dsize = 0,
	406	.cs_density = 18,
	407	.ncs = 1,
	408	.cs1_mirror = 0,
	409	.walat = 0,
	410	.ralat = 5,
	411	.mif3_mode = 3,
	412	.bi_on = 1,
	413	.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
	414	.rtt_nom = 0,
	415	.sde_to_rst = 0, /* LPDDR2 does not need this field */
416	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
417	.ddr_type = DDR_TYPE_LPDDR2,
edf00937 FE	418	.refsel = 0, /* Refresh cycles at 64KHz */
edf00937 FE	419	.refr = 3, /* 4 refresh commands per refresh cycle */
d9cbb264 PF	420	};
	421
	422	#else
	423	static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
f0ff57b0 PF	424	.dram_dqm0 = 0x00000030,
	425	.dram_dqm1 = 0x00000030,
	426	.dram_ras = 0x00000030,
	427	.dram_cas = 0x00000030,
	428	.dram_odt0 = 0x00000030,
	429	.dram_odt1 = 0x00000030,
	430	.dram_sdba2 = 0x00000000,
b343417e FE	431	.dram_sdclk_0 = 0x00000030,
b343417e FE	432	.dram_sdqs0 = 0x00000030,
f0ff57b0 PF	433	.dram_sdqs1 = 0x00000030,
	434	.dram_reset = 0x00000030,
	435	};
	436
d9cbb264	437	static struct mx6_mmdc_calibration mx6_mmcd_calib = {
b343417e FE	438	.p0_mpwldectrl0 = 0x00000000,
	439	.p0_mpdgctrl0 = 0x41570155,
	440	.p0_mprddlctl = 0x4040474A,
	441	.p0_mpwrdlctl = 0x40405550,
f0ff57b0 PF	442	};
f0ff57b0 PF	443
d9cbb264 PF	444	struct mx6_ddr_sysinfo ddr_sysinfo = {
	445	.dsize = 0,
	446	.cs_density = 20,
	447	.ncs = 1,
	448	.cs1_mirror = 0,
	449	.rtt_wr = 2,
	450	.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
b343417e	451	.walat = 0, /* Write additional latency */
d9cbb264 PF	452	.ralat = 5, /* Read additional latency */
	453	.mif3_mode = 3, /* Command prediction working mode */
	454	.bi_on = 1, /* Bank interleaving enabled */
	455	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	456	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
	457	.ddr_type = DDR_TYPE_DDR3,
7dbda25e FE	458	.refsel = 0, /* Refresh cycles at 64KHz */
7dbda25e FE	459	.refr = 1, /* 2 refresh commands per refresh cycle */
d9cbb264 PF	460	};
d9cbb264 PF	461
f0ff57b0 PF	462	static struct mx6_ddr3_cfg mem_ddr = {
	463	.mem_speed = 800,
	464	.density = 4,
	465	.width = 16,
	466	.banks = 8,
	467	.rowaddr = 15,
	468	.coladdr = 10,
	469	.pagesz = 2,
	470	.trcd = 1375,
	471	.trcmin = 4875,
	472	.trasmin = 3500,
	473	};
d9cbb264	474	#endif
f0ff57b0 PF	475
	476	static void ccgr_init(void)
	477	{
	478	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	479
	480	writel(0xFFFFFFFF, &ccm->CCGR0);
	481	writel(0xFFFFFFFF, &ccm->CCGR1);
	482	writel(0xFFFFFFFF, &ccm->CCGR2);
	483	writel(0xFFFFFFFF, &ccm->CCGR3);
	484	writel(0xFFFFFFFF, &ccm->CCGR4);
	485	writel(0xFFFFFFFF, &ccm->CCGR5);
	486	writel(0xFFFFFFFF, &ccm->CCGR6);
	487	writel(0xFFFFFFFF, &ccm->CCGR7);
	488	}
	489
	490	static void spl_dram_init(void)
	491	{
f0ff57b0	492	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
d9cbb264	493	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
f0ff57b0 PF	494	}
	495
	496	void board_init_f(ulong dummy)
	497	{
ab25f0f6 FE	498	ccgr_init();
ab25f0f6 FE	499
f0ff57b0 PF	500	/* setup AIPS and disable watchdog */
	501	arch_cpu_init();
	502
f0ff57b0 PF	503	/* iomux and setup of i2c */
	504	board_early_init_f();
	505
	506	/* setup GP timer */
	507	timer_init();
	508
	509	/* UART clocks enabled and gd valid - init serial console */
	510	preloader_console_init();
	511
	512	/* DDR initialization */
	513	spl_dram_init();
	514
	515	/* Clear the BSS. */
	516	memset(__bss_start, 0, __bss_end - __bss_start);
	517
	518	/* load/boot image from boot device */
	519	board_init_r(NULL, 0);
	520	}
f0ff57b0	521	#endif