[J-u-boot.git] / board / bachmann / ot1200 / ot1200.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
 * Copyright (C) 2014, Bachmann electronic GmbH
 */

#include <common.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <env.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
#include <asm/gpio.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

#define OUTPUT_40OHM	(PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)

#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
	OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define USDHC_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define ENET_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
	PAD_CTL_HYS)

#define SPI_PAD_CTRL	(PAD_CTL_HYS | OUTPUT_40OHM |		\
	PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
	PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

static iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}

static iomux_v3_cfg_t const ecspi1_pads[] = {
	MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};

static void setup_iomux_spi(void)
{
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}

int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
}

static iomux_v3_cfg_t const feature_pads[] = {
	/* SD card detect */
	MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),

	/* eMMC soldered? */
	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
};

static void setup_iomux_features(void)
{
	imx_iomux_v3_setup_multiple_pads(feature_pads,
		ARRAY_SIZE(feature_pads));
}

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

/* I2C2 - EEPROM */
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
		.gp = IMX_GPIO_NR(2, 30)
	},
	.sda = {
		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
		.gp = IMX_GPIO_NR(3, 16)
	}
};

/* I2C3 - IO expander  */
static struct i2c_pads_info i2c_pad_info2 = {
	.scl = {
		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
		.gp = IMX_GPIO_NR(3, 17)
	},
	.sda = {
		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
		.gp = IMX_GPIO_NR(3, 18)
	}
};

static void setup_iomux_i2c(void)
{
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
}

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC33, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

int board_early_init_f(void)
{
	ccgr_init();
	gpr_init();

	setup_iomux_uart();
	setup_iomux_spi();
	setup_iomux_i2c();
	setup_iomux_features();

	return 0;
}

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
		gpio_direction_input(IMX_GPIO_NR(4, 5));
		ret = gpio_get_value(IMX_GPIO_NR(4, 5));
	} else {
		gpio_direction_input(IMX_GPIO_NR(1, 5));
		ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
	}

	return ret;
}

struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC3_BASE_ADDR},
	{USDHC4_BASE_ADDR},
};

int board_mmc_init(bd_t *bis)
{
	int ret;
	u32 index = 0;

	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

	usdhc_cfg[0].max_bus_width = 8;
	usdhc_cfg[1].max_bus_width = 4;

	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
		switch (index) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
				"(%d) then supported by the board (%d)\n",
				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
		if (ret)
			return ret;
	}

	return 0;
}

static void leds_on(void)
{
	/* turn on all possible leds connected via GPIO expander */
	i2c_set_bus_num(2);
	pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
	pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
}

static void backlight_lcd_off(void)
{
	unsigned gpio = IMX_GPIO_NR(2, 0);
	gpio_direction_output(gpio, 0);

	gpio = IMX_GPIO_NR(2, 3);
	gpio_direction_output(gpio, 0);
}

int board_eth_init(bd_t *bis)
{
	uint32_t base = IMX_FEC_BASE;
	struct mii_dev *bus = NULL;
	struct phy_device *phydev = NULL;
	int ret;

	setup_iomux_enet();

	bus = fec_get_miibus(base, -1);
	if (!bus)
		return -EINVAL;

	/* scan phy 0 and 5 */
	phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
	if (!phydev) {
		ret = -EINVAL;
		goto free_bus;
	}

	/* depending on the phy address we can detect our board version */
	if (phydev->addr == 0)
		env_set("boardver", "");
	else
		env_set("boardver", "mr");

	printf("using phy at %d\n", phydev->addr);
	ret = fec_probe(bis, -1, base, bus, phydev);
	if (ret)
		goto free_phydev;

	return 0;

free_phydev:
	free(phydev);
free_bus:
	free(bus);
	return ret;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	backlight_lcd_off();

	leds_on();

#ifdef CONFIG_SATA
	setup_sata();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: "CONFIG_SYS_BOARD"\n");
	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{NULL,		0},
};
#endif

int misc_init_r(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
39d09733 CG	2	/*
	3	* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
	4	* Copyright (C) 2014, Bachmann electronic GmbH
39d09733 CG	5	*/
	6
	7	#include <common.h>
90526e9f	8	#include <net.h>
84c5dd16	9	#include <asm/io.h>
39d09733 CG	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/imx-regs.h>
	12	#include <asm/arch/iomux.h>
9fb625ce	13	#include <env.h>
39d09733 CG	14	#include <malloc.h>
39d09733 CG	15	#include <asm/arch/mx6-pins.h>
552a848e SB	16	#include <asm/mach-imx/iomux-v3.h>
	17	#include <asm/mach-imx/sata.h>
	18	#include <asm/mach-imx/mxc_i2c.h>
	19	#include <asm/mach-imx/boot_mode.h>
39d09733	20	#include <asm/arch/crm_regs.h>
f77dd6d7	21	#include <asm/arch/sys_proto.h>
39d09733	22	#include <mmc.h>
e37ac717	23	#include <fsl_esdhc_imx.h>
39d09733 CG	24	#include <netdev.h>
	25	#include <i2c.h>
	26	#include <pca953x.h>
	27	#include <asm/gpio.h>
	28	#include <phy.h>
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	#define OUTPUT_40OHM (PAD_CTL_SPEED_MED\|PAD_CTL_DSE_40ohm)
	33
	34	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	35	OUTPUT_40OHM \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	36
	37	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	38	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	39	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	40
	41	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| OUTPUT_40OHM \| \
	42	PAD_CTL_HYS)
	43
	44	#define SPI_PAD_CTRL (PAD_CTL_HYS \| OUTPUT_40OHM \| \
	45	PAD_CTL_SRE_FAST)
	46
	47	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| OUTPUT_40OHM \| \
	48	PAD_CTL_HYS \| PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	49
	50	int dram_init(void)
	51	{
f77dd6d7	52	gd->ram_size = imx_ddr_size();
39d09733 CG	53
	54	return 0;
	55	}
	56
	57	static iomux_v3_cfg_t const uart1_pads[] = {
	58	MX6_PAD_CSI0_DAT10__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	59	MX6_PAD_CSI0_DAT11__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	60	};
	61
	62	static void setup_iomux_uart(void)
	63	{
	64	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	65	}
	66
	67	static iomux_v3_cfg_t const enet_pads[] = {
	68	MX6_PAD_KEY_ROW1__ENET_COL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	69	MX6_PAD_KEY_COL3__ENET_CRS \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	70	MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	71	MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	72	MX6_PAD_GPIO_16__ENET_REF_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	73	MX6_PAD_GPIO_18__ENET_RX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	74	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	75	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	76	MX6_PAD_KEY_COL2__ENET_RX_DATA2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	77	MX6_PAD_KEY_COL0__ENET_RX_DATA3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	78	MX6_PAD_ENET_CRS_DV__ENET_RX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	79	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	80	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	81	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	82	MX6_PAD_KEY_ROW2__ENET_TX_DATA2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	83	MX6_PAD_KEY_ROW0__ENET_TX_DATA3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	84	MX6_PAD_ENET_TX_EN__ENET_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	85	};
	86
	87	static void setup_iomux_enet(void)
	88	{
	89	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	90	}
	91
	92	static iomux_v3_cfg_t const ecspi1_pads[] = {
	93	MX6_PAD_DISP0_DAT3__ECSPI3_SS0 \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	94	MX6_PAD_DISP0_DAT4__ECSPI3_SS1 \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	95	MX6_PAD_DISP0_DAT2__ECSPI3_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	96	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	97	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	98	};
	99
	100	static void setup_iomux_spi(void)
	101	{
	102	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
	103	}
	104
2e3a1f4d CG	105	int board_spi_cs_gpio(unsigned bus, unsigned cs)
	106	{
	107	return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
	108	}
	109
1199ddce CG	110	static iomux_v3_cfg_t const feature_pads[] = {
	111	/* SD card detect */
	112	MX6_PAD_GPIO_4__GPIO1_IO04 \| MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
	113
	114	/* eMMC soldered? */
	115	MX6_PAD_GPIO_19__GPIO4_IO05 \| MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
	116	};
	117
	118	static void setup_iomux_features(void)
	119	{
	120	imx_iomux_v3_setup_multiple_pads(feature_pads,
	121	ARRAY_SIZE(feature_pads));
	122	}
	123
cefe06bf CG	124	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
cefe06bf CG	125
130e6c8c CG	126	/* I2C2 - EEPROM */
	127	static struct i2c_pads_info i2c_pad_info1 = {
	128	.scl = {
	129	.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL \| PC,
	130	.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 \| PC,
	131	.gp = IMX_GPIO_NR(2, 30)
	132	},
	133	.sda = {
	134	.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA \| PC,
	135	.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 \| PC,
	136	.gp = IMX_GPIO_NR(3, 16)
	137	}
	138	};
	139
cefe06bf CG	140	/* I2C3 - IO expander */
	141	static struct i2c_pads_info i2c_pad_info2 = {
	142	.scl = {
	143	.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL \| PC,
	144	.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 \| PC,
	145	.gp = IMX_GPIO_NR(3, 17)
	146	},
	147	.sda = {
	148	.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| PC,
	149	.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 \| PC,
	150	.gp = IMX_GPIO_NR(3, 18)
	151	}
	152	};
	153
	154	static void setup_iomux_i2c(void)
	155	{
130e6c8c	156	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
cefe06bf CG	157	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	158	}
	159
84c5dd16 CG	160	static void ccgr_init(void)
	161	{
	162	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	163
	164	writel(0x00C03F3F, &ccm->CCGR0);
e88b8357	165	writel(0x0030FC33, &ccm->CCGR1);
84c5dd16 CG	166	writel(0x0FFFC000, &ccm->CCGR2);
	167	writel(0x3FF00000, &ccm->CCGR3);
	168	writel(0x00FFF300, &ccm->CCGR4);
	169	writel(0x0F0000C3, &ccm->CCGR5);
	170	writel(0x000003FF, &ccm->CCGR6);
	171	}
	172
39d09733 CG	173	int board_early_init_f(void)
39d09733 CG	174	{
84c5dd16 CG	175	ccgr_init();
	176	gpr_init();
	177
39d09733 CG	178	setup_iomux_uart();
39d09733 CG	179	setup_iomux_spi();
cefe06bf	180	setup_iomux_i2c();
1199ddce	181	setup_iomux_features();
39d09733 CG	182
	183	return 0;
	184	}
	185
	186	static iomux_v3_cfg_t const usdhc3_pads[] = {
	187	MX6_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	188	MX6_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	189	MX6_PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	190	MX6_PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	191	MX6_PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	192	MX6_PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	193	MX6_PAD_SD3_DAT4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	194	MX6_PAD_SD3_DAT5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	195	MX6_PAD_SD3_DAT6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	196	MX6_PAD_SD3_DAT7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	197	MX6_PAD_SD3_RST__SD3_RESET \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	198	};
	199
5a9ca420 CG	200	iomux_v3_cfg_t const usdhc4_pads[] = {
	201	MX6_PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	202	MX6_PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	203	MX6_PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	204	MX6_PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	205	MX6_PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	206	MX6_PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	207	};
	208
39d09733 CG	209	int board_mmc_getcd(struct mmc *mmc)
39d09733 CG	210	{
5a9ca420 CG	211	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	212	int ret;
	213
56740fa9 CG	214	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
	215	gpio_direction_input(IMX_GPIO_NR(4, 5));
	216	ret = gpio_get_value(IMX_GPIO_NR(4, 5));
	217	} else {
cb0b6986 CG	218	gpio_direction_input(IMX_GPIO_NR(1, 5));
cb0b6986 CG	219	ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
5a9ca420 CG	220	}
	221
	222	return ret;
39d09733 CG	223	}
39d09733 CG	224
5a9ca420	225	struct fsl_esdhc_cfg usdhc_cfg[2] = {
39d09733	226	{USDHC3_BASE_ADDR},
5a9ca420	227	{USDHC4_BASE_ADDR},
39d09733 CG	228	};
	229
	230	int board_mmc_init(bd_t *bis)
	231	{
e37197ac	232	int ret;
5a9ca420	233	u32 index = 0;
39d09733	234
5a9ca420 CG	235	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
5a9ca420 CG	236	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
39d09733	237
5a9ca420 CG	238	usdhc_cfg[0].max_bus_width = 8;
	239	usdhc_cfg[1].max_bus_width = 4;
	240
	241	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
	242	switch (index) {
	243	case 0:
	244	imx_iomux_v3_setup_multiple_pads(
	245	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	246	break;
	247	case 1:
	248	imx_iomux_v3_setup_multiple_pads(
	249	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	250	break;
	251	default:
	252	printf("Warning: you configured more USDHC controllers"
	253	"(%d) then supported by the board (%d)\n",
	254	index + 1, CONFIG_SYS_FSL_USDHC_NUM);
e37197ac	255	return -EINVAL;
5a9ca420 CG	256	}
5a9ca420 CG	257
e37197ac FE	258	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	259	if (ret)
	260	return ret;
5a9ca420 CG	261	}
5a9ca420 CG	262
e37197ac	263	return 0;
39d09733 CG	264	}
39d09733 CG	265
39d09733 CG	266	static void leds_on(void)
	267	{
	268	/* turn on all possible leds connected via GPIO expander */
	269	i2c_set_bus_num(2);
	270	pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
	271	pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
	272	}
	273
	274	static void backlight_lcd_off(void)
	275	{
	276	unsigned gpio = IMX_GPIO_NR(2, 0);
	277	gpio_direction_output(gpio, 0);
	278
	279	gpio = IMX_GPIO_NR(2, 3);
	280	gpio_direction_output(gpio, 0);
	281	}
	282
	283	int board_eth_init(bd_t *bis)
	284	{
	285	uint32_t base = IMX_FEC_BASE;
	286	struct mii_dev *bus = NULL;
	287	struct phy_device *phydev = NULL;
	288	int ret;
	289
	290	setup_iomux_enet();
	291
	292	bus = fec_get_miibus(base, -1);
	293	if (!bus)
cbb8f967	294	return -EINVAL;
39d09733 CG	295
	296	/* scan phy 0 and 5 */
	297	phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
	298	if (!phydev) {
cbb8f967 FE	299	ret = -EINVAL;
cbb8f967 FE	300	goto free_bus;
39d09733 CG	301	}
	302
	303	/* depending on the phy address we can detect our board version */
	304	if (phydev->addr == 0)
382bee57	305	env_set("boardver", "");
39d09733	306	else
382bee57	307	env_set("boardver", "mr");
39d09733 CG	308
	309	printf("using phy at %d\n", phydev->addr);
	310	ret = fec_probe(bis, -1, base, bus, phydev);
cbb8f967 FE	311	if (ret)
	312	goto free_phydev;
	313
39d09733	314	return 0;
cbb8f967 FE	315
	316	free_phydev:
	317	free(phydev);
	318	free_bus:
	319	free(bus);
	320	return ret;
39d09733 CG	321	}
	322
	323	int board_init(void)
	324	{
	325	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	326
	327	backlight_lcd_off();
	328
39d09733 CG	329	leds_on();
39d09733 CG	330
10e40d54	331	#ifdef CONFIG_SATA
3f97af53 CG	332	setup_sata();
	333	#endif
	334
39d09733 CG	335	return 0;
	336	}
	337
	338	int checkboard(void)
	339	{
	340	puts("Board: "CONFIG_SYS_BOARD"\n");
	341	return 0;
	342	}
	343
	344	#ifdef CONFIG_CMD_BMODE
	345	static const struct boot_mode board_boot_modes[] = {
	346	/* 4 bit bus width */
	347	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	348	{NULL, 0},
	349	};
	350	#endif
	351
	352	int misc_init_r(void)
	353	{
	354	#ifdef CONFIG_CMD_BMODE
	355	add_board_boot_modes(board_boot_modes);
	356	#endif
	357	return 0;
	358	}