[J-u-boot.git] / arch / arm / mach-u8500 / cache.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2019 Stephan Gerhold <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <asm/armv7.h>
#include <asm/cache.h>
#include <asm/pl310.h>

#define PL310_WAY_MASK	0xff

#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;

	/*
	 * Linux expects the L2 cache to be turned off by the bootloader.
	 * Otherwise, it fails very early (shortly after decompressing the kernel).
	 *
	 * On U8500, the L2 cache can be only turned on/off from the secure world.
	 * Instead, prevent usage of the L2 cache by locking all ways.
	 * The kernel needs to unlock them to make the L2 cache work again.
	 */
	writel(PL310_WAY_MASK, &pl310->pl310_lockdown_dbase);
	writel(PL310_WAY_MASK, &pl310->pl310_lockdown_ibase);
}
#endif
Commit	Line	Data
689088f9 SG	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright (C) 2019 Stephan Gerhold <[email protected]>
	4	*/
	5
	6	#include <common.h>
	7	#include <cpu_func.h>
	8	#include <asm/armv7.h>
90526e9f	9	#include <asm/cache.h>
689088f9 SG	10	#include <asm/pl310.h>
	11
	12	#define PL310_WAY_MASK 0xff
	13
	14	#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
	15	void enable_caches(void)
	16	{
	17	/* Enable D-cache. I-cache is already enabled in start.S */
	18	dcache_enable();
	19	}
	20	#endif
	21
	22	#ifdef CONFIG_SYS_L2_PL310
	23	void v7_outer_cache_disable(void)
	24	{
	25	struct pl310_regs const pl310 = (struct pl310_regs )CONFIG_SYS_PL310_BASE;
	26
	27	/*
	28	* Linux expects the L2 cache to be turned off by the bootloader.
	29	* Otherwise, it fails very early (shortly after decompressing the kernel).
	30	*
	31	* On U8500, the L2 cache can be only turned on/off from the secure world.
	32	* Instead, prevent usage of the L2 cache by locking all ways.
	33	* The kernel needs to unlock them to make the L2 cache work again.
	34	*/
	35	writel(PL310_WAY_MASK, &pl310->pl310_lockdown_dbase);
	36	writel(PL310_WAY_MASK, &pl310->pl310_lockdown_ibase);
	37	}
	38	#endif