]>
Commit | Line | Data |
---|---|---|
4782ac80 JZ |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. | |
3 | * Author: Jason Jin<[email protected]> | |
4 | * Zhang Wei<[email protected]> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | * with the reference on libata and ahci drvier in kernel | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | ||
29 | #ifdef CONFIG_SCSI_AHCI | |
30 | ||
31 | #include <command.h> | |
32 | #include <pci.h> | |
33 | #include <asm/processor.h> | |
34 | #include <asm/errno.h> | |
35 | #include <asm/io.h> | |
36 | #include <malloc.h> | |
37 | #include <scsi.h> | |
38 | #include <ata.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <ahci.h> | |
41 | ||
42 | struct ahci_probe_ent *probe_ent = NULL; | |
43 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; | |
44 | ||
4a7cc0f2 JL |
45 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
46 | ||
4782ac80 JZ |
47 | |
48 | static inline u32 ahci_port_base(u32 base, u32 port) | |
49 | { | |
50 | return base + 0x100 + (port * 0x80); | |
51 | } | |
52 | ||
53 | ||
54 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
55 | unsigned int port_idx) | |
56 | { | |
57 | base = ahci_port_base(base, port_idx); | |
58 | ||
4a7cc0f2 JL |
59 | port->cmd_addr = base; |
60 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
61 | } |
62 | ||
63 | ||
64 | #define msleep(a) udelay(a * 1000) | |
65 | #define ssleep(a) msleep(a * 1000) | |
4a7cc0f2 JL |
66 | |
67 | static int waiting_for_cmd_completed(volatile u8 *offset, | |
68 | int timeout_msec, | |
69 | u32 sign) | |
4782ac80 JZ |
70 | { |
71 | int i; | |
72 | u32 status; | |
4a7cc0f2 JL |
73 | |
74 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
75 | msleep(1); |
76 | ||
4a7cc0f2 | 77 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
78 | } |
79 | ||
80 | ||
81 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) | |
82 | { | |
83 | pci_dev_t pdev = probe_ent->dev; | |
84 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; | |
85 | u32 tmp, cap_save; | |
86 | u16 tmp16; | |
87 | int i, j; | |
4a7cc0f2 | 88 | volatile u8 *port_mmio; |
4782ac80 JZ |
89 | unsigned short vendor; |
90 | ||
91 | cap_save = readl(mmio + HOST_CAP); | |
4a7cc0f2 | 92 | cap_save &= ((1 << 28) | (1 << 17)); |
4782ac80 JZ |
93 | cap_save |= (1 << 27); |
94 | ||
95 | /* global controller reset */ | |
96 | tmp = readl(mmio + HOST_CTL); | |
97 | if ((tmp & HOST_RESET) == 0) | |
98 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
99 | ||
100 | /* reset must complete within 1 second, or | |
101 | * the hardware should be considered fried. | |
102 | */ | |
103 | ssleep(1); | |
104 | ||
105 | tmp = readl(mmio + HOST_CTL); | |
106 | if (tmp & HOST_RESET) { | |
107 | debug("controller reset failed (0x%x)\n", tmp); | |
108 | return -1; | |
109 | } | |
110 | ||
111 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
112 | writel(cap_save, mmio + HOST_CAP); | |
113 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
114 | ||
115 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
116 | ||
117 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
118 | u16 tmp16; | |
119 | pci_read_config_word(pdev, 0x92, &tmp16); | |
120 | tmp16 |= 0xf; | |
121 | pci_write_config_word(pdev, 0x92, tmp16); | |
122 | } | |
123 | ||
124 | probe_ent->cap = readl(mmio + HOST_CAP); | |
125 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
126 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; | |
127 | ||
128 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 129 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 JZ |
130 | |
131 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4a7cc0f2 JL |
132 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
133 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
134 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
135 | |
136 | /* make sure port is not active */ | |
137 | tmp = readl(port_mmio + PORT_CMD); | |
138 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
139 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
140 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
141 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
142 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
143 | ||
144 | /* spec says 500 msecs for each bit, so | |
145 | * this is slightly incorrect. | |
146 | */ | |
147 | msleep(500); | |
148 | } | |
149 | ||
150 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); | |
151 | ||
152 | j = 0; | |
153 | while (j < 100) { | |
154 | msleep(10); | |
155 | tmp = readl(port_mmio + PORT_SCR_STAT); | |
156 | if ((tmp & 0xf) == 0x3) | |
157 | break; | |
158 | j++; | |
159 | } | |
160 | ||
161 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
162 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
163 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
164 | ||
165 | /* ack any pending irq events for this port */ | |
166 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
167 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
168 | if (tmp) | |
169 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
170 | ||
171 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
172 | ||
173 | /* set irq mask (enables interrupts) */ | |
174 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
175 | ||
4a7cc0f2 | 176 | /*register linkup ports */ |
4782ac80 | 177 | tmp = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
178 | debug("Port %d status: 0x%x\n", i, tmp); |
179 | if ((tmp & 0xf) == 0x03) | |
180 | probe_ent->link_port_map |= (0x01 << i); | |
4782ac80 JZ |
181 | } |
182 | ||
183 | tmp = readl(mmio + HOST_CTL); | |
184 | debug("HOST_CTL 0x%x\n", tmp); | |
185 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
186 | tmp = readl(mmio + HOST_CTL); | |
187 | debug("HOST_CTL 0x%x\n", tmp); | |
188 | ||
189 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); | |
190 | tmp |= PCI_COMMAND_MASTER; | |
191 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | ||
197 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
198 | { | |
199 | pci_dev_t pdev = probe_ent->dev; | |
4a7cc0f2 | 200 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4782ac80 JZ |
201 | u32 vers, cap, impl, speed; |
202 | const char *speed_s; | |
203 | u16 cc; | |
204 | const char *scc_s; | |
205 | ||
206 | vers = readl(mmio + HOST_VERSION); | |
207 | cap = probe_ent->cap; | |
208 | impl = probe_ent->port_map; | |
209 | ||
210 | speed = (cap >> 20) & 0xf; | |
211 | if (speed == 1) | |
212 | speed_s = "1.5"; | |
213 | else if (speed == 2) | |
214 | speed_s = "3"; | |
215 | else | |
216 | speed_s = "?"; | |
217 | ||
218 | pci_read_config_word(pdev, 0x0a, &cc); | |
219 | if (cc == 0x0101) | |
220 | scc_s = "IDE"; | |
221 | else if (cc == 0x0106) | |
222 | scc_s = "SATA"; | |
223 | else if (cc == 0x0104) | |
224 | scc_s = "RAID"; | |
225 | else | |
226 | scc_s = "unknown"; | |
227 | ||
4a7cc0f2 JL |
228 | printf("AHCI %02x%02x.%02x%02x " |
229 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
230 | (vers >> 24) & 0xff, | |
231 | (vers >> 16) & 0xff, | |
232 | (vers >> 8) & 0xff, | |
233 | vers & 0xff, | |
234 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
235 | |
236 | printf("flags: " | |
4a7cc0f2 JL |
237 | "%s%s%s%s%s%s" |
238 | "%s%s%s%s%s%s%s\n", | |
239 | cap & (1 << 31) ? "64bit " : "", | |
240 | cap & (1 << 30) ? "ncq " : "", | |
241 | cap & (1 << 28) ? "ilck " : "", | |
242 | cap & (1 << 27) ? "stag " : "", | |
243 | cap & (1 << 26) ? "pm " : "", | |
244 | cap & (1 << 25) ? "led " : "", | |
245 | cap & (1 << 24) ? "clo " : "", | |
246 | cap & (1 << 19) ? "nz " : "", | |
247 | cap & (1 << 18) ? "only " : "", | |
248 | cap & (1 << 17) ? "pmp " : "", | |
249 | cap & (1 << 15) ? "pio " : "", | |
250 | cap & (1 << 14) ? "slum " : "", | |
251 | cap & (1 << 13) ? "part " : ""); | |
4782ac80 JZ |
252 | } |
253 | ||
4a7cc0f2 | 254 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 255 | { |
63cec581 ES |
256 | u32 iobase; |
257 | u16 vendor; | |
4782ac80 JZ |
258 | int rc; |
259 | ||
4a7cc0f2 | 260 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
4782ac80 | 261 | |
594e7983 ES |
262 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
263 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
4782ac80 JZ |
264 | probe_ent->dev = pdev; |
265 | ||
266 | pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); | |
267 | iobase &= ~0xf; | |
268 | ||
4a7cc0f2 JL |
269 | probe_ent->host_flags = ATA_FLAG_SATA |
270 | | ATA_FLAG_NO_LEGACY | |
271 | | ATA_FLAG_MMIO | |
272 | | ATA_FLAG_PIO_DMA | |
273 | | ATA_FLAG_NO_ATAPI; | |
274 | probe_ent->pio_mask = 0x1f; | |
275 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 276 | |
4a7cc0f2 | 277 | probe_ent->mmio_base = iobase; |
4782ac80 JZ |
278 | |
279 | /* Take from kernel: | |
280 | * JMicron-specific fixup: | |
281 | * make sure we're in AHCI mode | |
282 | */ | |
283 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 284 | if (vendor == 0x197b) |
4782ac80 JZ |
285 | pci_write_config_byte(pdev, 0x41, 0xa1); |
286 | ||
287 | /* initialize adapter */ | |
288 | rc = ahci_host_init(probe_ent); | |
289 | if (rc) | |
290 | goto err_out; | |
291 | ||
292 | ahci_print_info(probe_ent); | |
293 | ||
294 | return 0; | |
295 | ||
4a7cc0f2 | 296 | err_out: |
4782ac80 JZ |
297 | return rc; |
298 | } | |
299 | ||
300 | ||
301 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 302 | |
4782ac80 JZ |
303 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
304 | { | |
4782ac80 JZ |
305 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
306 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
307 | u32 sg_count; | |
308 | int i; | |
309 | ||
310 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 311 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
312 | printf("Error:Too much sg!\n"); |
313 | return -1; | |
314 | } | |
315 | ||
4a7cc0f2 JL |
316 | for (i = 0; i < sg_count; i++) { |
317 | ahci_sg->addr = | |
318 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 319 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
320 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
321 | (buf_len < MAX_DATA_BYTE_COUNT | |
322 | ? (buf_len - 1) | |
323 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
324 | ahci_sg++; |
325 | buf_len -= MAX_DATA_BYTE_COUNT; | |
326 | } | |
327 | ||
328 | return sg_count; | |
329 | } | |
330 | ||
331 | ||
332 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
333 | { | |
334 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
335 | pp->cmd_slot->status = 0; | |
336 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
337 | pp->cmd_slot->tbl_addr_hi = 0; | |
338 | } | |
339 | ||
340 | ||
341 | static void ahci_set_feature(u8 port) | |
342 | { | |
4782ac80 | 343 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
344 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
345 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
346 | u8 fis[20]; |
347 | ||
4a7cc0f2 JL |
348 | /*set feature */ |
349 | memset(fis, 0, 20); | |
4782ac80 JZ |
350 | fis[0] = 0x27; |
351 | fis[1] = 1 << 7; | |
352 | fis[2] = ATA_CMD_SETF; | |
353 | fis[3] = SETFEATURES_XFER; | |
354 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
355 | ||
4a7cc0f2 | 356 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
4782ac80 JZ |
357 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
358 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
359 | readl(port_mmio + PORT_CMD_ISSUE); | |
360 | ||
4a7cc0f2 | 361 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
4782ac80 JZ |
362 | printf("set feature error!\n"); |
363 | } | |
364 | } | |
365 | ||
366 | ||
367 | static int ahci_port_start(u8 port) | |
368 | { | |
4782ac80 | 369 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 370 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
371 | u32 port_status; |
372 | u32 mem; | |
373 | ||
4a7cc0f2 | 374 | debug("Enter start port: %d\n", port); |
4782ac80 | 375 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
376 | debug("Port %d status: %x\n", port, port_status); |
377 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
378 | printf("No Link on this port!\n"); |
379 | return -1; | |
380 | } | |
381 | ||
4a7cc0f2 | 382 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
383 | if (!mem) { |
384 | free(pp); | |
385 | printf("No mem for table!\n"); | |
386 | return -ENOMEM; | |
387 | } | |
388 | ||
4a7cc0f2 JL |
389 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
390 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 391 | |
4782ac80 JZ |
392 | /* |
393 | * First item in chunk of DMA memory: 32-slot command table, | |
394 | * 32 bytes each in size | |
395 | */ | |
396 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | |
4a7cc0f2 | 397 | debug("cmd_slot = 0x%x\n", pp->cmd_slot); |
4782ac80 | 398 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 399 | |
4782ac80 JZ |
400 | /* |
401 | * Second item: Received-FIS area | |
402 | */ | |
403 | pp->rx_fis = mem; | |
4782ac80 | 404 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 405 | |
4782ac80 JZ |
406 | /* |
407 | * Third item: data area for storing a single command | |
408 | * and its scatter-gather table | |
409 | */ | |
410 | pp->cmd_tbl = mem; | |
4a7cc0f2 | 411 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
412 | |
413 | mem += AHCI_CMD_TBL_HDR; | |
414 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; | |
415 | ||
4a7cc0f2 | 416 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
417 | |
418 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
419 | ||
420 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
4a7cc0f2 JL |
421 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
422 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 423 | |
4a7cc0f2 | 424 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
425 | |
426 | return 0; | |
427 | } | |
428 | ||
429 | ||
4a7cc0f2 JL |
430 | static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, |
431 | int buf_len) | |
4782ac80 JZ |
432 | { |
433 | ||
4a7cc0f2 JL |
434 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
435 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
436 | u32 opts; |
437 | u32 port_status; | |
438 | int sg_count; | |
439 | ||
4a7cc0f2 | 440 | debug("Enter get_ahci_device_data: for port %d\n", port); |
4782ac80 | 441 | |
4a7cc0f2 | 442 | if (port > probe_ent->n_ports) { |
4782ac80 JZ |
443 | printf("Invaild port number %d\n", port); |
444 | return -1; | |
445 | } | |
446 | ||
447 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
448 | if ((port_status & 0xf) != 0x03) { |
449 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
450 | return -1; |
451 | } | |
452 | ||
453 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
454 | ||
4a7cc0f2 JL |
455 | sg_count = ahci_fill_sg(port, buf, buf_len); |
456 | opts = (fis_len >> 2) | (sg_count << 16); | |
4782ac80 JZ |
457 | ahci_fill_cmd_slot(pp, opts); |
458 | ||
459 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
460 | ||
461 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { | |
462 | printf("timeout exit!\n"); | |
463 | return -1; | |
464 | } | |
465 | debug("get_ahci_device_data: %d byte transferred.\n", | |
4a7cc0f2 | 466 | pp->cmd_slot->status); |
4782ac80 JZ |
467 | |
468 | return 0; | |
469 | } | |
470 | ||
471 | ||
472 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
473 | { | |
474 | int i; | |
4a7cc0f2 | 475 | for (i = 0; i < len / 2; i++) |
4782ac80 JZ |
476 | target[i] = le16_to_cpu(src[i]); |
477 | return (char *)target; | |
478 | } | |
479 | ||
480 | ||
481 | static void dump_ataid(hd_driveid_t *ataid) | |
482 | { | |
483 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); | |
484 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); | |
485 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); | |
486 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); | |
487 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); | |
488 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); | |
489 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); | |
490 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); | |
491 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); | |
492 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); | |
493 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); | |
494 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); | |
495 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); | |
496 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); | |
497 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); | |
498 | } | |
499 | ||
4a7cc0f2 | 500 | |
4782ac80 JZ |
501 | /* |
502 | * SCSI INQUIRY command operation. | |
503 | */ | |
504 | static int ata_scsiop_inquiry(ccb *pccb) | |
505 | { | |
506 | u8 hdr[] = { | |
507 | 0, | |
508 | 0, | |
4a7cc0f2 | 509 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
510 | 2, |
511 | 95 - 4, | |
512 | }; | |
513 | u8 fis[20]; | |
514 | u8 *tmpid; | |
515 | u8 port; | |
516 | ||
517 | /* Clean ccb data buffer */ | |
518 | memset(pccb->pdata, 0, pccb->datalen); | |
519 | ||
520 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
521 | ||
4a7cc0f2 | 522 | if (pccb->datalen <= 35) |
4782ac80 JZ |
523 | return 0; |
524 | ||
525 | memset(fis, 0, 20); | |
526 | /* Construct the FIS */ | |
4a7cc0f2 JL |
527 | fis[0] = 0x27; /* Host to device FIS. */ |
528 | fis[1] = 1 << 7; /* Command FIS. */ | |
529 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ | |
4782ac80 JZ |
530 | |
531 | /* Read id from sata */ | |
532 | port = pccb->target; | |
4a7cc0f2 | 533 | if (!(tmpid = malloc(sizeof(hd_driveid_t)))) |
4782ac80 JZ |
534 | return -ENOMEM; |
535 | ||
4a7cc0f2 JL |
536 | if (get_ahci_device_data(port, (u8 *) & fis, 20, |
537 | tmpid, sizeof(hd_driveid_t))) { | |
4782ac80 JZ |
538 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
539 | return -EIO; | |
540 | } | |
541 | ||
4a7cc0f2 | 542 | if (ataid[port]) |
4782ac80 | 543 | free(ataid[port]); |
4a7cc0f2 | 544 | ataid[port] = (hd_driveid_t *) tmpid; |
4782ac80 JZ |
545 | |
546 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
4a7cc0f2 JL |
547 | ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
548 | ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); | |
4782ac80 JZ |
549 | |
550 | dump_ataid(ataid[port]); | |
551 | return 0; | |
552 | } | |
553 | ||
554 | ||
555 | /* | |
556 | * SCSI READ10 command operation. | |
557 | */ | |
4a7cc0f2 | 558 | static int ata_scsiop_read10(ccb * pccb) |
4782ac80 JZ |
559 | { |
560 | u64 lba = 0; | |
561 | u32 len = 0; | |
562 | u8 fis[20]; | |
563 | ||
4a7cc0f2 JL |
564 | lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) |
565 | | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); | |
566 | len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); | |
4782ac80 JZ |
567 | |
568 | /* For 10-byte and 16-byte SCSI R/W commands, transfer | |
569 | * length 0 means transfer 0 block of data. | |
570 | * However, for ATA R/W commands, sector count 0 means | |
571 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
572 | * | |
573 | * WARNING: one or two older ATA drives treat 0 as 0... | |
574 | */ | |
4a7cc0f2 JL |
575 | if (!len) |
576 | return 0; | |
4782ac80 JZ |
577 | memset(fis, 0, 20); |
578 | ||
579 | /* Construct the FIS */ | |
4a7cc0f2 JL |
580 | fis[0] = 0x27; /* Host to device FIS. */ |
581 | fis[1] = 1 << 7; /* Command FIS. */ | |
4782ac80 JZ |
582 | fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ |
583 | ||
4a7cc0f2 | 584 | /* LBA address, only support LBA28 in this driver */ |
4782ac80 JZ |
585 | fis[4] = pccb->cmd[5]; |
586 | fis[5] = pccb->cmd[4]; | |
587 | fis[6] = pccb->cmd[3]; | |
588 | fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; | |
589 | ||
590 | /* Sector Count */ | |
591 | fis[12] = pccb->cmd[8]; | |
592 | fis[13] = pccb->cmd[7]; | |
593 | ||
594 | /* Read from ahci */ | |
4a7cc0f2 JL |
595 | if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, |
596 | pccb->pdata, pccb->datalen)) { | |
4782ac80 JZ |
597 | debug("scsi_ahci: SCSI READ10 command failure.\n"); |
598 | return -EIO; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | ||
605 | /* | |
606 | * SCSI READ CAPACITY10 command operation. | |
607 | */ | |
608 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
609 | { | |
610 | u8 buf[8]; | |
611 | ||
4a7cc0f2 | 612 | if (!ataid[pccb->target]) { |
4782ac80 | 613 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
614 | "\tNo ATA info!\n" |
615 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
616 | return -EPERM; |
617 | } | |
618 | ||
619 | memset(buf, 0, 8); | |
620 | ||
4a7cc0f2 | 621 | *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); |
4782ac80 JZ |
622 | |
623 | buf[6] = 512 >> 8; | |
624 | buf[7] = 512 & 0xff; | |
625 | ||
626 | memcpy(pccb->pdata, buf, 8); | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | ||
632 | /* | |
633 | * SCSI TEST UNIT READY command operation. | |
634 | */ | |
635 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
636 | { | |
637 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
638 | } | |
639 | ||
4a7cc0f2 | 640 | |
4782ac80 JZ |
641 | int scsi_exec(ccb *pccb) |
642 | { | |
643 | int ret; | |
644 | ||
4a7cc0f2 | 645 | switch (pccb->cmd[0]) { |
4782ac80 JZ |
646 | case SCSI_READ10: |
647 | ret = ata_scsiop_read10(pccb); | |
648 | break; | |
649 | case SCSI_RD_CAPAC: | |
650 | ret = ata_scsiop_read_capacity10(pccb); | |
651 | break; | |
652 | case SCSI_TST_U_RDY: | |
653 | ret = ata_scsiop_test_unit_ready(pccb); | |
654 | break; | |
655 | case SCSI_INQUIRY: | |
656 | ret = ata_scsiop_inquiry(pccb); | |
657 | break; | |
658 | default: | |
659 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
660 | return FALSE; | |
661 | } | |
662 | ||
4a7cc0f2 JL |
663 | if (ret) { |
664 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
4782ac80 JZ |
665 | return FALSE; |
666 | } | |
667 | return TRUE; | |
668 | ||
669 | } | |
670 | ||
671 | ||
672 | void scsi_low_level_init(int busdevfunc) | |
673 | { | |
674 | int i; | |
675 | u32 linkmap; | |
676 | ||
677 | ahci_init_one(busdevfunc); | |
678 | ||
679 | linkmap = probe_ent->link_port_map; | |
680 | ||
4a7cc0f2 JL |
681 | for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { |
682 | if (((linkmap >> i) & 0x01)) { | |
683 | if (ahci_port_start((u8) i)) { | |
684 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
685 | continue; |
686 | } | |
4a7cc0f2 | 687 | ahci_set_feature((u8) i); |
4782ac80 JZ |
688 | } |
689 | } | |
690 | } | |
691 | ||
692 | ||
693 | void scsi_bus_reset(void) | |
694 | { | |
4a7cc0f2 | 695 | /*Not implement*/ |
4782ac80 JZ |
696 | } |
697 | ||
698 | ||
4a7cc0f2 | 699 | void scsi_print_error(ccb * pccb) |
4782ac80 | 700 | { |
4a7cc0f2 | 701 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 JZ |
702 | } |
703 | #endif |