[J-u-boot.git] / include / configs / x600.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
 * Author(s): Vipin Kumar, <[email protected]> for STMicroelectronics.
 *
 * Copyright (C) 2012, 2015 Stefan Roese <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SPEAR600				/* SPEAr600 SoC */
#define CONFIG_X600				/* on X600 board */

#include <asm/arch/hardware.h>

/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ_CLOCK			8300000

#define CONFIG_SYS_FLASH_BASE			0xf8000000
/* Reserve 8KiB for SPL */
#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
						 CONFIG_SYS_SPL_LEN)
#define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN			0x60000

/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0			0xD0000000
#define CONFIG_SYS_SERIAL1			0xD0080000
#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
						(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
						  57600, 115200 }
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NOR FLASH config options */
#define CONFIG_ST_SMI
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT		128
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)

/* NAND FLASH config options */
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
#define CONFIG_MTD_ECC_SOFT
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_ECC_BCH

/* UBI/UBI config options */

/* Ethernet config options */
#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */

#define CONFIG_SPEAR_GPIO

/* I2C config options */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE			0xD0200000
#define CONFIG_SYS_I2C_SPEED			400000
#define CONFIG_SYS_I2C_SLAVE			0x02
#define CONFIG_I2C_CHIPADDRESS			0x50

#define CONFIG_RTC_M41T62	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/* FPGA config options */
#define CONFIG_FPGA_COUNT	1

/* USB EHCI options */
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/*
 * U-Boot Environment placing definitions.
 */
#define CONFIG_ENV_SECT_SIZE			0x00010000
#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
						 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE				0x02000
#define CONFIG_ENV_ADDR_REDUND			(CONFIG_ENV_ADDR + \
						 CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND			(CONFIG_ENV_SIZE)

/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */

#define CONFIG_SYS_MEMTEST_START		0x00800000
#define CONFIG_SYS_MEMTEST_END			0x04000000
#define CONFIG_SYS_MALLOC_LEN			(8 << 20)
#define CONFIG_SYS_LOAD_ADDR			0x00800000

#define CONFIG_HOSTNAME				"x600"
#define CONFIG_UBI_PART				ubi0
#define CONFIG_UBIFS_VOLUME			rootfs

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u-boot_addr=1000000\0"						\
	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0"		\
	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};"					\
		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
		" ${filesize};"						\
		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize}\0"					\
	"upd=run load update\0"						\
	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
		" ${filesize}\0"					\
	"upd_ubifs=run load_ubifs update_ubifs\0"			\
	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
		"ubi create ${vol} 4000000\0"				\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk-4.2/arm\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"boot_part=0\0"							\
	"altbootcmd=if test $boot_part -eq 0;then "			\
			"echo Switching to partition 1!;"		\
			"setenv boot_part 1;"				\
		"else; "						\
			"echo Switching to partition 0!;"		\
			"setenv boot_part 0;"				\
		"fi;"							\
		"saveenv;boot\0"					\
	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
	"kernel_fs=/boot/uImage \0"					\
	"kernel_addr=1000000\0"						\
	"dtb=" CONFIG_HOSTNAME "/"				\
		CONFIG_HOSTNAME ".dtb\0"			\
	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
	"dtb_addr=1800000\0"						\
	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
		"${baudrate}\0"						\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"net_nfs=run load_dtb load_kernel; "				\
		"run nfsargs addip addcon addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
		" addcon addmisc addmtd;"				\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
	"bootcmd=run nand_ubifs\0"					\
	"\0"

/* Physical Memory Map */
#define PHYS_SDRAM_1				0x00000000
#define PHYS_SDRAM_1_MAXSIZE			0x40000000

#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
#define CONFIG_SRAM_BASE			0xd2800000
/* Preserve the last 2 lwords for the boot-counter */
#define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * SPL related defines
 */
#define CONFIG_SPL_TEXT_BASE		0xd2800b00
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"

/*
 * Please select/define only one of the following
 * Each definition corresponds to a supported DDR chip.
 * DDR configuration is based on the following selection
 */
#define CONFIG_DDR_MT47H64M16		1
#define CONFIG_DDR_MT47H32M16		0
#define CONFIG_DDR_MT47H128M8		0

/*
 * Synchronous/Asynchronous operation of DDR
 *
 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
 */
#define CONFIG_DDR_2HCLK		1
#define CONFIG_DDR_HCLK			0
#define CONFIG_DDR_PLL2			0

/*
 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
 * or not. Modify/Add to only these macros to define new boot types
 */
#define USB_BOOT_SUPPORTED		0
#define PCIE_BOOT_SUPPORTED		0
#define SNOR_BOOT_SUPPORTED		1
#define NAND_BOOT_SUPPORTED		1
#define PNOR_BOOT_SUPPORTED		0
#define TFTP_BOOT_SUPPORTED		0
#define UART_BOOT_SUPPORTED		0
#define SPI_BOOT_SUPPORTED		0
#define I2C_BOOT_SUPPORTED		0
#define MMC_BOOT_SUPPORTED		0

#endif  /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
995b72dd	2	/*
e36591c3 PC	3	* Copyright (C) 2009, STMicroelectronics - All Rights Reserved
e36591c3 PC	4	* Author(s): Vipin Kumar, <[email protected]> for STMicroelectronics.
995b72dd	5	*
2fbdbda1	6	* Copyright (C) 2012, 2015 Stefan Roese <[email protected]>
995b72dd SR	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	* (easy to change)
	15	*/
	16	#define CONFIG_SPEAR600 /* SPEAr600 SoC */
	17	#define CONFIG_X600 /* on X600 board */
	18
	19	#include <asm/arch/hardware.h>
	20
	21	/* Timer, HZ specific defines */
995b72dd SR	22	#define CONFIG_SYS_HZ_CLOCK 8300000
995b72dd SR	23
995b72dd SR	24	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	25	/* Reserve 8KiB for SPL */
	26	#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
	27	#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
	28	#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
	29	CONFIG_SYS_SPL_LEN)
285e266b	30	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
995b72dd SR	31	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	32	#define CONFIG_SYS_MONITOR_LEN 0x60000
	33
995b72dd SR	34	/* Serial Configuration (PL011) */
	35	#define CONFIG_SYS_SERIAL0 0xD0000000
	36	#define CONFIG_SYS_SERIAL1 0xD0080000
	37	#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
	38	(void *)CONFIG_SYS_SERIAL1 }
995b72dd	39	#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
995b72dd SR	40	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
	41	57600, 115200 }
	42	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	43
	44	/* NOR FLASH config options */
	45	#define CONFIG_ST_SMI
	46	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	47	#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
	48	#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
	49	#define CONFIG_SYS_MAX_FLASH_SECT 128
	50	#define CONFIG_SYS_FLASH_EMPTY_INFO
	51	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
	52	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
	53
	54	/* NAND FLASH config options */
	55	#define CONFIG_NAND_FSMC
	56	#define CONFIG_SYS_NAND_SELF_INIT
	57	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	58	#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
	59	#define CONFIG_MTD_ECC_SOFT
	60	#define CONFIG_SYS_FSMC_NAND_8BIT
	61	#define CONFIG_SYS_NAND_ONFI_DETECTION
0ddc5a2d	62	#define CONFIG_NAND_ECC_BCH
995b72dd SR	63
995b72dd SR	64	/* UBI/UBI config options */
995b72dd SR	65
995b72dd SR	66	/* Ethernet config options */
995b72dd	67	#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
995b72dd SR	68
	69	#define CONFIG_SPEAR_GPIO
	70
	71	/* I2C config options */
678398b1	72	#define CONFIG_SYS_I2C
f93f589c	73	#define CONFIG_SYS_I2C_BASE 0xD0200000
995b72dd SR	74	#define CONFIG_SYS_I2C_SPEED 400000
	75	#define CONFIG_SYS_I2C_SLAVE 0x02
	76	#define CONFIG_I2C_CHIPADDRESS 0x50
	77
	78	#define CONFIG_RTC_M41T62 1
	79	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	80
	81	/* FPGA config options */
995b72dd SR	82	#define CONFIG_FPGA_COUNT 1
995b72dd SR	83
285e266b	84	/* USB EHCI options */
285e266b	85	#define CONFIG_USB_EHCI_SPEAR
285e266b SR	86	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
285e266b SR	87
995b72dd SR	88	/*
	89	* U-Boot Environment placing definitions.
	90	*/
	91	#define CONFIG_ENV_SECT_SIZE 0x00010000
	92	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	93	CONFIG_SYS_MONITOR_LEN)
	94	#define CONFIG_ENV_SIZE 0x02000
	95	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
	96	CONFIG_ENV_SECT_SIZE)
	97	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	98
	99	/* Miscellaneous configurable options */
	100	#define CONFIG_ARCH_CPU_INIT
995b72dd SR	101	#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
995b72dd SR	102	#define CONFIG_CMDLINE_TAG
995b72dd	103	#define CONFIG_SETUP_MEMORY_TAGS
995b72dd	104	#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
995b72dd SR	105
	106	#define CONFIG_SYS_MEMTEST_START 0x00800000
	107	#define CONFIG_SYS_MEMTEST_END 0x04000000
285e266b	108	#define CONFIG_SYS_MALLOC_LEN (8 << 20)
995b72dd	109	#define CONFIG_SYS_LOAD_ADDR 0x00800000
995b72dd	110
5bc0543d	111	#define CONFIG_HOSTNAME "x600"
995b72dd SR	112	#define CONFIG_UBI_PART ubi0
	113	#define CONFIG_UBIFS_VOLUME rootfs
	114
995b72dd SR	115	#define CONFIG_EXTRA_ENV_SETTINGS \
995b72dd SR	116	"u-boot_addr=1000000\0" \
5bc0543d	117	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \
995b72dd	118	"load=tftp ${u-boot_addr} ${u-boot}\0" \
4a8c3f69 AG	119	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	120	" +${filesize};" \
	121	"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
	122	"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd	123	" ${filesize};" \
4a8c3f69	124	"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd SR	125	" +${filesize}\0" \
995b72dd SR	126	"upd=run load update\0" \
5bc0543d	127	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
4a8c3f69 AG	128	"part=" __stringify(CONFIG_UBI_PART) "\0" \
4a8c3f69 AG	129	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
995b72dd SR	130	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
	131	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
	132	" ${filesize}\0" \
	133	"upd_ubifs=run load_ubifs update_ubifs\0" \
	134	"init_ubifs=nand erase.part ubi0;ubi part ${part};" \
	135	"ubi create ${vol} 4000000\0" \
	136	"netdev=eth0\0" \
	137	"rootpath=/opt/eldk-4.2/arm\0" \
	138	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	139	"nfsroot=${serverip}:${rootpath}\0" \
	140	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	141	"boot_part=0\0" \
	142	"altbootcmd=if test $boot_part -eq 0;then " \
	143	"echo Switching to partition 1!;" \
	144	"setenv boot_part 1;" \
	145	"else; " \
	146	"echo Switching to partition 0!;" \
	147	"setenv boot_part 0;" \
	148	"fi;" \
	149	"saveenv;boot\0" \
	150	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
	151	"root=ubi0:rootfs rootfstype=ubifs\0" \
5bc0543d	152	"kernel=" CONFIG_HOSTNAME "/uImage\0" \
995b72dd SR	153	"kernel_fs=/boot/uImage \0" \
995b72dd SR	154	"kernel_addr=1000000\0" \
5bc0543d MS	155	"dtb=" CONFIG_HOSTNAME "/" \
	156	CONFIG_HOSTNAME ".dtb\0" \
	157	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
995b72dd SR	158	"dtb_addr=1800000\0" \
	159	"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
	160	"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
	161	"addip=setenv bootargs ${bootargs} " \
	162	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	163	":${hostname}:${netdev}:off panic=1\0" \
	164	"addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
	165	"${baudrate}\0" \
	166	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	167	"net_nfs=run load_dtb load_kernel; " \
	168	"run nfsargs addip addcon addmtd addmisc;" \
	169	"bootm ${kernel_addr} - ${dtb_addr}\0" \
43ede0bc TR	170	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	171	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
995b72dd SR	172	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
	173	" addcon addmisc addmtd;" \
	174	"bootm ${kernel_addr} - ${dtb_addr}\0" \
949a7710	175	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
995b72dd SR	176	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
	177	"ubifsload ${dtb_addr} ${dtb_fs};\0" \
	178	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
	179	"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
	180	"bootcmd=run nand_ubifs\0" \
	181	"\0"
	182
995b72dd	183	/* Physical Memory Map */
995b72dd SR	184	#define PHYS_SDRAM_1 0x00000000
	185	#define PHYS_SDRAM_1_MAXSIZE 0x40000000
	186
	187	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
2fbdbda1 SR	188	#define CONFIG_SRAM_BASE 0xd2800000
	189	/* Preserve the last 2 lwords for the boot-counter */
	190	#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
	191	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
	192	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
995b72dd SR	193
	194	#define CONFIG_SYS_INIT_SP_OFFSET \
	195	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	196
	197	#define CONFIG_SYS_INIT_SP_ADDR \
	198	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	199
	200	/*
	201	* SPL related defines
	202	*/
2fbdbda1 SR	203	#define CONFIG_SPL_TEXT_BASE 0xd2800b00
2fbdbda1 SR	204	#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
995b72dd	205	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
995b72dd	206
995b72dd SR	207	/*
	208	* Please select/define only one of the following
	209	* Each definition corresponds to a supported DDR chip.
	210	* DDR configuration is based on the following selection
	211	*/
	212	#define CONFIG_DDR_MT47H64M16 1
	213	#define CONFIG_DDR_MT47H32M16 0
	214	#define CONFIG_DDR_MT47H128M8 0
	215
	216	/*
	217	* Synchronous/Asynchronous operation of DDR
	218	*
	219	* Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
	220	* Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
	221	* Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
	222	*/
	223	#define CONFIG_DDR_2HCLK 1
	224	#define CONFIG_DDR_HCLK 0
	225	#define CONFIG_DDR_PLL2 0
	226
	227	/*
	228	* xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
	229	* or not. Modify/Add to only these macros to define new boot types
	230	*/
	231	#define USB_BOOT_SUPPORTED 0
	232	#define PCIE_BOOT_SUPPORTED 0
	233	#define SNOR_BOOT_SUPPORTED 1
	234	#define NAND_BOOT_SUPPORTED 1
	235	#define PNOR_BOOT_SUPPORTED 0
	236	#define TFTP_BOOT_SUPPORTED 0
	237	#define UART_BOOT_SUPPORTED 0
	238	#define SPI_BOOT_SUPPORTED 0
	239	#define I2C_BOOT_SUPPORTED 0
	240	#define MMC_BOOT_SUPPORTED 0
	241
	242	#endif /* __CONFIG_H */