[J-u-boot.git] / include / configs / controlcenterd.h

/*
 * (C) Copyright 2013
 * Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
 *
 * based on P1022DS.h
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#endif

/* High Level Configuration Options */
#define CONFIG_CONTROLCENTERD

#define CONFIG_ENABLE_36BIT_PHYS

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
#endif

#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_CLK_FREQ	66666600
#define CONFIG_DDR_CLK_FREQ	66666600

#define CONFIG_SYS_RAMBOOT

#ifdef CONFIG_TRAILBLAZER

#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

/*
 * Config the L2 Cache
 */
#define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)

#else /* CONFIG_TRAILBLAZER */

#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#endif /* CONFIG_TRAILBLAZER */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

/*
 * Memory map
 *
 * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
 * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
 * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
 *
 * Localbus non-cacheable
 * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
 * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#ifdef CONFIG_TRAILBLAZER
/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
#else
#define CONFIG_SYS_CCSRBAR		0xffe00000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)

/*
 * DDR Setup
 */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

#define CONFIG_SYS_MEMTEST_START	0x00000000
#define CONFIG_SYS_MEMTEST_END		0x3fffffff

#ifdef CONFIG_TRAILBLAZER
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS 0x52
/*#define CONFIG_FSL_DDR_INTERACTIVE*/
#endif

/*
 * Local Bus Definitions
 */

#define CONFIG_SYS_ELBC_BASE		0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
#endif

#define CONFIG_UART_BR_PRELIM  \
	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
#define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)

#define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
#define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */

#define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

#ifndef CONFIG_TRAILBLAZER
/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_HARD_SPI

#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		0
#endif

/*
 * MMC
 */
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR

#ifndef CONFIG_TRAILBLAZER

/*
 * Video
 */
#define CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */

#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/*
 * SATA
 */
#define CONFIG_LBA48

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

/*
 * Ethernet
 */

#define CONFIG_TSECV2

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

/*
 * USB
 */

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

#endif /* CONFIG_TRAILBLAZER */

/*
 * Environment
 */
#if defined(CONFIG_TRAILBLAZER)
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_SYS_MMC_ENV_DEV	0
#endif

#define CONFIG_SYS_EXTRA_ENV_RELOC

/*
 * Command line configuration.
 */

#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#ifndef CONFIG_TRAILBLAZER
/*
 * Board initialisation callbacks
 */
#endif /* CONFIG_TRAILBLAZER */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_HW_WATCHDOG
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TRAILBLAZER
#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"mp_holdoff=1\0"

#else

#define CONFIG_HOSTNAME		"controlcenterd"
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */

#define CONFIG_LOADADDR		1000000

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
		"protect off $ubootaddr +$filesize && "		\
		"erase $ubootaddr +$filesize && "		\
		"cp.b $loadaddr $ubootaddr $filesize && "	\
		"protect on $ubootaddr +$filesize && "		\
		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
	"consoledev=ttyS1\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=controlcenterd.dtb\0"				\
	"bdev=sda3\0"

/* these are used and NUL-terminated in env_default.h */
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND

#endif /* CONFIG_TRAILBLAZER */

#endif
Commit	Line	Data
b9944a77 DE	1	/*
	2	* (C) Copyright 2013
	3	* Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
	4	*
	5	* based on P1022DS.h
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
b9944a77 DE	29	#ifdef CONFIG_SDCARD
	30	#define CONFIG_RAMBOOT_SDCARD
	31	#endif
	32
	33	#ifdef CONFIG_SPIFLASH
	34	#define CONFIG_RAMBOOT_SPIFLASH
	35	#endif
	36
	37	/* High Level Configuration Options */
b9944a77	38	#define CONFIG_CONTROLCENTERD
b9944a77	39
b9944a77	40	#define CONFIG_ENABLE_36BIT_PHYS
b9944a77	41
b9944a77 DE	42	#ifdef CONFIG_PHYS_64BIT
	43	#define CONFIG_ADDR_MAP
	44	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	45	#endif
	46
	47	#define CONFIG_L2_CACHE
	48	#define CONFIG_BTB
	49
	50	#define CONFIG_SYS_CLK_FREQ 66666600
	51	#define CONFIG_DDR_CLK_FREQ 66666600
	52
	53	#define CONFIG_SYS_RAMBOOT
	54
	55	#ifdef CONFIG_TRAILBLAZER
	56
b9944a77 DE	57	#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
	58	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	59
	60	/*
	61	* Config the L2 Cache
	62	*/
	63	#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
	64	#ifdef CONFIG_PHYS_64BIT
	65	#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
	66	#else
	67	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	68	#endif
	69	#define CONFIG_SYS_L2_SIZE (256 << 10)
	70	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	71
	72	#else /* CONFIG_TRAILBLAZER */
	73
b9944a77 DE	74	#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
	75	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	76
	77	#endif /* CONFIG_TRAILBLAZER */
	78
	79	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	80	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	81
b9944a77 DE	82	/*
	83	* Memory map
	84	*
	85	* 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
	86	* 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
	87	* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
	88	*
	89	* Localbus non-cacheable
	90	* 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
	91	* 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
	92	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
	93	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	94	*/
	95
	96	#define CONFIG_SYS_INIT_RAM_LOCK
	97	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
	98	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
	99	#define CONFIG_SYS_GBL_DATA_OFFSET \
	100	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	101	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	102
	103	#ifdef CONFIG_TRAILBLAZER
	104	/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
	105	#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
	106	#else
	107	#define CONFIG_SYS_CCSRBAR 0xffe00000
	108	#endif
	109	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	110	#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
	111
	112	/*
	113	* DDR Setup
	114	*/
	115
	116	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	117	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	118	#define CONFIG_SYS_SDRAM_SIZE 1024
	119	#define CONFIG_VERY_BIG_RAM
	120
b9944a77 DE	121	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	122	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	123
	124	#define CONFIG_SYS_MEMTEST_START 0x00000000
	125	#define CONFIG_SYS_MEMTEST_END 0x3fffffff
	126
	127	#ifdef CONFIG_TRAILBLAZER
	128	#define CONFIG_SPD_EEPROM
	129	#define SPD_EEPROM_ADDRESS 0x52
	130	/#define CONFIG_FSL_DDR_INTERACTIVE/
	131	#endif
	132
	133	/*
	134	* Local Bus Definitions
	135	*/
b9944a77 DE	136
	137	#define CONFIG_SYS_ELBC_BASE 0xe0000000
	138	#ifdef CONFIG_PHYS_64BIT
	139	#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
	140	#else
	141	#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
	142	#endif
	143
	144	#define CONFIG_UART_BR_PRELIM \
	145	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) \| BR_PS_8 \| BR_V)
	146	#define CONFIG_UART_OR_PRELIM (OR_AM_32KB \| 0xff7)
	147
	148	#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
	149	#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
	150
	151	#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
	152	#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
	153
	154	/*
	155	* Serial Port
	156	*/
b9944a77 DE	157	#define CONFIG_SYS_NS16550_SERIAL
	158	#define CONFIG_SYS_NS16550_REG_SIZE 1
	159	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	160
	161	#define CONFIG_SYS_BAUDRATE_TABLE \
	162	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	163
	164	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	165	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	166
	167	/*
	168	* I2C
	169	*/
00f792e0 HS	170	#define CONFIG_SYS_I2C
	171	#define CONFIG_SYS_I2C_FSL
	172	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	173	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	174	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	175	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	176	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	177	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
5568fb44	178
b9944a77 DE	179	#define CONFIG_PCA9698 /* NXP PCA9698 */
b9944a77 DE	180
b9944a77 DE	181	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	182	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	183
	184	#ifndef CONFIG_TRAILBLAZER
	185	/*
	186	* eSPI - Enhanced SPI
	187	*/
	188	#define CONFIG_HARD_SPI
b9944a77	189
b9944a77 DE	190	#define CONFIG_SF_DEFAULT_SPEED 10000000
	191	#define CONFIG_SF_DEFAULT_MODE 0
	192	#endif
	193
b9944a77 DE	194	/*
	195	* MMC
	196	*/
b9944a77 DE	197	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
b9944a77 DE	198
b9944a77 DE	199	#ifndef CONFIG_TRAILBLAZER
	200
	201	/*
	202	* Video
	203	*/
	204	#define CONFIG_FSL_DIU_FB
	205	#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
b9944a77 DE	206
	207	/*
	208	* General PCI
	209	* Memory space is mapped 1-1, but I/O space must start from 0.
	210	*/
b38eaec5	211	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b9944a77	212	#define CONFIG_PCI_INDIRECT_BRIDGE
b9944a77 DE	213	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
b9944a77 DE	214	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
b9944a77 DE	215
	216	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	217	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	218
	219	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
	220	#ifdef CONFIG_PHYS_64BIT
	221	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
	222	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
	223	#else
	224	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	225	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	226	#endif
	227	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	228	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	229	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	230	#ifdef CONFIG_PHYS_64BIT
	231	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
	232	#else
	233	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	234	#endif
	235	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	236
	237	/*
	238	* SATA
	239	*/
b9944a77	240	#define CONFIG_LBA48
b9944a77	241
b9944a77 DE	242	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	243	#define CONFIG_SATA1
	244	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	245	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	246	#define CONFIG_SATA2
	247	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	248	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	249
	250	/*
	251	* Ethernet
	252	*/
b9944a77 DE	253
	254	#define CONFIG_TSECV2
	255
b9944a77 DE	256	#define CONFIG_TSEC1 1
	257	#define CONFIG_TSEC1_NAME "eTSEC1"
	258	#define CONFIG_TSEC2 1
	259	#define CONFIG_TSEC2_NAME "eTSEC2"
	260
	261	#define TSEC1_PHY_ADDR 0
	262	#define TSEC2_PHY_ADDR 1
	263
	264	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	265	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	266
	267	#define TSEC1_PHYIDX 0
	268	#define TSEC2_PHYIDX 0
	269
	270	#define CONFIG_ETHPRIME "eTSEC1"
	271
b9944a77 DE	272	/*
	273	* USB
	274	*/
b9944a77 DE	275
	276	#define CONFIG_HAS_FSL_DR_USB
	277	#define CONFIG_USB_EHCI_FSL
	278	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	279
	280	#endif /* CONFIG_TRAILBLAZER */
	281
	282	/*
	283	* Environment
	284	*/
	285	#if defined(CONFIG_TRAILBLAZER)
b9944a77	286	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
b9944a77	287	#elif defined(CONFIG_RAMBOOT_SPIFLASH)
b9944a77 DE	288	#define CONFIG_ENV_SPI_BUS 0
	289	#define CONFIG_ENV_SPI_CS 0
	290	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	291	#define CONFIG_ENV_SPI_MODE 0
	292	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	293	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	294	#define CONFIG_ENV_SECT_SIZE 0x10000
	295	#elif defined(CONFIG_RAMBOOT_SDCARD)
b9944a77 DE	296	#define CONFIG_FSL_FIXED_MMC_LOCATION
	297	#define CONFIG_ENV_SIZE 0x2000
	298	#define CONFIG_SYS_MMC_ENV_DEV 0
	299	#endif
	300
	301	#define CONFIG_SYS_EXTRA_ENV_RELOC
	302
b9944a77 DE	303	/*
	304	* Command line configuration.
	305	*/
b9944a77 DE	306
b9944a77 DE	307	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
b9944a77	308
b9944a77	309	#ifndef CONFIG_TRAILBLAZER
b9944a77 DE	310	/*
	311	* Board initialisation callbacks
	312	*/
b9944a77 DE	313	#endif /* CONFIG_TRAILBLAZER */
	314
	315	/*
	316	* Miscellaneous configurable options
	317	*/
b9944a77 DE	318	#define CONFIG_HW_WATCHDOG
	319	#define CONFIG_LOADS_ECHO
	320	#define CONFIG_SYS_LOADS_BAUD_CHANGE
b9944a77 DE	321
	322	/*
	323	* For booting Linux, the board info and command line data
	324	* have to be in the first 64 MB of memory, since this is
	325	* the maximum mapped by the Linux kernel during initialization.
	326	*/
	327	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
	328	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	329
	330	/*
	331	* Environment Configuration
	332	*/
	333
	334	#ifdef CONFIG_TRAILBLAZER
b9944a77 DE	335	#define CONFIG_EXTRA_ENV_SETTINGS \
	336	"mp_holdoff=1\0"
	337
	338	#else
	339
5bc0543d	340	#define CONFIG_HOSTNAME "controlcenterd"
b9944a77 DE	341	#define CONFIG_ROOTPATH "/opt/nfsroot"
	342	#define CONFIG_BOOTFILE "uImage"
	343	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
	344
	345	#define CONFIG_LOADADDR 1000000
	346
b9944a77 DE	347	#define CONFIG_EXTRA_ENV_SETTINGS \
	348	"netdev=eth0\0" \
	349	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	350	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	351	"tftpflash=tftpboot $loadaddr $uboot && " \
	352	"protect off $ubootaddr +$filesize && " \
	353	"erase $ubootaddr +$filesize && " \
	354	"cp.b $loadaddr $ubootaddr $filesize && " \
	355	"protect on $ubootaddr +$filesize && " \
	356	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	357	"consoledev=ttyS1\0" \
	358	"ramdiskaddr=2000000\0" \
	359	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	360	"fdtaddr=1e00000\0" \
b9944a77 DE	361	"fdtfile=controlcenterd.dtb\0" \
	362	"bdev=sda3\0"
	363
	364	/* these are used and NUL-terminated in env_default.h */
	365	#define CONFIG_NFSBOOTCOMMAND \
	366	"setenv bootargs root=/dev/nfs rw " \
	367	"nfsroot=$serverip:$rootpath " \
	368	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	369	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	370	"tftp $loadaddr $bootfile;" \
	371	"tftp $fdtaddr $fdtfile;" \
	372	"bootm $loadaddr - $fdtaddr"
	373
	374	#define CONFIG_RAMBOOTCOMMAND \
	375	"setenv bootargs root=/dev/ram rw " \
	376	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	377	"tftp $ramdiskaddr $ramdiskfile;" \
	378	"tftp $loadaddr $bootfile;" \
	379	"tftp $fdtaddr $fdtfile;" \
	380	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	381
	382	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	383
	384	#endif /* CONFIG_TRAILBLAZER */
	385
	386	#endif