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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
b29ca4a1 SR |
2 | /* |
3 | * Copyright (C) 2013 Stefan Roese <[email protected]> | |
4 | * | |
5 | * Configuration settings for the ProjectionDesign / Barco | |
6 | * Titanium board. | |
7 | * | |
8 | * Based on mx6qsabrelite.h which is: | |
9 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
b29ca4a1 SR |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
02824dc7 | 15 | #include "mx6_common.h" |
b29ca4a1 | 16 | |
b29ca4a1 | 17 | #define CONFIG_MX6Q |
b29ca4a1 | 18 | |
cd7b6344 TR |
19 | /* Provide the MACH_TYPE value that the vendor kernel requires. */ |
20 | #define CONFIG_MACH_TYPE 3769 | |
b29ca4a1 | 21 | |
b29ca4a1 SR |
22 | /* Size of malloc() pool */ |
23 | #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) | |
24 | ||
b29ca4a1 SR |
25 | #define CONFIG_MXC_UART |
26 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
27 | ||
28 | /* I2C Configs */ | |
b089d039 | 29 | #define CONFIG_SYS_I2C |
30 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
31 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
32 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 33 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
b29ca4a1 SR |
34 | #define CONFIG_SYS_I2C_SPEED 100000 |
35 | ||
36 | /* MMC Configs */ | |
b29ca4a1 SR |
37 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
38 | #define CONFIG_SYS_FSL_USDHC_NUM 1 | |
39 | ||
b29ca4a1 | 40 | #define CONFIG_FEC_MXC |
b29ca4a1 SR |
41 | #define IMX_FEC_BASE ENET_BASE_ADDR |
42 | #define CONFIG_FEC_XCV_TYPE RGMII | |
43 | #define CONFIG_FEC_MXC_PHYADDR 4 | |
b29ca4a1 SR |
44 | |
45 | /* USB Configs */ | |
b29ca4a1 SR |
46 | #define CONFIG_MXC_USB_PORT 1 |
47 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
48 | #define CONFIG_MXC_USB_FLAGS 0 | |
49 | ||
b29ca4a1 SR |
50 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
51 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20)) | |
52 | ||
5bc0543d | 53 | #define CONFIG_HOSTNAME "titanium" |
b29ca4a1 SR |
54 | #define CONFIG_UBI_PART ubi |
55 | #define CONFIG_UBIFS_VOLUME rootfs0 | |
56 | ||
b29ca4a1 | 57 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5bc0543d | 58 | "kernel=" CONFIG_HOSTNAME "/uImage\0" \ |
b29ca4a1 SR |
59 | "kernel_fs=/boot/uImage\0" \ |
60 | "kernel_addr=11000000\0" \ | |
5bc0543d MS |
61 | "dtb=" CONFIG_HOSTNAME "/" \ |
62 | CONFIG_HOSTNAME ".dtb\0" \ | |
63 | "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ | |
b29ca4a1 SR |
64 | "dtb_addr=12800000\0" \ |
65 | "script=boot.scr\0" \ | |
66 | "uimage=uImage\0" \ | |
67 | "console=ttymxc0\0" \ | |
68 | "baudrate=115200\0" \ | |
69 | "fdt_high=0xffffffff\0" \ | |
70 | "initrd_high=0xffffffff\0" \ | |
71 | "mmcdev=0\0" \ | |
72 | "mmcpart=1\0" \ | |
73 | "uimage=uImage\0" \ | |
74 | "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ | |
75 | " ${script}\0" \ | |
76 | "bootscript=echo Running bootscript from mmc ...; source\0" \ | |
77 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ | |
78 | "mmcroot=/dev/mmcblk0p2\0" \ | |
79 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
80 | "root=${mmcroot} rootwait rw\0" \ | |
81 | "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ | |
82 | " ${uimage}; bootm\0" \ | |
83 | "addip=setenv bootargs ${bootargs} " \ | |
84 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
85 | ":${hostname}:${netdev}:off panic=1\0" \ | |
86 | "addcon=setenv bootargs ${bootargs} console=ttymxc0," \ | |
87 | "${baudrate}\0" \ | |
88 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
89 | "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \ | |
90 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
91 | "nfsroot=${serverip}:${rootpath}\0" \ | |
5bc0543d | 92 | "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ |
b29ca4a1 SR |
93 | "part=" __stringify(CONFIG_UBI_PART) "\0" \ |
94 | "boot_vol=0\0" \ | |
95 | "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ | |
96 | "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ | |
97 | "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ | |
98 | " ${filesize}\0" \ | |
99 | "upd_ubifs=run load_ubifs update_ubifs\0" \ | |
100 | "init_ubi=nand erase.part ubi;ubi part ${part};" \ | |
101 | "ubi create ${vol} c800000\0" \ | |
43ede0bc TR |
102 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
103 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ | |
b29ca4a1 SR |
104 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ |
105 | " addcon addmtd;" \ | |
106 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
107 | "ubifsargs=set bootargs ubi.mtd=ubi " \ | |
108 | "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \ | |
109 | "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \ | |
110 | "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ | |
111 | "ubifsload ${dtb_addr} ${dtb_fs};\0" \ | |
112 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ | |
113 | "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
114 | "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ | |
115 | "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ | |
116 | "net_nfs=run load_dtb load_kernel; " \ | |
117 | "run nfsargs addip addcon addmtd;" \ | |
118 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
119 | "delenv=env default -a -f; saveenv; reset\0" | |
120 | ||
121 | #define CONFIG_BOOTCOMMAND "run nand_ubifs" | |
122 | ||
b29ca4a1 | 123 | /* Physical Memory Map */ |
b29ca4a1 SR |
124 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
125 | #define PHYS_SDRAM_SIZE (512 << 20) | |
126 | ||
127 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
128 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
129 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
130 | ||
131 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
132 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
133 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
134 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
135 | ||
b29ca4a1 | 136 | /* Enable NAND support */ |
b29ca4a1 SR |
137 | #ifdef CONFIG_CMD_NAND |
138 | ||
139 | /* NAND stuff */ | |
b29ca4a1 SR |
140 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
141 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
142 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
143 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
144 | ||
145 | /* DMA stuff, needed for GPMI/MXS NAND support */ | |
b29ca4a1 SR |
146 | |
147 | /* Environment in NAND */ | |
b29ca4a1 SR |
148 | #define CONFIG_ENV_OFFSET (16 << 20) |
149 | #define CONFIG_ENV_SECT_SIZE (128 << 10) | |
150 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
151 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) | |
152 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
153 | ||
154 | #else /* CONFIG_CMD_NAND */ | |
155 | ||
156 | /* Environment in MMC */ | |
157 | #define CONFIG_ENV_SIZE (8 << 10) | |
b29ca4a1 SR |
158 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
159 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
160 | ||
161 | #endif /* CONFIG_CMD_NAND */ | |
162 | ||
163 | /* UBI/UBIFS config options */ | |
b29ca4a1 | 164 | |
b29ca4a1 | 165 | #endif /* __CONFIG_H */ |