[J-u-boot.git] / cpu / mpc8260 / cpu.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code for the MPC8255 / MPC8260 CPUs
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <[email protected]>
 *
 * modified by
 * Wolfgang Denk <[email protected]>
 *
 * modified for 8260 by
 * Murray Jensen <[email protected]>
 *
 * added 8260 masks by
 * Marius Groeger <[email protected]>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8260.h>
#include <asm/processor.h>
#include <asm/cpm_8260.h>

int checkcpu (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	ulong clock = gd->cpu_clk;
	uint pvr = get_pvr ();
	uint immr, rev, m, k;
	char buf[32];

	puts ("CPU:   ");

	if (((pvr >> 16) & 0xff) != 0x81)
		return -1;	/* whoops! not an MPC8260 */
	rev = pvr & 0xff;

	immr = immap->im_memctl.memc_immr;
	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
		return -1;	/* whoops! someone moved the IMMR */

	printf (CPU_ID_STR " (Rev %02x, Mask ", rev);

	/*
	 * the bottom 16 bits of the immr are the Part Number and Mask Number
	 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
	 * RISC Microcode Revision Number (13-10).
	 * For the 8260, Motorola doesn't include the Microcode Revision
	 * in the mask.
	 */
	m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
	k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);

	switch (m) {
	case 0x0000:
		printf ("0.2 2J24M");
		break;
	case 0x0010:
		printf ("A.0 K22A");
		break;
	case 0x0011:
		printf ("A.1 1K22A-XC");
		break;
	case 0x0001:
		printf ("B.1 1K23A");
		break;
	case 0x0021:
		printf ("B.2 2K23A-XC");
		break;
	case 0x0023:
		printf ("B.3 3K23A");
		break;
	case 0x0024:
		printf ("C.2 6K23A");
		break;
	case 0x0060:
		printf ("A.0(A) 2K25A");
		break;
	case 0x0062:
		printf ("B.1 4K25A");
		break;
	default:
		printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
		break;
	}

	printf (") at %s MHz\n", strmhz (buf, clock));

	return 0;
}

/* ------------------------------------------------------------------------- */
/* configures a UPM by writing into the UPM RAM array			     */
/* uses bank 11 and a dummy physical address (=BRx_BA_MSK)		     */
/* NOTE: the physical address chosen must not overlap into any other area    */
/* mapped by the memory controller because bank 11 has the lowest priority   */

void upmconfig (uint upm, uint * table, uint size)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	volatile uchar *dummy = (uchar *) BRx_BA_MSK;	/* set all BA bits */
	uint i;

	/* first set up bank 11 to reference the correct UPM at a dummy address */

	memctl->memc_or11 = ORxU_AM_MSK;	/* set all AM bits */

	switch (upm) {

	case UPMA:
		memctl->memc_br11 =
			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
			BRx_V;
		memctl->memc_mamr = MxMR_OP_WARR;
		break;

	case UPMB:
		memctl->memc_br11 =
			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
			BRx_V;
		memctl->memc_mbmr = MxMR_OP_WARR;
		break;

	case UPMC:
		memctl->memc_br11 =
			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
			BRx_V;
		memctl->memc_mcmr = MxMR_OP_WARR;
		break;

	default:
		panic ("upmconfig passed invalid UPM number (%u)\n", upm);
		break;

	}

	/*
	 * at this point, the dummy address is set up to access the selected UPM,
	 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
	 *
	 * now we simply load the mdr with each word and poke the dummy address.
	 * the MAD is incremented on each access.
	 */

	for (i = 0; i < size; i++) {
		memctl->memc_mdr = table[i];
		*dummy = 0;
	}

	/* now kill bank 11 */
	memctl->memc_br11 = 0;
}

/* ------------------------------------------------------------------------- */

int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	ulong msr, addr;

	volatile immap_t *immap = (immap_t *) CFG_IMMR;

	immap->im_clkrst.car_rmr = RMR_CSRE;	/* Checkstop Reset enable */

	/* Interrupts and MMU off */
	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);

	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

	/*
	 * Trying to execute the next instruction at a non-existing address
	 * should cause a machine check, resulting in reset
	 */
#ifdef CFG_RESET_ADDRESS
	addr = CFG_RESET_ADDRESS;
#else
	/*
	 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
	 * - sizeof (ulong) is usually a valid address. Better pick an address
	 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
	 */
	addr = CFG_MONITOR_BASE - sizeof (ulong);
#endif
	((void (*)(void)) addr) ();
	return 1;

}

/* ------------------------------------------------------------------------- */

/*
 * Get timebase clock frequency (like cpu_clk in Hz)
 *
 */
unsigned long get_tbclk (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	ulong tbclk;

	tbclk = (gd->bus_clk + 3L) / 4L;

	return (tbclk);
}

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
	int re_enable = disable_interrupts ();

	reset_8260_watchdog ((immap_t *) CFG_IMMR);
	if (re_enable)
		enable_interrupts ();
}
#endif /* CONFIG_WATCHDOG */

/* ------------------------------------------------------------------------- */
Commit	Line	Data
4a9cbbe8	1	/*
4532cb69	2	* (C) Copyright 2000-2003
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
4532cb69	25	* CPU specific code for the MPC8255 / MPC8260 CPUs
4a9cbbe8 WD	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <[email protected]>
	29	*
4532cb69	30	* modified by
4a9cbbe8 WD	31	* Wolfgang Denk <[email protected]>
	32	*
	33	* modified for 8260 by
	34	* Murray Jensen <[email protected]>
	35	*
	36	* added 8260 masks by
	37	* Marius Groeger <[email protected]>
	38	*/
	39
	40	#include <common.h>
	41	#include <watchdog.h>
	42	#include <command.h>
	43	#include <mpc8260.h>
	44	#include <asm/processor.h>
	45	#include <asm/cpm_8260.h>
	46
	47	int checkcpu (void)
	48	{
	49	DECLARE_GLOBAL_DATA_PTR;
	50
	51	volatile immap_t immap = (immap_t ) CFG_IMMR;
	52	ulong clock = gd->cpu_clk;
	53	uint pvr = get_pvr ();
	54	uint immr, rev, m, k;
	55	char buf[32];
	56
	57	puts ("CPU: ");
	58
	59	if (((pvr >> 16) & 0xff) != 0x81)
	60	return -1; /* whoops! not an MPC8260 */
	61	rev = pvr & 0xff;
	62
	63	immr = immap->im_memctl.memc_immr;
	64	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
	65	return -1; /* whoops! someone moved the IMMR */
	66
4532cb69	67	printf (CPU_ID_STR " (Rev %02x, Mask ", rev);
4a9cbbe8 WD	68
	69	/*
	70	* the bottom 16 bits of the immr are the Part Number and Mask Number
	71	* (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
	72	* RISC Microcode Revision Number (13-10).
	73	* For the 8260, Motorola doesn't include the Microcode Revision
	74	* in the mask.
	75	*/
	76	m = immr & (IMMR_PARTNUM_MSK \| IMMR_MASKNUM_MSK);
	77	k = ((ushort ) & immap->im_dprambase[PROFF_REVNUM]);
	78
	79	switch (m) {
	80	case 0x0000:
	81	printf ("0.2 2J24M");
	82	break;
	83	case 0x0010:
	84	printf ("A.0 K22A");
	85	break;
	86	case 0x0011:
	87	printf ("A.1 1K22A-XC");
	88	break;
	89	case 0x0001:
	90	printf ("B.1 1K23A");
	91	break;
	92	case 0x0021:
	93	printf ("B.2 2K23A-XC");
	94	break;
	95	case 0x0023:
	96	printf ("B.3 3K23A");
	97	break;
	98	case 0x0024:
	99	printf ("C.2 6K23A");
	100	break;
	101	case 0x0060:
	102	printf ("A.0(A) 2K25A");
	103	break;
4532cb69 WD	104	case 0x0062:
	105	printf ("B.1 4K25A");
	106	break;
4a9cbbe8 WD	107	default:
	108	printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
	109	break;
	110	}
	111
	112	printf (") at %s MHz\n", strmhz (buf, clock));
	113
	114	return 0;
	115	}
	116
	117	/* ------------------------------------------------------------------------- */
	118	/* configures a UPM by writing into the UPM RAM array */
	119	/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
	120	/* NOTE: the physical address chosen must not overlap into any other area */
	121	/* mapped by the memory controller because bank 11 has the lowest priority */
	122
	123	void upmconfig (uint upm, uint * table, uint size)
	124	{
	125	volatile immap_t immap = (immap_t ) CFG_IMMR;
	126	volatile memctl8260_t *memctl = &immap->im_memctl;
	127	volatile uchar dummy = (uchar ) BRx_BA_MSK; /* set all BA bits */
	128	uint i;
	129
	130	/* first set up bank 11 to reference the correct UPM at a dummy address */
	131
	132	memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
	133
	134	switch (upm) {
	135
	136	case UPMA:
	137	memctl->memc_br11 =
	138	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMA \|
	139	BRx_V;
	140	memctl->memc_mamr = MxMR_OP_WARR;
	141	break;
	142
	143	case UPMB:
	144	memctl->memc_br11 =
	145	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMB \|
	146	BRx_V;
	147	memctl->memc_mbmr = MxMR_OP_WARR;
	148	break;
	149
	150	case UPMC:
	151	memctl->memc_br11 =
	152	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMC \|
	153	BRx_V;
	154	memctl->memc_mcmr = MxMR_OP_WARR;
	155	break;
	156
	157	default:
	158	panic ("upmconfig passed invalid UPM number (%u)\n", upm);
	159	break;
	160
	161	}
	162
	163	/*
	164	* at this point, the dummy address is set up to access the selected UPM,
	165	* the MAD pointer is zero, and the MxMR OP is set for writing to RAM
	166	*
	167	* now we simply load the mdr with each word and poke the dummy address.
	168	* the MAD is incremented on each access.
	169	*/
	170
171	for (i = 0; i < size; i++) {
172	memctl->memc_mdr = table[i];
173	*dummy = 0;
174	}
175
176	/* now kill bank 11 */
177	memctl->memc_br11 = 0;
178	}
179
180	/* ------------------------------------------------------------------------- */
181
182	int
8bde7f77	183	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
4a9cbbe8 WD	184	{
	185	ulong msr, addr;
	186
	187	volatile immap_t immap = (immap_t ) CFG_IMMR;
	188
	189	immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
	190
	191	/* Interrupts and MMU off */
	192	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
	193
	194	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);
	195	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
	196
	197	/*
	198	* Trying to execute the next instruction at a non-existing address
	199	* should cause a machine check, resulting in reset
	200	*/
	201	#ifdef CFG_RESET_ADDRESS
	202	addr = CFG_RESET_ADDRESS;
	203	#else
	204	/*
	205	* note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
	206	* - sizeof (ulong) is usually a valid address. Better pick an address
	207	* known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
	208	*/
	209	addr = CFG_MONITOR_BASE - sizeof (ulong);
	210	#endif
	211	((void (*)(void)) addr) ();
	212	return 1;
	213
	214	}
	215
	216	/* ------------------------------------------------------------------------- */
	217
	218	/*
	219	* Get timebase clock frequency (like cpu_clk in Hz)
	220	*
	221	*/
	222	unsigned long get_tbclk (void)
	223	{
	224	DECLARE_GLOBAL_DATA_PTR;
	225
	226	ulong tbclk;
	227
	228	tbclk = (gd->bus_clk + 3L) / 4L;
	229
	230	return (tbclk);
	231	}
	232
	233	/* ------------------------------------------------------------------------- */
	234
	235	#if defined(CONFIG_WATCHDOG)
	236	void watchdog_reset (void)
	237	{
	238	int re_enable = disable_interrupts ();
	239
	240	reset_8260_watchdog ((immap_t *) CFG_IMMR);
	241	if (re_enable)
	242	enable_interrupts ();
	243	}
	244	#endif /* CONFIG_WATCHDOG */
	245
	246	/* ------------------------------------------------------------------------- */