[J-u-boot.git] / drivers / video / tegra.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2011 The Chromium OS Authors.
 */

#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <panel.h>
#include <part.h>
#include <pwm.h>
#include <video.h>
#include <asm/cache.h>
#include <asm/system.h>
#include <asm/gpio.h>
#include <asm/io.h>

#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pwm.h>
#include <asm/arch/display.h>
#include <asm/arch-tegra/timer.h>

DECLARE_GLOBAL_DATA_PTR;

/* Information about the display controller */
struct tegra_lcd_priv {
	int width;			/* width in pixels */
	int height;			/* height in pixels */
	enum video_log2_bpp log2_bpp;	/* colour depth */
	struct display_timing timing;
	struct udevice *panel;
	struct disp_ctlr *disp;		/* Display controller to use */
	fdt_addr_t frame_buffer;	/* Address of frame buffer */
	unsigned pixel_clock;		/* Pixel clock in Hz */
};

enum {
	/* Maximum LCD size we support */
	LCD_MAX_WIDTH		= 1366,
	LCD_MAX_HEIGHT		= 768,
	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
};

static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
{
	unsigned h_dda, v_dda;
	unsigned long val;

	val = readl(&dc->cmd.disp_win_header);
	val |= WINDOW_A_SELECT;
	writel(val, &dc->cmd.disp_win_header);

	writel(win->fmt, &dc->win.color_depth);

	clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
			BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);

	val = win->out_x << H_POSITION_SHIFT;
	val |= win->out_y << V_POSITION_SHIFT;
	writel(val, &dc->win.pos);

	val = win->out_w << H_SIZE_SHIFT;
	val |= win->out_h << V_SIZE_SHIFT;
	writel(val, &dc->win.size);

	val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
	val |= win->h << V_PRESCALED_SIZE_SHIFT;
	writel(val, &dc->win.prescaled_size);

	writel(0, &dc->win.h_initial_dda);
	writel(0, &dc->win.v_initial_dda);

	h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
	v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);

	val = h_dda << H_DDA_INC_SHIFT;
	val |= v_dda << V_DDA_INC_SHIFT;
	writel(val, &dc->win.dda_increment);

	writel(win->stride, &dc->win.line_stride);
	writel(0, &dc->win.buf_stride);

	val = WIN_ENABLE;
	if (win->bpp < 24)
		val |= COLOR_EXPAND;
	writel(val, &dc->win.win_opt);

	writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
	writel(win->x, &dc->winbuf.addr_h_offset);
	writel(win->y, &dc->winbuf.addr_v_offset);

	writel(0xff00, &dc->win.blend_nokey);
	writel(0xff00, &dc->win.blend_1win);

	val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
	val |= GENERAL_UPDATE | WIN_A_UPDATE;
	writel(val, &dc->cmd.state_ctrl);
}

static int update_display_mode(struct dc_disp_reg *disp,
			       struct tegra_lcd_priv *priv)
{
	struct display_timing *dt = &priv->timing;
	unsigned long val;
	unsigned long rate;
	unsigned long div;

	writel(0x0, &disp->disp_timing_opt);

	writel(1 | 1 << 16, &disp->ref_to_sync);
	writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
	writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
	       &disp->back_porch);
	writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
	       &disp->front_porch);
	writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);

	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
	val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
	writel(val, &disp->data_enable_opt);

	val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
	val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
	val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
	writel(val, &disp->disp_interface_ctrl);

	/*
	 * The pixel clock divider is in 7.1 format (where the bottom bit
	 * represents 0.5). Here we calculate the divider needed to get from
	 * the display clock (typically 600MHz) to the pixel clock. We round
	 * up or down as requried.
	 */
	rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
	div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
	debug("Display clock %lu, divider %lu\n", rate, div);

	writel(0x00010001, &disp->shift_clk_opt);

	val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
	val |= div << SHIFT_CLK_DIVIDER_SHIFT;
	writel(val, &disp->disp_clk_ctrl);

	return 0;
}

/* Start up the display and turn on power to PWMs */
static void basic_init(struct dc_cmd_reg *cmd)
{
	u32 val;

	writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
	writel(0x0000011a, &cmd->cont_syncpt_vsync);
	writel(0x00000000, &cmd->int_type);
	writel(0x00000000, &cmd->int_polarity);
	writel(0x00000000, &cmd->int_mask);
	writel(0x00000000, &cmd->int_enb);

	val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
	val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
	val |= PM1_ENABLE;
	writel(val, &cmd->disp_pow_ctrl);

	val = readl(&cmd->disp_cmd);
	val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
	writel(val, &cmd->disp_cmd);
}

static void basic_init_timer(struct dc_disp_reg *disp)
{
	writel(0x00000020, &disp->mem_high_pri);
	writel(0x00000001, &disp->mem_high_pri_timer);
}

static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
};

static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
	0x00000000,
	0x01000000,
	0x00000000,
	0x00000000,
};

static const u32 rgb_data_tab[PIN_REG_COUNT] = {
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
};

static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00210222,
	0x00002200,
	0x00020000,
};

static void rgb_enable(struct dc_com_reg *com)
{
	int i;

	for (i = 0; i < PIN_REG_COUNT; i++) {
		writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
		writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
		writel(rgb_data_tab[i], &com->pin_output_data[i]);
	}

	for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
		writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}

static int setup_window(struct disp_ctl_win *win,
			struct tegra_lcd_priv *priv)
{
	win->x = 0;
	win->y = 0;
	win->w = priv->width;
	win->h = priv->height;
	win->out_x = 0;
	win->out_y = 0;
	win->out_w = priv->width;
	win->out_h = priv->height;
	win->phys_addr = priv->frame_buffer;
	win->stride = priv->width * (1 << priv->log2_bpp) / 8;
	debug("%s: depth = %d\n", __func__, priv->log2_bpp);
	switch (priv->log2_bpp) {
	case VIDEO_BPP32:
		win->fmt = COLOR_DEPTH_R8G8B8A8;
		win->bpp = 32;
		break;
	case VIDEO_BPP16:
		win->fmt = COLOR_DEPTH_B5G6R5;
		win->bpp = 16;
		break;

	default:
		debug("Unsupported LCD bit depth");
		return -1;
	}

	return 0;
}

/**
 * Register a new display based on device tree configuration.
 *
 * The frame buffer can be positioned by U-Boot or overridden by the fdt.
 * You should pass in the U-Boot address here, and check the contents of
 * struct tegra_lcd_priv to see what was actually chosen.
 *
 * @param blob			Device tree blob
 * @param priv			Driver's private data
 * @param default_lcd_base	Default address of LCD frame buffer
 * @return 0 if ok, -1 on error (unsupported bits per pixel)
 */
static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
			       void *default_lcd_base)
{
	struct disp_ctl_win window;
	struct dc_ctlr *dc;

	priv->frame_buffer = (u32)default_lcd_base;

	dc = (struct dc_ctlr *)priv->disp;

	/*
	 * A header file for clock constants was NAKed upstream.
	 * TODO: Put this into the FDT and fdt_lcd struct when we have clock
	 * support there
	 */
	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
			       144 * 1000000);
	clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
			       600 * 1000000);
	basic_init(&dc->cmd);
	basic_init_timer(&dc->disp);
	rgb_enable(&dc->com);

	if (priv->pixel_clock)
		update_display_mode(&dc->disp, priv);

	if (setup_window(&window, priv))
		return -1;

	update_window(dc, &window);

	return 0;
}

static int tegra_lcd_probe(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	struct tegra_lcd_priv *priv = dev_get_priv(dev);
	const void *blob = gd->fdt_blob;
	int ret;

	/* Initialize the Tegra display controller */
	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
	if (tegra_display_probe(blob, priv, (void *)plat->base)) {
		printf("%s: Failed to probe display driver\n", __func__);
		return -1;
	}

	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
	pinmux_tristate_disable(PMUX_PINGRP_GPU);

	ret = panel_enable_backlight(priv->panel);
	if (ret) {
		debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
		return ret;
	}

	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
					DCACHE_WRITETHROUGH);

	/* Enable flushing after LCD writes if requested */
	video_set_flush_dcache(dev, true);

	uc_priv->xsize = priv->width;
	uc_priv->ysize = priv->height;
	uc_priv->bpix = priv->log2_bpp;
	debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
	      plat->size);

	return 0;
}

static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
{
	struct tegra_lcd_priv *priv = dev_get_priv(dev);
	const void *blob = gd->fdt_blob;
	struct display_timing *timing;
	int node = dev_of_offset(dev);
	int panel_node;
	int rgb;
	int ret;

	priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
	if (!priv->disp) {
		debug("%s: No display controller address\n", __func__);
		return -EINVAL;
	}

	rgb = fdt_subnode_offset(blob, node, "rgb");
	if (rgb < 0) {
		debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
		      __func__, dev->name, rgb);
		return -EINVAL;
	}

	ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
	if (ret) {
		debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
		      __func__, dev->name, ret);
		return -EINVAL;
	}
	timing = &priv->timing;
	priv->width = timing->hactive.typ;
	priv->height = timing->vactive.typ;
	priv->pixel_clock = timing->pixelclock.typ;
	priv->log2_bpp = VIDEO_BPP16;

	/*
	 * Sadly the panel phandle is in an rgb subnode so we cannot use
	 * uclass_get_device_by_phandle().
	 */
	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
	if (panel_node < 0) {
		debug("%s: Cannot find panel information\n", __func__);
		return -EINVAL;
	}
	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
					     &priv->panel);
	if (ret) {
		debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
		      dev->name, ret);
		return ret;
	}

	return 0;
}

static int tegra_lcd_bind(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	int rgb;

	rgb = fdt_subnode_offset(blob, node, "rgb");
	if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
		return -ENODEV;

	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
		(1 << LCD_MAX_LOG2_BPP) / 8;

	return 0;
}

static const struct video_ops tegra_lcd_ops = {
};

static const struct udevice_id tegra_lcd_ids[] = {
	{ .compatible = "nvidia,tegra20-dc" },
	{ }
};

U_BOOT_DRIVER(tegra_lcd) = {
	.name	= "tegra_lcd",
	.id	= UCLASS_VIDEO,
	.of_match = tegra_lcd_ids,
	.ops	= &tegra_lcd_ops,
	.bind	= tegra_lcd_bind,
	.probe	= tegra_lcd_probe,
	.ofdata_to_platdata	= tegra_lcd_ofdata_to_platdata,
	.priv_auto_alloc_size	= sizeof(struct tegra_lcd_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
0be8f203 SG	2	/*
0be8f203 SG	3	* Copyright (c) 2011 The Chromium OS Authors.
0be8f203	4	*/
f20b2c06	5
0be8f203	6	#include <common.h>
9e6866d3	7	#include <dm.h>
0be8f203	8	#include <fdtdec.h>
f7ae49fc	9	#include <log.h>
ec550770	10	#include <panel.h>
e6f6f9e6	11	#include <part.h>
91c08afe	12	#include <pwm.h>
9e6866d3	13	#include <video.h>
90526e9f	14	#include <asm/cache.h>
0be8f203 SG	15	#include <asm/system.h>
0be8f203 SG	16	#include <asm/gpio.h>
71cafc3f	17	#include <asm/io.h>
0be8f203 SG	18
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/funcmux.h>
	21	#include <asm/arch/pinmux.h>
	22	#include <asm/arch/pwm.h>
	23	#include <asm/arch/display.h>
	24	#include <asm/arch-tegra/timer.h>
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
ce0c474a SG	28	/* Information about the display controller */
ce0c474a SG	29	struct tegra_lcd_priv {
ce0c474a SG	30	int width; /* width in pixels */
ce0c474a SG	31	int height; /* height in pixels */
ec550770 SG	32	enum video_log2_bpp log2_bpp; /* colour depth */
	33	struct display_timing timing;
	34	struct udevice *panel;
ce0c474a SG	35	struct disp_ctlr disp; / Display controller to use */
	36	fdt_addr_t frame_buffer; /* Address of frame buffer */
	37	unsigned pixel_clock; /* Pixel clock in Hz */
ce0c474a SG	38	};
ce0c474a SG	39
0be8f203 SG	40	enum {
	41	/* Maximum LCD size we support */
	42	LCD_MAX_WIDTH = 1366,
	43	LCD_MAX_HEIGHT = 768,
9e6866d3	44	LCD_MAX_LOG2_BPP = VIDEO_BPP16,
0be8f203 SG	45	};
0be8f203 SG	46
71cafc3f SG	47	static void update_window(struct dc_ctlr dc, struct disp_ctl_win win)
	48	{
	49	unsigned h_dda, v_dda;
	50	unsigned long val;
	51
	52	val = readl(&dc->cmd.disp_win_header);
	53	val \|= WINDOW_A_SELECT;
	54	writel(val, &dc->cmd.disp_win_header);
	55
	56	writel(win->fmt, &dc->win.color_depth);
	57
	58	clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
	59	BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
	60
	61	val = win->out_x << H_POSITION_SHIFT;
	62	val \|= win->out_y << V_POSITION_SHIFT;
	63	writel(val, &dc->win.pos);
	64
	65	val = win->out_w << H_SIZE_SHIFT;
	66	val \|= win->out_h << V_SIZE_SHIFT;
	67	writel(val, &dc->win.size);
	68
	69	val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
	70	val \|= win->h << V_PRESCALED_SIZE_SHIFT;
	71	writel(val, &dc->win.prescaled_size);
	72
	73	writel(0, &dc->win.h_initial_dda);
	74	writel(0, &dc->win.v_initial_dda);
	75
	76	h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
	77	v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
	78
	79	val = h_dda << H_DDA_INC_SHIFT;
	80	val \|= v_dda << V_DDA_INC_SHIFT;
	81	writel(val, &dc->win.dda_increment);
	82
	83	writel(win->stride, &dc->win.line_stride);
	84	writel(0, &dc->win.buf_stride);
	85
	86	val = WIN_ENABLE;
	87	if (win->bpp < 24)
	88	val \|= COLOR_EXPAND;
	89	writel(val, &dc->win.win_opt);
	90
	91	writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
	92	writel(win->x, &dc->winbuf.addr_h_offset);
	93	writel(win->y, &dc->winbuf.addr_v_offset);
	94
	95	writel(0xff00, &dc->win.blend_nokey);
	96	writel(0xff00, &dc->win.blend_1win);
	97
	98	val = GENERAL_ACT_REQ \| WIN_A_ACT_REQ;
	99	val \|= GENERAL_UPDATE \| WIN_A_UPDATE;
	100	writel(val, &dc->cmd.state_ctrl);
	101	}
	102
71cafc3f	103	static int update_display_mode(struct dc_disp_reg *disp,
9e6866d3	104	struct tegra_lcd_priv *priv)
71cafc3f	105	{
ec550770	106	struct display_timing *dt = &priv->timing;
71cafc3f SG	107	unsigned long val;
	108	unsigned long rate;
	109	unsigned long div;
	110
	111	writel(0x0, &disp->disp_timing_opt);
71cafc3f	112
ec550770 SG	113	writel(1 \| 1 << 16, &disp->ref_to_sync);
	114	writel(dt->hsync_len.typ \| dt->vsync_len.typ << 16, &disp->sync_width);
	115	writel(dt->hback_porch.typ \| dt->vback_porch.typ << 16,
	116	&disp->back_porch);
	117	writel((dt->hfront_porch.typ - 1) \| (dt->vfront_porch.typ - 1) << 16,
	118	&disp->front_porch);
	119	writel(dt->hactive.typ \| (dt->vactive.typ << 16), &disp->disp_active);
71cafc3f SG	120
	121	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
	122	val \|= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
	123	writel(val, &disp->data_enable_opt);
	124
	125	val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
	126	val \|= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
	127	val \|= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
	128	writel(val, &disp->disp_interface_ctrl);
	129
	130	/*
	131	* The pixel clock divider is in 7.1 format (where the bottom bit
	132	* represents 0.5). Here we calculate the divider needed to get from
	133	* the display clock (typically 600MHz) to the pixel clock. We round
	134	* up or down as requried.
	135	*/
	136	rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
9e6866d3	137	div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
71cafc3f SG	138	debug("Display clock %lu, divider %lu\n", rate, div);
	139
	140	writel(0x00010001, &disp->shift_clk_opt);
	141
	142	val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
	143	val \|= div << SHIFT_CLK_DIVIDER_SHIFT;
	144	writel(val, &disp->disp_clk_ctrl);
	145
	146	return 0;
	147	}
	148
	149	/* Start up the display and turn on power to PWMs */
	150	static void basic_init(struct dc_cmd_reg *cmd)
	151	{
	152	u32 val;
	153
	154	writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
	155	writel(0x0000011a, &cmd->cont_syncpt_vsync);
	156	writel(0x00000000, &cmd->int_type);
	157	writel(0x00000000, &cmd->int_polarity);
	158	writel(0x00000000, &cmd->int_mask);
	159	writel(0x00000000, &cmd->int_enb);
	160
	161	val = PW0_ENABLE \| PW1_ENABLE \| PW2_ENABLE;
	162	val \|= PW3_ENABLE \| PW4_ENABLE \| PM0_ENABLE;
	163	val \|= PM1_ENABLE;
	164	writel(val, &cmd->disp_pow_ctrl);
	165
	166	val = readl(&cmd->disp_cmd);
	167	val \|= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
	168	writel(val, &cmd->disp_cmd);
	169	}
	170
	171	static void basic_init_timer(struct dc_disp_reg *disp)
	172	{
	173	writel(0x00000020, &disp->mem_high_pri);
	174	writel(0x00000001, &disp->mem_high_pri_timer);
	175	}
	176
	177	static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
	178	0x00000000,
	179	0x00000000,
	180	0x00000000,
	181	0x00000000,
	182	};
	183
	184	static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
	185	0x00000000,
	186	0x01000000,
	187	0x00000000,
	188	0x00000000,
	189	};
	190
	191	static const u32 rgb_data_tab[PIN_REG_COUNT] = {
	192	0x00000000,
	193	0x00000000,
	194	0x00000000,
	195	0x00000000,
	196	};
	197
	198	static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
	199	0x00000000,
	200	0x00000000,
	201	0x00000000,
202	0x00000000,
203	0x00210222,
204	0x00002200,
205	0x00020000,
206	};
207
208	static void rgb_enable(struct dc_com_reg *com)
209	{
210	int i;
211
212	for (i = 0; i < PIN_REG_COUNT; i++) {
213	writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
214	writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
215	writel(rgb_data_tab[i], &com->pin_output_data[i]);
216	}
217
218	for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
219	writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
220	}
221
222	static int setup_window(struct disp_ctl_win *win,
9e6866d3	223	struct tegra_lcd_priv *priv)
71cafc3f SG	224	{
	225	win->x = 0;
	226	win->y = 0;
9e6866d3 SG	227	win->w = priv->width;
9e6866d3 SG	228	win->h = priv->height;
71cafc3f SG	229	win->out_x = 0;
71cafc3f SG	230	win->out_y = 0;
9e6866d3 SG	231	win->out_w = priv->width;
	232	win->out_h = priv->height;
	233	win->phys_addr = priv->frame_buffer;
	234	win->stride = priv->width * (1 << priv->log2_bpp) / 8;
	235	debug("%s: depth = %d\n", __func__, priv->log2_bpp);
	236	switch (priv->log2_bpp) {
ec550770	237	case VIDEO_BPP32:
71cafc3f SG	238	win->fmt = COLOR_DEPTH_R8G8B8A8;
	239	win->bpp = 32;
	240	break;
ec550770	241	case VIDEO_BPP16:
71cafc3f SG	242	win->fmt = COLOR_DEPTH_B5G6R5;
	243	win->bpp = 16;
	244	break;
	245
	246	default:
	247	debug("Unsupported LCD bit depth");
	248	return -1;
	249	}
	250
	251	return 0;
	252	}
	253
71cafc3f SG	254	/**
	255	* Register a new display based on device tree configuration.
	256	*
62a3b7dd	257	* The frame buffer can be positioned by U-Boot or overridden by the fdt.
71cafc3f	258	* You should pass in the U-Boot address here, and check the contents of
ce0c474a	259	* struct tegra_lcd_priv to see what was actually chosen.
71cafc3f SG	260	*
71cafc3f SG	261	* @param blob Device tree blob
9e6866d3	262	* @param priv Driver's private data
71cafc3f SG	263	* @param default_lcd_base Default address of LCD frame buffer
	264	* @return 0 if ok, -1 on error (unsupported bits per pixel)
	265	*/
9e6866d3 SG	266	static int tegra_display_probe(const void blob, struct tegra_lcd_priv priv,
9e6866d3 SG	267	void *default_lcd_base)
71cafc3f SG	268	{
	269	struct disp_ctl_win window;
	270	struct dc_ctlr *dc;
	271
9e6866d3	272	priv->frame_buffer = (u32)default_lcd_base;
71cafc3f	273
9e6866d3	274	dc = (struct dc_ctlr *)priv->disp;
71cafc3f SG	275
	276	/*
	277	* A header file for clock constants was NAKed upstream.
	278	* TODO: Put this into the FDT and fdt_lcd struct when we have clock
	279	* support there
	280	*/
	281	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
	282	144 * 1000000);
	283	clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
	284	600 * 1000000);
	285	basic_init(&dc->cmd);
	286	basic_init_timer(&dc->disp);
	287	rgb_enable(&dc->com);
	288
9e6866d3 SG	289	if (priv->pixel_clock)
9e6866d3 SG	290	update_display_mode(&dc->disp, priv);
71cafc3f	291
9e6866d3	292	if (setup_window(&window, priv))
71cafc3f SG	293	return -1;
	294
	295	update_window(dc, &window);
	296
	297	return 0;
	298	}
	299
9e6866d3	300	static int tegra_lcd_probe(struct udevice *dev)
0be8f203	301	{
9e6866d3 SG	302	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	303	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	304	struct tegra_lcd_priv *priv = dev_get_priv(dev);
	305	const void *blob = gd->fdt_blob;
ec550770	306	int ret;
9e6866d3	307
9e6866d3	308	/* Initialize the Tegra display controller */
ec550770	309	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
9e6866d3 SG	310	if (tegra_display_probe(blob, priv, (void *)plat->base)) {
	311	printf("%s: Failed to probe display driver\n", __func__);
	312	return -1;
0be8f203	313	}
9e6866d3	314
ec550770 SG	315	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
	316	pinmux_tristate_disable(PMUX_PINGRP_GPU);
	317
	318	ret = panel_enable_backlight(priv->panel);
	319	if (ret) {
	320	debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
	321	return ret;
	322	}
9e6866d3	323
8d37483e SG	324	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
8d37483e SG	325	DCACHE_WRITETHROUGH);
9e6866d3 SG	326
9e6866d3 SG	327	/* Enable flushing after LCD writes if requested */
8d37483e	328	video_set_flush_dcache(dev, true);
9e6866d3 SG	329
	330	uc_priv->xsize = priv->width;
	331	uc_priv->ysize = priv->height;
	332	uc_priv->bpix = priv->log2_bpp;
	333	debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
	334	plat->size);
	335
	336	return 0;
	337	}
	338
f5acf91f SG	339	static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
	340	{
	341	struct tegra_lcd_priv *priv = dev_get_priv(dev);
	342	const void *blob = gd->fdt_blob;
ec550770	343	struct display_timing *timing;
e160f7d4	344	int node = dev_of_offset(dev);
f5acf91f SG	345	int panel_node;
f5acf91f SG	346	int rgb;
91c08afe	347	int ret;
f5acf91f	348
a821c4af	349	priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
f5acf91f SG	350	if (!priv->disp) {
	351	debug("%s: No display controller address\n", __func__);
	352	return -EINVAL;
	353	}
	354
	355	rgb = fdt_subnode_offset(blob, node, "rgb");
ec550770 SG	356	if (rgb < 0) {
	357	debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
	358	__func__, dev->name, rgb);
f5acf91f SG	359	return -EINVAL;
	360	}
	361
ec550770 SG	362	ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
	363	if (ret) {
	364	debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
	365	__func__, dev->name, ret);
f5acf91f SG	366	return -EINVAL;
f5acf91f SG	367	}
ec550770 SG	368	timing = &priv->timing;
	369	priv->width = timing->hactive.typ;
	370	priv->height = timing->vactive.typ;
	371	priv->pixel_clock = timing->pixelclock.typ;
	372	priv->log2_bpp = VIDEO_BPP16;
f5acf91f	373
ec550770 SG	374	/*
	375	* Sadly the panel phandle is in an rgb subnode so we cannot use
	376	* uclass_get_device_by_phandle().
	377	*/
	378	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
	379	if (panel_node < 0) {
	380	debug("%s: Cannot find panel information\n", __func__);
f5acf91f SG	381	return -EINVAL;
f5acf91f SG	382	}
ec550770 SG	383	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
ec550770 SG	384	&priv->panel);
91c08afe	385	if (ret) {
ec550770 SG	386	debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
	387	dev->name, ret);
	388	return ret;
91c08afe	389	}
f5acf91f SG	390
	391	return 0;
	392	}
	393
9e6866d3 SG	394	static int tegra_lcd_bind(struct udevice *dev)
	395	{
	396	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
54693cbd	397	const void *blob = gd->fdt_blob;
e160f7d4	398	int node = dev_of_offset(dev);
54693cbd SW	399	int rgb;
	400
	401	rgb = fdt_subnode_offset(blob, node, "rgb");
	402	if ((rgb < 0) \|\| !fdtdec_get_is_enabled(blob, rgb))
	403	return -ENODEV;
9e6866d3 SG	404
	405	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
	406	(1 << LCD_MAX_LOG2_BPP) / 8;
	407
	408	return 0;
0be8f203	409	}
9e6866d3 SG	410
	411	static const struct video_ops tegra_lcd_ops = {
	412	};
	413
	414	static const struct udevice_id tegra_lcd_ids[] = {
	415	{ .compatible = "nvidia,tegra20-dc" },
	416	{ }
	417	};
	418
	419	U_BOOT_DRIVER(tegra_lcd) = {
	420	.name = "tegra_lcd",
	421	.id = UCLASS_VIDEO,
	422	.of_match = tegra_lcd_ids,
	423	.ops = &tegra_lcd_ops,
	424	.bind = tegra_lcd_bind,
	425	.probe = tegra_lcd_probe,
f5acf91f	426	.ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
9e6866d3 SG	427	.priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
9e6866d3 SG	428	};