[J-u-boot.git] / arch / arm / mach-aspeed / ast2500 / sdram_ast2500.c

/*
 * Copyright (C) 2012-2020  ASPEED Technology Inc.
 *
 * Copyright 2016 Google, Inc
 *
 * SPDX-License-Identifier:		GPL-2.0
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <ram.h>
#include <regmap.h>
#include <asm/io.h>
#include <asm/arch/scu_ast2500.h>
#include <asm/arch/sdram_ast2500.h>
#include <asm/arch/wdt.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/ast2500-scu.h>

/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE		0x08000000
#define DDR4_MR5_MODE		0x400
#define DDR4_MR13_MODE		0x101
#define DDR4_MR02_MODE		0x410
#define DDR4_TRFC		0x45457188

#define PHY_CFG_SIZE		15

static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
static const struct {
	u32 index[PHY_CFG_SIZE];
	u32 value[PHY_CFG_SIZE];
} ddr4_phy_config = {
	.index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
	.value = {
		0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
		0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
		0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
	},
};

#define SDRAM_MAX_SIZE		(1024 * 1024 * 1024)
#define SDRAM_MIN_SIZE		(128 * 1024 * 1024)

DECLARE_GLOBAL_DATA_PTR;

/*
 * Bandwidth configuration parameters for different SDRAM requests.
 * These are hardcoded settings taken from Aspeed SDK.
 */
static const u32 ddr_max_grant_params[4] = {
	0x88448844, 0x24422288, 0x22222222, 0x22222222
};

/*
 * These registers are not documented by Aspeed at all.
 * All writes and reads are taken pretty much as is from SDK.
 */
struct ast2500_ddr_phy {
	u32 phy[117];
};

struct dram_info {
	struct ram_info info;
	struct clk ddr_clk;
	struct ast2500_sdrammc_regs *regs;
	struct ast2500_scu *scu;
	struct ast2500_ddr_phy *phy;
	ulong clock_rate;
};

static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
{
	writel(0, &phy->phy[2]);
	writel(0, &phy->phy[6]);
	writel(0, &phy->phy[8]);
	writel(0, &phy->phy[10]);
	writel(0, &phy->phy[12]);
	writel(0, &phy->phy[42]);
	writel(0, &phy->phy[44]);

	writel(0x86000000, &phy->phy[16]);
	writel(0x00008600, &phy->phy[17]);
	writel(0x80000000, &phy->phy[18]);
	writel(0x80808080, &phy->phy[19]);

	return 0;
}

static void ast2500_ddr_phy_init_process(struct dram_info *info)
{
	struct ast2500_sdrammc_regs *regs = info->regs;

	writel(0, &regs->phy_ctrl[0]);
	writel(0x4040, &info->phy->phy[51]);

	writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
	while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
		;
	writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
	       &regs->phy_ctrl[0]);
}

static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
{
	writel(0, &info->regs->phy_ctrl[0]);
	writel((vref << 8) | 0x6, &info->phy->phy[48]);
	ast2500_ddr_phy_init_process(info);
}

static int ast2500_ddr_cbr_test(struct dram_info *info)
{
	struct ast2500_sdrammc_regs *regs = info->regs;
	int i;
	const u32 test_params = SDRAM_TEST_EN
			| SDRAM_TEST_ERRSTOP
			| SDRAM_TEST_TWO_MODES;
	int ret = 0;

	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
	       (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), &regs->refresh_timing);
	writel((0xfff << SDRAM_TEST_LEN_SHIFT), &regs->test_addr);
	writel(0xff00ff00, &regs->test_init_val);
	writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
	       SDRAM_TEST_ERRSTOP, &regs->ecc_test_ctrl);

	while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
		;

	if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
		ret = -EIO;
	} else {
		for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
			writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
			       &regs->ecc_test_ctrl);
			while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
				;
			if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
				ret = -EIO;
				break;
			}
		}
	}

	writel(0, &regs->refresh_timing);
	writel(0, &regs->ecc_test_ctrl);

	return ret;
}

static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
{
	int i;
	int vref_min = 0xff;
	int vref_max = 0;
	int range_size = 0;

	for (i = 1; i < 0x40; ++i) {
		int res;

		ast2500_sdrammc_set_vref(info, i);
		res = ast2500_ddr_cbr_test(info);
		if (res < 0) {
			if (range_size > 0)
				break;
		} else {
			++range_size;
			vref_min = min(vref_min, i);
			vref_max = max(vref_max, i);
		}
	}

	/* Pick average setting */
	ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);

	return 0;
}

static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
	size_t vga_mem_size_base = 8 * 1024 * 1024;
	u32 vga_hwconf = (readl(&info->scu->hwstrap)
			  >> SCU_HWSTRAP_VGAMEM_SHIFT)
			& SCU_HWSTRAP_VGAMEM_MASK;

	return vga_mem_size_base << vga_hwconf;
}

/*
 * Find out RAM size and save it in dram_info
 *
 * The procedure is taken from Aspeed SDK
 */
static void ast2500_sdrammc_calc_size(struct dram_info *info)
{
	/* The controller supports 128/256/512/1024 MB ram */
	size_t ram_size = SDRAM_MIN_SIZE;
	const int write_test_offset = 0x100000;
	u32 test_pattern = 0xdeadbeef;
	u32 cap_param = SDRAM_CONF_CAP_1024M;
	u32 refresh_timing_param = DDR4_TRFC;
	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;

	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
	     ram_size >>= 1) {
		writel(test_pattern, write_addr_base + (ram_size >> 1));
		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
	}

	/* One last write to overwrite all wrapped values */
	writel(test_pattern, write_addr_base);

	/* Reset the pattern and see which value was really written */
	test_pattern = 0xdeadbeef;
	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
	     ram_size >>= 1) {
		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
			break;

		--cap_param;
		refresh_timing_param >>= 8;
		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
	}

	clrsetbits_le32(&info->regs->ac_timing[1],
			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
			 << SDRAM_AC_TRFC_SHIFT));

	info->info.base = CONFIG_SYS_SDRAM_BASE;
	info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
	clrsetbits_le32(&info->regs->config,
			(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
			((cap_param & SDRAM_CONF_CAP_MASK)
			 << SDRAM_CONF_CAP_SHIFT));
}

static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
{
	int i;
	const u32 power_control = SDRAM_PCR_CKE_EN
	    | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
	    | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
	    | SDRAM_PCR_RESETN_DIS
	    | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
	const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
#ifdef CONFIG_DUALX8_RAM
	    | SDRAM_CONF_DUALX8
#endif
	    | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
	int ret;

	writel(conf, &info->regs->config);
	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
		writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);

	writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
	writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
	writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
	writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);

	for (i = 0; i < PHY_CFG_SIZE; ++i) {
		writel(ddr4_phy_config.value[i],
		       &info->phy->phy[ddr4_phy_config.index[i]]);
	}

	writel(power_control, &info->regs->power_control);

	ast2500_ddr_phy_init_process(info);

	ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
	if (ret < 0) {
		debug("Vref calibration failed!\n");
		return ret;
	}

	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
	       | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
	       &info->regs->refresh_timing);

	setbits_le32(&info->regs->power_control,
		     SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);

	ast2500_sdrammc_calc_size(info);

	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
	while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
		;
	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);

	writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);

	/* Enable all requests except video & display */
	writel(SDRAM_REQ_USB20_EHCI1
	       | SDRAM_REQ_USB20_EHCI2
	       | SDRAM_REQ_CPU
	       | SDRAM_REQ_AHB2
	       | SDRAM_REQ_AHB
	       | SDRAM_REQ_MAC0
	       | SDRAM_REQ_MAC1
	       | SDRAM_REQ_PCIE
	       | SDRAM_REQ_XDMA
	       | SDRAM_REQ_ENCRYPTION
	       | SDRAM_REQ_VIDEO_FLAG
	       | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
	       | SDRAM_REQ_2D_RW
	       | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);

	return 0;
}

static void ast2500_sdrammc_unlock(struct dram_info *info)
{
	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
	while (!readl(&info->regs->protection_key))
		;
}

static void ast2500_sdrammc_lock(struct dram_info *info)
{
	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
	while (readl(&info->regs->protection_key))
		;
}

static int ast2500_sdrammc_probe(struct udevice *dev)
{
	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
	struct ast2500_sdrammc_regs *regs = priv->regs;
	int i;
	int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);

	if (ret) {
		debug("DDR:No CLK\n");
		return ret;
	}

	priv->scu = ast_get_scu();
	if (IS_ERR(priv->scu)) {
		debug("%s(): can't get SCU\n", __func__);
		return PTR_ERR(priv->scu);
	}

	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
	ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
	if (ret) {
		debug("%s(): SDRAM reset failed\n", __func__);
		return ret;
	}

	ast2500_sdrammc_unlock(priv);

	writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
	       &regs->power_control);
	writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);

	/* Mask all requests except CPU and AHB during PHY init */
	writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), &regs->req_limit_mask);

	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
		writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);

	setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);

	ast2500_sdrammc_init_phy(priv->phy);
	if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
		ast2500_sdrammc_init_ddr4(priv);
	} else {
		debug("Unsupported DRAM3\n");
		return -EINVAL;
	}

	clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
	ast2500_sdrammc_lock(priv);

	return 0;
}

static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
{
	struct dram_info *priv = dev_get_priv(dev);
	struct regmap *map;
	int ret;

	ret = regmap_init_mem(dev, &map);
	if (ret)
		return ret;

	priv->regs = regmap_get_range(map, 0);
	priv->phy = regmap_get_range(map, 1);

	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
					  "clock-frequency", 0);

	if (!priv->clock_rate) {
		debug("DDR Clock Rate not defined\n");
		return -EINVAL;
	}

	return 0;
}

static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
{
	struct dram_info *priv = dev_get_priv(dev);

	*info = priv->info;

	return 0;
}

static struct ram_ops ast2500_sdrammc_ops = {
	.get_info = ast2500_sdrammc_get_info,
};

static const struct udevice_id ast2500_sdrammc_ids[] = {
	{ .compatible = "aspeed,ast2500-sdrammc" },
	{ }
};

U_BOOT_DRIVER(sdrammc_ast2500) = {
	.name = "aspeed_ast2500_sdrammc",
	.id = UCLASS_RAM,
	.of_match = ast2500_sdrammc_ids,
	.ops = &ast2500_sdrammc_ops,
	.ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
	.probe = ast2500_sdrammc_probe,
	.priv_auto_alloc_size = sizeof(struct dram_info),
};
Commit	Line	Data
14e4b149	1	/*
	2	* Copyright (C) 2012-2020 ASPEED Technology Inc.
	3	*
	4	* Copyright 2016 Google, Inc
	5	*
	6	* SPDX-License-Identifier: GPL-2.0
	7	*/
	8
	9	#include <common.h>
	10	#include <clk.h>
	11	#include <dm.h>
	12	#include <errno.h>
	13	#include <ram.h>
	14	#include <regmap.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/scu_ast2500.h>
	17	#include <asm/arch/sdram_ast2500.h>
	18	#include <asm/arch/wdt.h>
	19	#include <linux/err.h>
	20	#include <linux/kernel.h>
	21	#include <dt-bindings/clock/ast2500-scu.h>
	22
	23	/* These configuration parameters are taken from Aspeed SDK */
	24	#define DDR4_MR46_MODE 0x08000000
	25	#define DDR4_MR5_MODE 0x400
	26	#define DDR4_MR13_MODE 0x101
	27	#define DDR4_MR02_MODE 0x410
	28	#define DDR4_TRFC 0x45457188
	29
	30	#define PHY_CFG_SIZE 15
	31
	32	static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
	33	static const struct {
	34	u32 index[PHY_CFG_SIZE];
	35	u32 value[PHY_CFG_SIZE];
	36	} ddr4_phy_config = {
	37	.index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
	38	.value = {
	39	0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
	40	0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
	41	0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
	42	},
	43	};
	44
	45	#define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
	46	#define SDRAM_MIN_SIZE (128 * 1024 * 1024)
	47
	48	DECLARE_GLOBAL_DATA_PTR;
	49
	50	/*
	51	* Bandwidth configuration parameters for different SDRAM requests.
	52	* These are hardcoded settings taken from Aspeed SDK.
	53	*/
	54	static const u32 ddr_max_grant_params[4] = {
	55	0x88448844, 0x24422288, 0x22222222, 0x22222222
	56	};
	57
	58	/*
	59	* These registers are not documented by Aspeed at all.
	60	* All writes and reads are taken pretty much as is from SDK.
	61	*/
	62	struct ast2500_ddr_phy {
	63	u32 phy[117];
	64	};
65
66	struct dram_info {
67	struct ram_info info;
68	struct clk ddr_clk;
69	struct ast2500_sdrammc_regs *regs;
70	struct ast2500_scu *scu;
71	struct ast2500_ddr_phy *phy;
72	ulong clock_rate;
73	};
74
75	static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
76	{
77	writel(0, &phy->phy[2]);
78	writel(0, &phy->phy[6]);
79	writel(0, &phy->phy[8]);
80	writel(0, &phy->phy[10]);
81	writel(0, &phy->phy[12]);
82	writel(0, &phy->phy[42]);
83	writel(0, &phy->phy[44]);
84
85	writel(0x86000000, &phy->phy[16]);
86	writel(0x00008600, &phy->phy[17]);
87	writel(0x80000000, &phy->phy[18]);
88	writel(0x80808080, &phy->phy[19]);
89
90	return 0;
91	}
92
93	static void ast2500_ddr_phy_init_process(struct dram_info *info)
94	{
95	struct ast2500_sdrammc_regs *regs = info->regs;
96
97	writel(0, &regs->phy_ctrl[0]);
98	writel(0x4040, &info->phy->phy[51]);
99
100	writel(SDRAM_PHYCTRL0_NRST \| SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
101	while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
102	;
103	writel(SDRAM_PHYCTRL0_NRST \| SDRAM_PHYCTRL0_AUTO_UPDATE,
104	&regs->phy_ctrl[0]);
105	}
106
107	static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
108	{
109	writel(0, &info->regs->phy_ctrl[0]);
110	writel((vref << 8) \| 0x6, &info->phy->phy[48]);
111	ast2500_ddr_phy_init_process(info);
112	}
113
114	static int ast2500_ddr_cbr_test(struct dram_info *info)
115	{
116	struct ast2500_sdrammc_regs *regs = info->regs;
117	int i;
118	const u32 test_params = SDRAM_TEST_EN
119	\| SDRAM_TEST_ERRSTOP
120	\| SDRAM_TEST_TWO_MODES;
121	int ret = 0;
122
123	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) \|
124	(0x5c << SDRAM_REFRESH_PERIOD_SHIFT), &regs->refresh_timing);
125	writel((0xfff << SDRAM_TEST_LEN_SHIFT), &regs->test_addr);
126	writel(0xff00ff00, &regs->test_init_val);
127	writel(SDRAM_TEST_EN \| (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) \|
128	SDRAM_TEST_ERRSTOP, &regs->ecc_test_ctrl);
129
130	while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
131	;
132
133	if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
134	ret = -EIO;
135	} else {
136	for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
137	writel((i << SDRAM_TEST_GEN_MODE_SHIFT) \| test_params,
138	&regs->ecc_test_ctrl);
139	while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
140	;
141	if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
142	ret = -EIO;
143	break;
144	}
145	}
146	}
147
148	writel(0, &regs->refresh_timing);
149	writel(0, &regs->ecc_test_ctrl);
150
151	return ret;
152	}
153
154	static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
155	{
156	int i;
157	int vref_min = 0xff;
158	int vref_max = 0;
159	int range_size = 0;
160
161	for (i = 1; i < 0x40; ++i) {
162	int res;
163
164	ast2500_sdrammc_set_vref(info, i);
165	res = ast2500_ddr_cbr_test(info);
166	if (res < 0) {
167	if (range_size > 0)
168	break;
169	} else {
170	++range_size;
171	vref_min = min(vref_min, i);
172	vref_max = max(vref_max, i);
173	}
174	}
175
176	/* Pick average setting */
177	ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
178
179	return 0;
180	}
181
182	static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
183	{
184	size_t vga_mem_size_base = 8 * 1024 * 1024;
185	u32 vga_hwconf = (readl(&info->scu->hwstrap)
186	>> SCU_HWSTRAP_VGAMEM_SHIFT)
187	& SCU_HWSTRAP_VGAMEM_MASK;
188
189	return vga_mem_size_base << vga_hwconf;
190	}
191
192	/*
193	* Find out RAM size and save it in dram_info
194	*
195	* The procedure is taken from Aspeed SDK
196	*/
197	static void ast2500_sdrammc_calc_size(struct dram_info *info)
198	{
199	/* The controller supports 128/256/512/1024 MB ram */
200	size_t ram_size = SDRAM_MIN_SIZE;
201	const int write_test_offset = 0x100000;
202	u32 test_pattern = 0xdeadbeef;
203	u32 cap_param = SDRAM_CONF_CAP_1024M;
204	u32 refresh_timing_param = DDR4_TRFC;
205	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
206
207	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
208	ram_size >>= 1) {
209	writel(test_pattern, write_addr_base + (ram_size >> 1));
210	test_pattern = (test_pattern >> 4) \| (test_pattern << 28);
211	}
212
213	/* One last write to overwrite all wrapped values */
214	writel(test_pattern, write_addr_base);
215
216	/* Reset the pattern and see which value was really written */
217	test_pattern = 0xdeadbeef;
218	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
219	ram_size >>= 1) {
220	if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
221	break;
222
223	--cap_param;
224	refresh_timing_param >>= 8;
225	test_pattern = (test_pattern >> 4) \| (test_pattern << 28);
226	}
227
228	clrsetbits_le32(&info->regs->ac_timing[1],
229	(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
230	((refresh_timing_param & SDRAM_AC_TRFC_MASK)
231	<< SDRAM_AC_TRFC_SHIFT));
232
233	info->info.base = CONFIG_SYS_SDRAM_BASE;
234	info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
235	clrsetbits_le32(&info->regs->config,
236	(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
237	((cap_param & SDRAM_CONF_CAP_MASK)
238	<< SDRAM_CONF_CAP_SHIFT));
239	}
240
241	static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
242	{
243	int i;
244	const u32 power_control = SDRAM_PCR_CKE_EN
245	\| (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
246	\| (2 << SDRAM_PCR_TCKE_PW_SHIFT)
247	\| SDRAM_PCR_RESETN_DIS
248	\| SDRAM_PCR_RGAP_CTRL_EN \| SDRAM_PCR_ODT_EN \| SDRAM_PCR_ODT_EXT_EN;
249	const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
250	#ifdef CONFIG_DUALX8_RAM
251	\| SDRAM_CONF_DUALX8
252	#endif
253	\| SDRAM_CONF_SCRAMBLE \| SDRAM_CONF_SCRAMBLE_PAT2 \| SDRAM_CONF_DDR4;
254	int ret;
255
256	writel(conf, &info->regs->config);
257	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
258	writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
259
260	writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
261	writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
262	writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
263	writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
264
265	for (i = 0; i < PHY_CFG_SIZE; ++i) {
266	writel(ddr4_phy_config.value[i],
267	&info->phy->phy[ddr4_phy_config.index[i]]);
268	}
269
270	writel(power_control, &info->regs->power_control);
271
272	ast2500_ddr_phy_init_process(info);
273
274	ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
275	if (ret < 0) {
276	debug("Vref calibration failed!\n");
277	return ret;
278	}
279
280	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
281	\| SDRAM_REFRESH_ZQCS_EN \| (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
282	&info->regs->refresh_timing);
283
284	setbits_le32(&info->regs->power_control,
285	SDRAM_PCR_AUTOPWRDN_EN \| SDRAM_PCR_ODT_AUTO_ON);
286
287	ast2500_sdrammc_calc_size(info);
288
289	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
290	while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
291	;
292	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
293
294	writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
295
296	/* Enable all requests except video & display */
297	writel(SDRAM_REQ_USB20_EHCI1
298	\| SDRAM_REQ_USB20_EHCI2
299	\| SDRAM_REQ_CPU
300	\| SDRAM_REQ_AHB2
301	\| SDRAM_REQ_AHB
302	\| SDRAM_REQ_MAC0
303	\| SDRAM_REQ_MAC1
304	\| SDRAM_REQ_PCIE
305	\| SDRAM_REQ_XDMA
306	\| SDRAM_REQ_ENCRYPTION
307	\| SDRAM_REQ_VIDEO_FLAG
308	\| SDRAM_REQ_VIDEO_LOW_PRI_WRITE
309	\| SDRAM_REQ_2D_RW
310	\| SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
311
312	return 0;
313	}
314
315	static void ast2500_sdrammc_unlock(struct dram_info *info)
316	{
317	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
318	while (!readl(&info->regs->protection_key))
319	;
320	}
321
322	static void ast2500_sdrammc_lock(struct dram_info *info)
323	{
324	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
325	while (readl(&info->regs->protection_key))
326	;
327	}
328
329	static int ast2500_sdrammc_probe(struct udevice *dev)
330	{
331	struct dram_info priv = (struct dram_info )dev_get_priv(dev);
332	struct ast2500_sdrammc_regs *regs = priv->regs;
333	int i;
334	int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
335
336	if (ret) {
337	debug("DDR:No CLK\n");
338	return ret;
339	}
340
341	priv->scu = ast_get_scu();
342	if (IS_ERR(priv->scu)) {
343	debug("%s(): can't get SCU\n", __func__);
344	return PTR_ERR(priv->scu);
345	}
346
347	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
348	ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
349	if (ret) {
350	debug("%s(): SDRAM reset failed\n", __func__);
351	return ret;
352	}
353
354	ast2500_sdrammc_unlock(priv);
355
356	writel(SDRAM_PCR_MREQI_DIS \| SDRAM_PCR_RESETN_DIS,
357	&regs->power_control);
358	writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
359
360	/* Mask all requests except CPU and AHB during PHY init */
361	writel(~(SDRAM_REQ_CPU \| SDRAM_REQ_AHB), &regs->req_limit_mask);
362
363	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
364	writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
365
366	setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
367
368	ast2500_sdrammc_init_phy(priv->phy);
369	if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
370	ast2500_sdrammc_init_ddr4(priv);
371	} else {
372	debug("Unsupported DRAM3\n");
373	return -EINVAL;
374	}
375
376	clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
377	ast2500_sdrammc_lock(priv);
378
379	return 0;
380	}
381
382	static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
383	{
384	struct dram_info *priv = dev_get_priv(dev);
385	struct regmap *map;
386	int ret;
387
388	ret = regmap_init_mem(dev, &map);
389	if (ret)
390	return ret;
391
392	priv->regs = regmap_get_range(map, 0);
393	priv->phy = regmap_get_range(map, 1);
394
395	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
396	"clock-frequency", 0);
397
398	if (!priv->clock_rate) {
399	debug("DDR Clock Rate not defined\n");
400	return -EINVAL;
401	}
402
403	return 0;
404	}
405
406	static int ast2500_sdrammc_get_info(struct udevice dev, struct ram_info info)
407	{
408	struct dram_info *priv = dev_get_priv(dev);
409
410	*info = priv->info;
411
412	return 0;
413	}
414
415	static struct ram_ops ast2500_sdrammc_ops = {
416	.get_info = ast2500_sdrammc_get_info,
417	};
418
419	static const struct udevice_id ast2500_sdrammc_ids[] = {
420	{ .compatible = "aspeed,ast2500-sdrammc" },
421	{ }
422	};
423
424	U_BOOT_DRIVER(sdrammc_ast2500) = {
425	.name = "aspeed_ast2500_sdrammc",
426	.id = UCLASS_RAM,
427	.of_match = ast2500_sdrammc_ids,
428	.ops = &ast2500_sdrammc_ops,
429	.ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
430	.probe = ast2500_sdrammc_probe,
431	.priv_auto_alloc_size = sizeof(struct dram_info),
432	};