[J-u-boot.git] / drivers / spi / mxc_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return -1;
}

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
#endif

#define MAX_CS_COUNT	4

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
	unsigned int	max_hz;
	unsigned int	mode;
	struct gpio_desc ss;
	struct gpio_desc cs_gpios[MAX_CS_COUNT];
	struct udevice *dev;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
#if CONFIG_IS_ENABLED(DM_SPI)
	struct udevice *dev = mxcs->dev;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	u32 cs = slave_plat->cs;

	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
		return;

	dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
#else
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, mxcs->ss_pol);
#endif
}

static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
#if CONFIG_IS_ENABLED(DM_SPI)
	struct udevice *dev = mxcs->dev;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	u32 cs = slave_plat->cs;

	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
		return;

	dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
#else
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
#endif
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	u32 pre_div = 0, post_div = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	if (clk_src > max_hz) {
		pre_div = (clk_src - 1) / max_hz;
		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
		post_div = fls(pre_div);
		if (post_div > 4) {
			post_div -= 4;
			if (post_div >= 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			pre_div >>= post_div;
		} else {
			post_div = 0;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL) {
		sclkpol = 1;
		sclkctl = 1;
	}

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
		(sclkctl << (cs + MXC_CSPICON_CTL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	int nbytes = DIV_ROUND_UP(bitlen, 8);
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	u32 ts;
	int status;

	debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
		__func__, bitlen, (ulong)dout, (ulong)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
				dout += 4;
			}
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	ts = get_timer(0);
	status = reg_read(&regs->stat);
	/* Wait until the TC (Transfer completed) bit is set */
	while ((status & MXC_CSPICTRL_TC) == 0) {
		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
			printf("spi_xchg_single: Timeout!\n");
			return -1;
		}
		status = reg_read(&regs->stat);
	}

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = DIV_ROUND_UP(bitlen, 8);

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min_t(u32, nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
				 unsigned int bitlen, const void *dout,
				 void *din, unsigned long flags)
{
	int n_bytes = DIV_ROUND_UP(bitlen, 8);
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!mxcs)
		return -EINVAL;

	if (flags & SPI_XFER_BEGIN)
		mxc_spi_cs_activate(mxcs);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		mxc_spi_cs_deactivate(mxcs);
	}

	return 0;
}

static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
{
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	int ret;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	ret = spi_cfg_mxc(mxcs, cs);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		return ret;
	}
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

/*
 * Some SPI devices require active chip-select over multiple
 * transactions, we achieve this using a GPIO. Still, the SPI
 * controller has to be configured to use one of its own chipselects.
 * To use this feature you have to implement board_spi_cs_gpio() to assign
 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
 * You must use some unused on this SPI controller cs between 0 and 3.
 */
static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
			 unsigned int bus, unsigned int cs)
{
	int ret;

	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	if (mxcs->gpio == -1)
		return 0;

	gpio_request(mxcs->gpio, "spi-cs");
	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	if (ret) {
		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
		return -EINVAL;
	}

	return 0;
}

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return NULL;
	}

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = setup_cs_gpio(mxcs, bus, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	mxcs->base = spi_bases[bus];
	mxcs->max_hz = max_hz;
	mxcs->mode = mode;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
#else

static int mxc_spi_probe(struct udevice *bus)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
	int node = dev_of_offset(bus);
	const void *blob = gd->fdt_blob;
	int ret;
	int i;

	ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
					ARRAY_SIZE(mxcs->cs_gpios), 0);
	if (ret < 0) {
		pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
		return ret;
	}

	for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
		if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
			continue;

		ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
					    GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
		if (ret) {
			dev_err(bus, "Setting cs %d error\n", i);
			return ret;
		}
	}

	mxcs->base = dev_read_addr(bus);
	if (mxcs->base == FDT_ADDR_T_NONE)
		return -ENODEV;

	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
				      20000000);

	return 0;
}

static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);


	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

static int mxc_spi_claim_bus(struct udevice *dev)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	mxcs->dev = dev;

	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}

static int mxc_spi_release_bus(struct udevice *dev)
{
	return 0;
}

static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
	/* Nothing to do */
	return 0;
}

static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(bus);

	mxcs->mode = mode;
	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	return 0;
}

static const struct dm_spi_ops mxc_spi_ops = {
	.claim_bus	= mxc_spi_claim_bus,
	.release_bus	= mxc_spi_release_bus,
	.xfer		= mxc_spi_xfer,
	.set_speed	= mxc_spi_set_speed,
	.set_mode	= mxc_spi_set_mode,
};

static const struct udevice_id mxc_spi_ids[] = {
	{ .compatible = "fsl,imx51-ecspi" },
	{ }
};

U_BOOT_DRIVER(mxc_spi) = {
	.name	= "mxc_spi",
	.id	= UCLASS_SPI,
	.of_match = mxc_spi_ids,
	.ops	= &mxc_spi_ops,
	.plat_auto	= sizeof(struct mxc_spi_slave),
	.probe	= mxc_spi_probe,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
38254f45 GL	2	/*
38254f45 GL	3	* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
38254f45 GL	4	*/
	5
	6	#include <common.h>
994266bd	7	#include <dm.h>
f7ae49fc	8	#include <log.h>
d255bb0e	9	#include <malloc.h>
38254f45	10	#include <spi.h>
336d4615	11	#include <dm/device_compat.h>
cd93d625	12	#include <linux/bitops.h>
c05ed00a	13	#include <linux/delay.h>
1221ce45	14	#include <linux/errno.h>
38254f45	15	#include <asm/io.h>
d8e0ca85	16	#include <asm/gpio.h>
86271115 SB	17	#include <asm/arch/imx-regs.h>
86271115 SB	18	#include <asm/arch/clock.h>
552a848e	19	#include <asm/mach-imx/spi.h>
38254f45	20
994266bd PF	21	DECLARE_GLOBAL_DATA_PTR;
994266bd PF	22
38254f45 GL	23	#ifdef CONFIG_MX27
	24	/* i.MX27 has a completely wrong register layout and register definitions in the
	25	* datasheet, the correct one is in the Freescale's Linux driver */
	26
61a58a16	27	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	28	"See linux mxc_spi driver from Freescale for details."
08c61a58	29	#endif
c9d59c7f	30
155fa9af NK	31	__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
	32	{
	33	return -1;
	34	}
	35
c4ea1424 SB	36	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	37
ac87c17d SB	38	#define reg_read readl
	39	#define reg_write(a, v) writel(v, a)
	40
f659b573 HS	41	#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
	42	#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
	43	#endif
	44
7a3faf31 HS	45	#define MAX_CS_COUNT 4
7a3faf31 HS	46
d255bb0e HS	47	struct mxc_spi_slave {
	48	struct spi_slave slave;
	49	unsigned long base;
	50	u32 ctrl_reg;
08c61a58	51	#if defined(MXC_ECSPI)
d205ddcf SB	52	u32 cfg_reg;
d205ddcf SB	53	#endif
fc7a93c8	54	int gpio;
c4ea1424	55	int ss_pol;
027a9a00 MN	56	unsigned int max_hz;
027a9a00 MN	57	unsigned int mode;
994266bd	58	struct gpio_desc ss;
7a3faf31 HS	59	struct gpio_desc cs_gpios[MAX_CS_COUNT];
7a3faf31 HS	60	struct udevice *dev;
38254f45	61	};
d255bb0e HS	62
	63	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	64	{
	65	return container_of(slave, struct mxc_spi_slave, slave);
	66	}
38254f45	67
994266bd	68	static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
d205ddcf	69	{
56c40460	70	#if CONFIG_IS_ENABLED(DM_SPI)
7a3faf31	71	struct udevice *dev = mxcs->dev;
8a8d24bd	72	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
7a3faf31 HS	73
	74	u32 cs = slave_plat->cs;
	75
	76	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
	77	return;
	78
	79	dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
	80	#else
	81	if (mxcs->gpio > 0)
	82	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	83	#endif
d205ddcf SB	84	}
d205ddcf SB	85
994266bd	86	static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
d205ddcf	87	{
56c40460	88	#if CONFIG_IS_ENABLED(DM_SPI)
7a3faf31	89	struct udevice *dev = mxcs->dev;
8a8d24bd	90	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
7a3faf31 HS	91
	92	u32 cs = slave_plat->cs;
	93
	94	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
	95	return;
	96
	97	dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
	98	#else
	99	if (mxcs->gpio > 0)
	100	gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	101	#endif
d205ddcf SB	102	}
d205ddcf SB	103
afaa9f65 AG	104	u32 get_cspi_div(u32 div)
	105	{
	106	int i;
	107
	108	for (i = 0; i < 8; i++) {
	109	if (div <= (4 << i))
	110	return i;
	111	}
	112	return i;
	113	}
	114
08c61a58	115	#ifdef MXC_CSPI
027a9a00	116	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
c9d59c7f SB	117	{
c9d59c7f SB	118	unsigned int ctrl_reg;
afaa9f65 AG	119	u32 clk_src;
afaa9f65 AG	120	u32 div;
027a9a00 MN	121	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	122	unsigned int mode = mxcs->mode;
afaa9f65 AG	123
	124	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	125
cd200403	126	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	127	div = get_cspi_div(div);
	128
	129	debug("clk %d Hz, div %d, real clk %d Hz\n",
	130	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	131
	132	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	133	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	134	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	135	MXC_CSPICTRL_EN \|
	136	#ifdef CONFIG_MX35
	137	MXC_CSPICTRL_SSCTL \|
	138	#endif
	139	MXC_CSPICTRL_MODE;
	140
	141	if (mode & SPI_CPHA)
	142	ctrl_reg \|= MXC_CSPICTRL_PHA;
	143	if (mode & SPI_CPOL)
	144	ctrl_reg \|= MXC_CSPICTRL_POL;
	145	if (mode & SPI_CS_HIGH)
	146	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	147	mxcs->ctrl_reg = ctrl_reg;
	148
	149	return 0;
	150	}
	151	#endif
	152
08c61a58	153	#ifdef MXC_ECSPI
027a9a00	154	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
d205ddcf SB	155	{
d205ddcf SB	156	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
9a30903b	157	s32 reg_ctrl, reg_config;
5d584cce MN	158	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
5d584cce MN	159	u32 pre_div = 0, post_div = 0;
ac87c17d	160	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
027a9a00 MN	161	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	162	unsigned int mode = mxcs->mode;
d205ddcf	163
0f1411bc FE	164	/*
	165	* Reset SPI and set all CSs to master mode, if toggling
	166	* between slave and master mode we might see a glitch
	167	* on the clock line
	168	*/
	169	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	170	reg_write(&regs->ctrl, reg_ctrl);
	171	reg_ctrl \|= MXC_CSPICTRL_EN;
	172	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	173
d205ddcf	174	if (clk_src > max_hz) {
9a30903b DB	175	pre_div = (clk_src - 1) / max_hz;
	176	/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
	177	post_div = fls(pre_div);
	178	if (post_div > 4) {
	179	post_div -= 4;
	180	if (post_div >= 16) {
d205ddcf SB	181	printf("Error: no divider for the freq: %d\n",
	182	max_hz);
	183	return -1;
	184	}
9a30903b DB	185	pre_div >>= post_div;
	186	} else {
	187	post_div = 0;
d205ddcf SB	188	}
	189	}
	190
	191	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	192	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	193	MXC_CSPICTRL_SELCHAN(cs);
	194	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	195	MXC_CSPICTRL_PREDIV(pre_div);
	196	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	197	MXC_CSPICTRL_POSTDIV(post_div);
	198
d205ddcf SB	199	if (mode & SPI_CS_HIGH)
	200	ss_pol = 1;
	201
5d584cce	202	if (mode & SPI_CPOL) {
d205ddcf	203	sclkpol = 1;
5d584cce MN	204	sclkctl = 1;
5d584cce MN	205	}
d205ddcf SB	206
	207	if (mode & SPI_CPHA)
	208	sclkpha = 1;
	209
ac87c17d	210	reg_config = reg_read(&regs->cfg);
d205ddcf SB	211
	212	/*
	213	* Configuration register setup
c9d59c7f	214	* The MX51 supports different setup for each SS
d205ddcf SB	215	*/
	216	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	217	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	218	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	219	(sclkpol << (cs + MXC_CSPICON_POL));
5d584cce MN	220	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
5d584cce MN	221	(sclkctl << (cs + MXC_CSPICON_CTL));
d205ddcf SB	222	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	223	(sclkpha << (cs + MXC_CSPICON_PHA));
	224
	225	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	226	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	227	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	228	reg_write(&regs->cfg, reg_config);
d205ddcf SB	229
	230	/* save config register and control register */
	231	mxcs->ctrl_reg = reg_ctrl;
	232	mxcs->cfg_reg = reg_config;
	233
	234	/* clear interrupt reg */
ac87c17d SB	235	reg_write(&regs->intr, 0);
ac87c17d SB	236	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	237
	238	return 0;
	239	}
	240	#endif
	241
994266bd	242	int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
2f721d17	243	const u8 dout, u8 din, unsigned long flags)
38254f45	244	{
9675fed4	245	int nbytes = DIV_ROUND_UP(bitlen, 8);
2f721d17	246	u32 data, cnt, i;
ac87c17d	247	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
f659b573 HS	248	u32 ts;
f659b573 HS	249	int status;
38254f45	250
65a106e3 YL	251	debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
65a106e3 YL	252	__func__, bitlen, (ulong)dout, (ulong)din);
d205ddcf SB	253
	254	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	255	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	256	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	257
ac87c17d	258	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	259	#ifdef MXC_ECSPI
ac87c17d	260	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	261	#endif
38254f45	262
d205ddcf	263	/* Clear interrupt register */
ac87c17d	264	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	265
2f721d17 SB	266	/*
	267	* The SPI controller works only with words,
	268	* check if less than a word is sent.
	269	* Access to the FIFO is only 32 bit
	270	*/
	271	if (bitlen % 32) {
	272	data = 0;
	273	cnt = (bitlen % 32) / 8;
	274	if (dout) {
	275	for (i = 0; i < cnt; i++) {
	276	data = (data << 8) \| (*dout++ & 0xFF);
	277	}
	278	}
	279	debug("Sending SPI 0x%x\n", data);
	280
ac87c17d	281	reg_write(&regs->txdata, data);
2f721d17 SB	282	nbytes -= cnt;
	283	}
	284
	285	data = 0;
	286
	287	while (nbytes > 0) {
	288	data = 0;
	289	if (dout) {
	290	/* Buffer is not 32-bit aligned */
	291	if ((unsigned long)dout & 0x03) {
	292	data = 0;
dff01094	293	for (i = 0; i < 4; i++)
2f721d17	294	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	295	} else {
	296	data = (u32 )dout;
	297	data = cpu_to_be32(data);
6d5ce1bd	298	dout += 4;
2f721d17	299	}
2f721d17 SB	300	}
2f721d17 SB	301	debug("Sending SPI 0x%x\n", data);
ac87c17d	302	reg_write(&regs->txdata, data);
2f721d17 SB	303	nbytes -= 4;
2f721d17 SB	304	}
38254f45	305
d205ddcf	306	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	307	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	308	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	309
f659b573 HS	310	ts = get_timer(0);
f659b573 HS	311	status = reg_read(&regs->stat);
d205ddcf	312	/* Wait until the TC (Transfer completed) bit is set */
f659b573 HS	313	while ((status & MXC_CSPICTRL_TC) == 0) {
	314	if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
	315	printf("spi_xchg_single: Timeout!\n");
	316	return -1;
	317	}
	318	status = reg_read(&regs->stat);
	319	}
38254f45	320
d205ddcf	321	/* Transfer completed, clear any pending request */
ac87c17d	322	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	323
9675fed4	324	nbytes = DIV_ROUND_UP(bitlen, 8);
d205ddcf	325
2f721d17	326	cnt = nbytes % 32;
d205ddcf	327
2f721d17	328	if (bitlen % 32) {
ac87c17d	329	data = reg_read(&regs->rxdata);
2f721d17	330	cnt = (bitlen % 32) / 8;
dff01094	331	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	332	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	333	if (din) {
dff01094 AG	334	memcpy(din, &data, cnt);
dff01094 AG	335	din += cnt;
2f721d17 SB	336	}
	337	nbytes -= cnt;
	338	}
	339
	340	while (nbytes > 0) {
	341	u32 tmp;
ac87c17d	342	tmp = reg_read(&regs->rxdata);
2f721d17 SB	343	data = cpu_to_be32(tmp);
2f721d17 SB	344	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
b4141195	345	cnt = min_t(u32, nbytes, sizeof(data));
2f721d17 SB	346	if (din) {
	347	memcpy(din, &data, cnt);
	348	din += cnt;
	349	}
	350	nbytes -= cnt;
	351	}
	352
	353	return 0;
fc7a93c8	354
38254f45 GL	355	}
38254f45 GL	356
994266bd PF	357	static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
	358	unsigned int bitlen, const void *dout,
	359	void *din, unsigned long flags)
38254f45	360	{
9675fed4	361	int n_bytes = DIV_ROUND_UP(bitlen, 8);
2f721d17 SB	362	int n_bits;
	363	int ret;
	364	u32 blk_size;
	365	u8 p_outbuf = (u8 )dout;
	366	u8 p_inbuf = (u8 )din;
38254f45	367
994266bd PF	368	if (!mxcs)
994266bd PF	369	return -EINVAL;
38254f45	370
2f721d17	371	if (flags & SPI_XFER_BEGIN)
994266bd	372	mxc_spi_cs_activate(mxcs);
2f721d17 SB	373
2f721d17 SB	374	while (n_bytes > 0) {
2f721d17 SB	375	if (n_bytes < MAX_SPI_BYTES)
	376	blk_size = n_bytes;
	377	else
	378	blk_size = MAX_SPI_BYTES;
	379
	380	n_bits = blk_size * 8;
	381
994266bd	382	ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
2f721d17 SB	383
	384	if (ret)
	385	return ret;
	386	if (dout)
	387	p_outbuf += blk_size;
	388	if (din)
	389	p_inbuf += blk_size;
	390	n_bytes -= blk_size;
eff536be ML	391	}
eff536be ML	392
2f721d17	393	if (flags & SPI_XFER_END) {
994266bd	394	mxc_spi_cs_deactivate(mxcs);
f9b6a157	395	}
38254f45 GL	396
	397	return 0;
	398	}
	399
994266bd PF	400	static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
	401	{
	402	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
	403	int ret;
	404
	405	reg_write(&regs->rxdata, 1);
	406	udelay(1);
	407	ret = spi_cfg_mxc(mxcs, cs);
	408	if (ret) {
	409	printf("mxc_spi: cannot setup SPI controller\n");
	410	return ret;
	411	}
	412	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	413	reg_write(&regs->intr, 0);
	414
	415	return 0;
	416	}
	417
56c40460	418	#if !CONFIG_IS_ENABLED(DM_SPI)
994266bd PF	419	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	420	void *din, unsigned long flags)
	421	{
	422	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	423
	424	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	425	}
	426
155fa9af NK	427	/*
	428	* Some SPI devices require active chip-select over multiple
	429	* transactions, we achieve this using a GPIO. Still, the SPI
	430	* controller has to be configured to use one of its own chipselects.
	431	* To use this feature you have to implement board_spi_cs_gpio() to assign
	432	* a gpio value for each cs (-1 if cs doesn't need to use gpio).
	433	* You must use some unused on this SPI controller cs between 0 and 3.
	434	*/
	435	static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
	436	unsigned int bus, unsigned int cs)
fc7a93c8 GL	437	{
	438	int ret;
	439
155fa9af NK	440	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	441	if (mxcs->gpio == -1)
	442	return 0;
	443
994266bd	444	gpio_request(mxcs->gpio, "spi-cs");
155fa9af NK	445	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	446	if (ret) {
	447	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	448	return -EINVAL;
fc7a93c8 GL	449	}
fc7a93c8 GL	450
155fa9af	451	return 0;
fc7a93c8 GL	452	}
fc7a93c8 GL	453
994266bd PF	454	static unsigned long spi_bases[] = {
	455	MXC_SPI_BASE_ADDRESSES
	456	};
	457
d255bb0e HS	458	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	459	unsigned int max_hz, unsigned int mode)
38254f45	460	{
d255bb0e	461	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	462	int ret;
	463
	464	if (bus >= ARRAY_SIZE(spi_bases))
	465	return NULL;
	466
027a9a00 MN	467	if (max_hz == 0) {
	468	printf("Error: desired clock is 0\n");
	469	return NULL;
	470	}
	471
d3504fee	472	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	473	if (!mxcs) {
2f721d17 SB	474	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	475	return NULL;
2f721d17	476	}
38254f45	477
de5bf02c FE	478	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	479
155fa9af	480	ret = setup_cs_gpio(mxcs, bus, cs);
fc7a93c8 GL	481	if (ret < 0) {
fc7a93c8 GL	482	free(mxcs);
d255bb0e	483	return NULL;
fc7a93c8 GL	484	}
fc7a93c8 GL	485
d205ddcf	486	mxcs->base = spi_bases[bus];
027a9a00 MN	487	mxcs->max_hz = max_hz;
027a9a00 MN	488	mxcs->mode = mode;
d205ddcf	489
d255bb0e HS	490	return &mxcs->slave;
	491	}
	492
	493	void spi_free_slave(struct spi_slave *slave)
	494	{
f9b6a157 GL	495	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	496
	497	free(mxcs);
d255bb0e HS	498	}
	499
	500	int spi_claim_bus(struct spi_slave *slave)
	501	{
	502	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	503
994266bd PF	504	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
	505	}
	506
	507	void spi_release_bus(struct spi_slave *slave)
	508	{
	509	/* TODO: Shut the controller down */
	510	}
	511	#else
	512
	513	static int mxc_spi_probe(struct udevice *bus)
	514	{
c69cda25	515	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
994266bd PF	516	int node = dev_of_offset(bus);
	517	const void *blob = gd->fdt_blob;
	518	int ret;
7a3faf31	519	int i;
994266bd	520
7a3faf31 HS	521	ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
	522	ARRAY_SIZE(mxcs->cs_gpios), 0);
	523	if (ret < 0) {
	524	pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
	525	return ret;
	526	}
	527
	528	for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
	529	if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
	530	continue;
	531
	532	ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
	533	GPIOD_IS_OUT \| GPIOD_ACTIVE_LOW);
	534	if (ret) {
	535	dev_err(bus, "Setting cs %d error\n", i);
	536	return ret;
	537	}
994266bd PF	538	}
994266bd PF	539
2548493a	540	mxcs->base = dev_read_addr(bus);
2b849e1f	541	if (mxcs->base == FDT_ADDR_T_NONE)
994266bd PF	542	return -ENODEV;
994266bd PF	543
994266bd PF	544	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
994266bd PF	545	20000000);
38254f45 GL	546
	547	return 0;
	548	}
d255bb0e	549
994266bd PF	550	static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
994266bd PF	551	const void dout, void din, unsigned long flags)
d255bb0e	552	{
c69cda25	553	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
994266bd PF	554
	555
	556	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	557	}
	558
	559	static int mxc_spi_claim_bus(struct udevice *dev)
	560	{
c69cda25	561	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
8a8d24bd	562	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
994266bd	563
7a3faf31 HS	564	mxcs->dev = dev;
7a3faf31 HS	565
994266bd	566	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
d255bb0e	567	}
994266bd PF	568
	569	static int mxc_spi_release_bus(struct udevice *dev)
	570	{
	571	return 0;
	572	}
	573
	574	static int mxc_spi_set_speed(struct udevice *bus, uint speed)
	575	{
	576	/* Nothing to do */
	577	return 0;
	578	}
	579
	580	static int mxc_spi_set_mode(struct udevice *bus, uint mode)
	581	{
c69cda25	582	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
994266bd PF	583
	584	mxcs->mode = mode;
	585	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
	586
	587	return 0;
	588	}
	589
	590	static const struct dm_spi_ops mxc_spi_ops = {
	591	.claim_bus = mxc_spi_claim_bus,
	592	.release_bus = mxc_spi_release_bus,
	593	.xfer = mxc_spi_xfer,
	594	.set_speed = mxc_spi_set_speed,
	595	.set_mode = mxc_spi_set_mode,
	596	};
	597
	598	static const struct udevice_id mxc_spi_ids[] = {
	599	{ .compatible = "fsl,imx51-ecspi" },
	600	{ }
	601	};
	602
	603	U_BOOT_DRIVER(mxc_spi) = {
	604	.name = "mxc_spi",
	605	.id = UCLASS_SPI,
	606	.of_match = mxc_spi_ids,
	607	.ops = &mxc_spi_ops,
caa4daa2	608	.plat_auto = sizeof(struct mxc_spi_slave),
994266bd PF	609	.probe = mxc_spi_probe,
	610	};
	611	#endif