[J-u-boot.git] / drivers / spi / cadence_qspi.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2012
 * Altera Corporation <www.altera.com>
 */

#ifndef __CADENCE_QSPI_H__
#define __CADENCE_QSPI_H__

#include <reset.h>

#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)

#define CQSPI_NO_DECODER_MAX_CS		4
#define CQSPI_DECODER_MAX_CS		16
#define CQSPI_READ_CAPTURE_MAX_DELAY	16

struct cadence_spi_plat {
	unsigned int	ref_clk_hz;
	unsigned int	max_hz;
	void		*regbase;
	void		*ahbbase;
	bool		is_decoded_cs;
	u32		fifo_depth;
	u32		fifo_width;
	u32		trigger_address;
	fdt_addr_t	ahbsize;
	bool		use_dac_mode;

	/* Flash parameters */
	u32		page_size;
	u32		block_size;
	u32		tshsl_ns;
	u32		tsd2d_ns;
	u32		tchsh_ns;
	u32		tslch_ns;
};

struct cadence_spi_priv {
	void		*regbase;
	void		*ahbbase;
	size_t		cmd_len;
	u8		cmd_buf[32];
	size_t		data_len;

	int		qspi_is_init;
	unsigned int	qspi_calibrated_hz;
	unsigned int	qspi_calibrated_cs;
	unsigned int	previous_hz;

	struct reset_ctl_bulk resets;
};

/* Functions call declaration */
void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
void cadence_qspi_apb_dac_mode_enable(void *reg_base);

int cadence_qspi_apb_command_read(void *reg_base_addr,
				  const struct spi_mem_op *op);
int cadence_qspi_apb_command_write(void *reg_base_addr,
				   const struct spi_mem_op *op);

int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
				const struct spi_mem_op *op);
int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
				  const struct spi_mem_op *op);
int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
				 const struct spi_mem_op *op);
int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
				   const struct spi_mem_op *op);

void cadence_qspi_apb_chipselect(void *reg_base,
	unsigned int chip_select, unsigned int decoder_enable);
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
	unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,
	unsigned int ref_clk, unsigned int sclk_hz,
	unsigned int tshsl_ns, unsigned int tsd2d_ns,
	unsigned int tchsh_ns, unsigned int tslch_ns);
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
void cadence_qspi_apb_readdata_capture(void *reg_base,
	unsigned int bypass, unsigned int delay);

#endif /* __CADENCE_QSPI_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
10e8bf88 SR	2	/*
	3	* Copyright (C) 2012
	4	* Altera Corporation <www.altera.com>
10e8bf88 SR	5	*/
	6
	7	#ifndef __CADENCE_QSPI_H__
	8	#define __CADENCE_QSPI_H__
	9
ac7e14ae SG	10	#include <reset.h>
ac7e14ae SG	11
10e8bf88 SR	12	#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
	13
	14	#define CQSPI_NO_DECODER_MAX_CS 4
	15	#define CQSPI_DECODER_MAX_CS 16
	16	#define CQSPI_READ_CAPTURE_MAX_DELAY 16
	17
8a8d24bd	18	struct cadence_spi_plat {
64c7c8c9	19	unsigned int ref_clk_hz;
10e8bf88 SR	20	unsigned int max_hz;
	21	void *regbase;
	22	void *ahbbase;
15a70a5d JR	23	bool is_decoded_cs;
	24	u32 fifo_depth;
	25	u32 fifo_width;
	26	u32 trigger_address;
ffab2121 VR	27	fdt_addr_t ahbsize;
ffab2121 VR	28	bool use_dac_mode;
10e8bf88	29
15a70a5d	30	/* Flash parameters */
10e8bf88 SR	31	u32 page_size;
	32	u32 block_size;
	33	u32 tshsl_ns;
	34	u32 tsd2d_ns;
	35	u32 tchsh_ns;
	36	u32 tslch_ns;
	37	};
	38
	39	struct cadence_spi_priv {
	40	void *regbase;
	41	void *ahbbase;
	42	size_t cmd_len;
	43	u8 cmd_buf[32];
	44	size_t data_len;
	45
	46	int qspi_is_init;
	47	unsigned int qspi_calibrated_hz;
	48	unsigned int qspi_calibrated_cs;
98fbd71d	49	unsigned int previous_hz;
ac7e14ae SG	50
ac7e14ae SG	51	struct reset_ctl_bulk resets;
10e8bf88 SR	52	};
	53
	54	/* Functions call declaration */
8a8d24bd	55	void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat);
10e8bf88 SR	56	void cadence_qspi_apb_controller_enable(void *reg_base_addr);
10e8bf88 SR	57	void cadence_qspi_apb_controller_disable(void *reg_base_addr);
ffab2121	58	void cadence_qspi_apb_dac_mode_enable(void *reg_base);
10e8bf88 SR	59
10e8bf88 SR	60	int cadence_qspi_apb_command_read(void *reg_base_addr,
d6407720	61	const struct spi_mem_op *op);
10e8bf88	62	int cadence_qspi_apb_command_write(void *reg_base_addr,
d6407720	63	const struct spi_mem_op *op);
10e8bf88	64
8a8d24bd	65	int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
ffab2121	66	const struct spi_mem_op *op);
8a8d24bd	67	int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
ffab2121	68	const struct spi_mem_op *op);
8a8d24bd	69	int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
ffab2121	70	const struct spi_mem_op *op);
8a8d24bd	71	int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
ffab2121	72	const struct spi_mem_op *op);
10e8bf88 SR	73
	74	void cadence_qspi_apb_chipselect(void *reg_base,
	75	unsigned int chip_select, unsigned int decoder_enable);
7d403f28	76	void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
10e8bf88 SR	77	void cadence_qspi_apb_config_baudrate_div(void *reg_base,
	78	unsigned int ref_clk_hz, unsigned int sclk_hz);
	79	void cadence_qspi_apb_delay(void *reg_base,
	80	unsigned int ref_clk, unsigned int sclk_hz,
	81	unsigned int tshsl_ns, unsigned int tsd2d_ns,
	82	unsigned int tchsh_ns, unsigned int tslch_ns);
	83	void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
	84	void cadence_qspi_apb_readdata_capture(void *reg_base,
	85	unsigned int bypass, unsigned int delay);
	86
	87	#endif /* __CADENCE_QSPI_H__ */