[J-u-boot.git] / include / configs / da850evm.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */

/*
 * SoC Configuration
 */
#define CFG_SYS_EXCEPTION_VECTORS_HIGH
#define CFG_SYS_OSCIN_FREQ		24000000
#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)

#ifdef CONFIG_MTD_NOR_FLASH
#define CFG_SYS_DV_NOR_BOOT_CFG	(0x11)
#endif

/*
 * Memory Info
 */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */

/* memtest will be run on 16MB */

#define CFG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */

#define CFG_SYS_DA850_PLL0_PLLM     24
#define CFG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CFG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CFG_SYS_DA850_DDR2_SDBCR2 0

#define CFG_SYS_DA850_DDR2_SDTIMR (		\
	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CFG_SYS_DA850_DDR2_SDTIMR2 (		\
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CFG_SYS_DA850_DDR2_SDRCR    0x00000494
#define CFG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */
#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)

#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)

/*
 * I2C Configuration
 */
#define CFG_SYS_I2C_EXPANDER_ADDR   0x20

/*
 * Flash & Environment
 */
#ifdef CONFIG_MTD_RAW_NAND
#define CFG_SYS_NAND_CS		3
#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CFG_SYS_NAND_MASK_CLE		0x10
#define CFG_SYS_NAND_MASK_ALE		0x8
#define CFG_SYS_NAND_U_BOOT_SIZE	0x40000
#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
#define CFG_SYS_NAND_ECCPOS		{				\
				24, 25, 26, 27, 28, \
				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
				59, 60, 61, 62, 63 }
#define CFG_SYS_NAND_ECCSIZE		512
#define CFG_SYS_NAND_ECCBYTES	10
#endif

#ifdef CONFIG_MTD_NOR_FLASH
#define CFG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
#endif

/*
 * U-Boot general configuration
 */

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)

#define DEFAULT_LINUX_BOOT_ENV \
	"loadaddr=0xc0700000\0" \
	"fdtaddr=0xc0600000\0" \
	"scriptaddr=0xc0600000\0"

#include <environment/ti/mmc.h>

#define CFG_EXTRA_ENV_SETTINGS \
	DEFAULT_LINUX_BOOT_ENV \
	DEFAULT_MMC_TI_ARGS \
	"bootpart=0:2\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"fdtfile=da850-evm.dtb\0" \
	"boot_fdt=yes\0" \
	"boot_fit=0\0" \
	"console=ttyS2,115200n8\0" \
	"hwconfig=dsp:wake=yes"

#ifdef CONFIG_SPL_BUILD
/* defines for SPL */

#endif

/* Load U-Boot Image From MMC */

/* additions for new relocation code, must added to all boards */
#define CFG_SYS_SDRAM_BASE		0xc0000000

#include <asm/arch/hardware.h>

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
89b765c7 SR	2	/*
	3	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	4	*
	5	* Based on davinci_dvevm.h. Original Copyrights follow:
	6	*
	7	* Copyright (C) 2007 Sergey Kubushyn <[email protected]>
89b765c7 SR	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* Board
	15	*/
	16
	17	/*
	18	* SoC Configuration
	19	*/
65cc0e2a TR	20	#define CFG_SYS_EXCEPTION_VECTORS_HIGH
	21	#define CFG_SYS_OSCIN_FREQ 24000000
	22	#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	23	#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
89b765c7	24
7bb33e46	25	#ifdef CONFIG_MTD_NOR_FLASH
65cc0e2a	26	#define CFG_SYS_DV_NOR_BOOT_CFG (0x11)
63777665 LP	27	#endif
63777665 LP	28
89b765c7 SR	29	/*
	30	* Memory Info
	31	*/
89b765c7 SR	32	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
89b765c7 SR	33	#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
8a897c4f	34	#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
89b765c7	35	/* memtest start addr */
89b765c7 SR	36
89b765c7 SR	37	/* memtest will be run on 16MB */
89b765c7	38
65cc0e2a	39	#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
3d2c8e6c CR	40	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	41	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	42	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	43	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	44	DAVINCI_SYSCFG_SUSPSRC_I2C)
	45
	46	/*
	47	* PLL configuration
	48	*/
3d2c8e6c	49
65cc0e2a TR	50	#define CFG_SYS_DA850_PLL0_PLLM 24
65cc0e2a TR	51	#define CFG_SYS_DA850_PLL1_PLLM 21
3d2c8e6c CR	52
	53	/*
	54	* DDR2 memory configuration
	55	*/
65cc0e2a	56	#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
3d2c8e6c CR	57	DV_DDR_PHY_EXT_STRBEN \| \
	58	(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	59
65cc0e2a	60	#define CFG_SYS_DA850_DDR2_SDBCR ( \
3d2c8e6c CR	61	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) \| \
	62	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	63	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	64	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	65	(0x3 << DV_DDR_SDCR_CL_SHIFT) \| \
	66	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	67	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	68
	69	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
65cc0e2a	70	#define CFG_SYS_DA850_DDR2_SDBCR2 0
3d2c8e6c	71
65cc0e2a	72	#define CFG_SYS_DA850_DDR2_SDTIMR ( \
3d2c8e6c CR	73	(14 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	74	(2 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	75	(2 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	76	(1 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	77	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	78	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	79	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	80	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
	81
65cc0e2a	82	#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
3d2c8e6c CR	83	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	84	(0 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	85	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	86	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	87	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	88	(0 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	89	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
	90
65cc0e2a TR	91	#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494
65cc0e2a TR	92	#define CFG_SYS_DA850_DDR2_PBBPR 0x30
3d2c8e6c	93
89b765c7 SR	94	/*
	95	* Serial Driver info
	96	*/
91092132	97	#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
89b765c7	98
65cc0e2a	99	#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
d73a8a1b	100
89b765c7 SR	101	/*
	102	* I2C Configuration
	103	*/
65cc0e2a	104	#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
89b765c7	105
6b2c6468 BG	106	/*
	107	* Flash & Environment
	108	*/
88718be3	109	#ifdef CONFIG_MTD_RAW_NAND
4e590945 TR	110	#define CFG_SYS_NAND_CS 3
	111	#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
	112	#define CFG_SYS_NAND_MASK_CLE 0x10
	113	#define CFG_SYS_NAND_MASK_ALE 0x8
	114	#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000
	115	#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
	116	#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
	117	#define CFG_SYS_NAND_ECCPOS { \
122f9c9b LP	118	24, 25, 26, 27, 28, \
	119	29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
	120	39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
	121	49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
	122	59, 60, 61, 62, 63 }
4e590945 TR	123	#define CFG_SYS_NAND_ECCSIZE 512
4e590945 TR	124	#define CFG_SYS_NAND_ECCBYTES 10
6b2c6468 BG	125	#endif
6b2c6468 BG	126
7bb33e46	127	#ifdef CONFIG_MTD_NOR_FLASH
65cc0e2a	128	#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
1506b0a8	129	#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
93f33627	130	#endif
d73a8a1b	131
89b765c7 SR	132	/*
	133	* U-Boot general configuration
	134	*/
89b765c7 SR	135
	136	/*
	137	* Linux Information
	138	*/
59e0d611	139	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
a4670f8e	140
a4670f8e AF	141	#define DEFAULT_LINUX_BOOT_ENV \
	142	"loadaddr=0xc0700000\0" \
	143	"fdtaddr=0xc0600000\0" \
	144	"scriptaddr=0xc0600000\0"
	145
	146	#include <environment/ti/mmc.h>
	147
0613c36a	148	#define CFG_EXTRA_ENV_SETTINGS \
a4670f8e AF	149	DEFAULT_LINUX_BOOT_ENV \
	150	DEFAULT_MMC_TI_ARGS \
	151	"bootpart=0:2\0" \
	152	"bootdir=/boot\0" \
	153	"bootfile=zImage\0" \
	154	"fdtfile=da850-evm.dtb\0" \
	155	"boot_fdt=yes\0" \
	156	"boot_fit=0\0" \
	157	"console=ttyS2,115200n8\0" \
	158	"hwconfig=dsp:wake=yes"
89b765c7	159
7bb33e46	160	#ifdef CONFIG_SPL_BUILD
3d2c8e6c	161	/* defines for SPL */
a69c4895	162
63777665	163	#endif
0d986e61 LP	164
0d986e61 LP	165	/* Load U-Boot Image From MMC */
0d986e61	166
ab86f72c	167	/* additions for new relocation code, must added to all boards */
aa6e94de	168	#define CFG_SYS_SDRAM_BASE 0xc0000000
63777665	169
89f5eaa1 SG	170	#include <asm/arch/hardware.h>
89f5eaa1 SG	171
89b765c7	172	#endif /* __CONFIG_H */