[J-u-boot.git] / arch / arm / mach-socfpga / qts-filter.sh

#!/bin/sh

#
# helper function to convert from DOS to Unix, if necessary, and handle
# lines ending in '\'.
#
fix_newlines_in_macros() {
	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
}

#
# Process iocsr_config_*.[ch]
# $1:	SoC type
# $2:	Input handoff directory
# $3:	Input BSP Generated directory
# $4:	Output directory
#
process_iocsr_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Altera SoCFPGA IOCSR configuration
 */

#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__

EOF

	# Retrieve the scan chain lengths
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
	grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"

	echo ""

	# Retrieve the scan chain config and zap the ad-hoc length encoding
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/iocsr_config_${soc}.c |
	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
EOF
	) > "${out_dir}/iocsr_config.h"
}

#
# Process pinmux_config_*.c (and ignore pinmux_config.h)
# $1:	SoC type
# $2:	Input directory
# $3:	Output directory
#
process_pinmux_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Altera SoCFPGA PinMux configuration
 */

#ifndef __SOCFPGA_PINMUX_CONFIG_H__
#define __SOCFPGA_PINMUX_CONFIG_H__

EOF

	# Retrieve the pinmux config and zap the ad-hoc length encoding
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/pinmux_config_${soc}.c |
	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
EOF
	) > "${out_dir}/pinmux_config.h"
}

#
# Process pll_config.h
# $1:	SoC type (not used)
# $2:	Input directory
# $3:	Output directory
#
process_pll_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Altera SoCFPGA Clock and PLL configuration
 */

#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__

EOF

	# Retrieve the pll config and zap parenthesis
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/pll_config.h |
	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_PLL_CONFIG_H__ */
EOF
	) > "${out_dir}/pll_config.h"
}

#
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
	egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}

#
# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
# $1:	SoC type (not used)
# $2:	Input directory
# $3:	Output directory
#
process_sdram_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Altera SoCFPGA SDRAM configuration
 *
 */

#ifndef __SOCFPGA_SDRAM_CONFIG_H__
#define __SOCFPGA_SDRAM_CONFIG_H__

EOF

	echo "/* SDRAM configuration */"
	# Retrieve the sdram config, zap broken lines and zap parenthesis
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/sdram/sdram_config.h |
	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer auto configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer defines configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer ac_rom_init configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'

	echo ""
	echo "/* Sequencer inst_rom_init configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
EOF
	) > "${out_dir}/sdram_config.h"
}

usage() {
	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
	echo "Process QTS-generated headers into U-Boot compatible ones."
	echo ""
	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
	echo "  input_qts_dir - Directory with compiled Quartus project"
	echo "                  and containing the Quartus project file (QPF)."
	echo "  input_bsp_dir - Directory with generated bsp containing"
	echo "                  the settings.bsp file."
	echo "  output_dir    - Directory to store the U-Boot compatible"
	echo "                  headers."
	echo ""
}

soc="$1"
in_qts_dir="$2"
in_bsp_dir="$3"
out_dir="$4"

if [ "$#" -ne 4 ] ; then
	usage
	exit 1
fi

if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
	! -d "${out_dir}" -o -z "${soc}" ] ; then
	usage
	exit 3
fi

process_iocsr_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_pll_config    "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_sdram_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
Commit	Line	Data
e996b936 MV	1	#!/bin/sh
e996b936 MV	2
27211b60 BR	3	#
	4	# helper function to convert from DOS to Unix, if necessary, and handle
	5	# lines ending in '\'.
	6	#
	7	fix_newlines_in_macros() {
	8	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
	9	}
	10
e996b936 MV	11	#
	12	# Process iocsr_config_*.[ch]
	13	# $1: SoC type
217db227 DW	14	# $2: Input handoff directory
	15	# $3: Input BSP Generated directory
	16	# $4: Output directory
e996b936 MV	17	#
	18	process_iocsr_config() {
	19	soc="$1"
217db227 DW	20	in_qts_dir="$2"
	21	in_bsp_dir="$3"
	22	out_dir="$4"
e996b936 MV	23
	24	(
	25	cat << EOF
83d290c5	26	/* SPDX-License-Identifier: BSD-3-Clause */
e996b936 MV	27	/*
e996b936 MV	28	* Altera SoCFPGA IOCSR configuration
e996b936 MV	29	*/
	30
	31	#ifndef __SOCFPGA_IOCSR_CONFIG_H__
	32	#define __SOCFPGA_IOCSR_CONFIG_H__
	33
	34	EOF
	35
	36	# Retrieve the scan chain lengths
27211b60 BR	37	fix_newlines_in_macros \
27211b60 BR	38	${in_bsp_dir}/generated/iocsr_config_${soc}.h \|
cc1159bb	39	grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \| tr -d "()"
e996b936 MV	40
	41	echo ""
	42
	43	# Retrieve the scan chain config and zap the ad-hoc length encoding
27211b60 BR	44	fix_newlines_in_macros \
	45	${in_bsp_dir}/generated/iocsr_config_${soc}.c \|
	46	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
e996b936 MV	47
	48	cat << EOF
	49
	50	#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
	51	EOF
	52	) > "${out_dir}/iocsr_config.h"
	53	}
	54
	55	#
	56	# Process pinmux_config_*.c (and ignore pinmux_config.h)
	57	# $1: SoC type
	58	# $2: Input directory
	59	# $3: Output directory
	60	#
	61	process_pinmux_config() {
	62	soc="$1"
217db227 DW	63	in_qts_dir="$2"
	64	in_bsp_dir="$3"
	65	out_dir="$4"
e996b936 MV	66
	67	(
	68	cat << EOF
83d290c5	69	/* SPDX-License-Identifier: BSD-3-Clause */
e996b936 MV	70	/*
e996b936 MV	71	* Altera SoCFPGA PinMux configuration
e996b936 MV	72	*/
	73
	74	#ifndef __SOCFPGA_PINMUX_CONFIG_H__
	75	#define __SOCFPGA_PINMUX_CONFIG_H__
	76
	77	EOF
	78
	79	# Retrieve the pinmux config and zap the ad-hoc length encoding
27211b60 BR	80	fix_newlines_in_macros \
	81	${in_bsp_dir}/generated/pinmux_config_${soc}.c \|
	82	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
e996b936 MV	83
	84	cat << EOF
	85
	86	#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
	87	EOF
	88	) > "${out_dir}/pinmux_config.h"
	89	}
	90
	91	#
	92	# Process pll_config.h
	93	# $1: SoC type (not used)
	94	# $2: Input directory
	95	# $3: Output directory
	96	#
	97	process_pll_config() {
	98	soc="$1"
217db227 DW	99	in_qts_dir="$2"
	100	in_bsp_dir="$3"
	101	out_dir="$4"
e996b936 MV	102
	103	(
	104	cat << EOF
83d290c5	105	/* SPDX-License-Identifier: BSD-3-Clause */
e996b936 MV	106	/*
e996b936 MV	107	* Altera SoCFPGA Clock and PLL configuration
e996b936 MV	108	*/
	109
	110	#ifndef __SOCFPGA_PLL_CONFIG_H__
	111	#define __SOCFPGA_PLL_CONFIG_H__
	112
	113	EOF
	114
	115	# Retrieve the pll config and zap parenthesis
27211b60 BR	116	fix_newlines_in_macros \
27211b60 BR	117	${in_bsp_dir}/generated/pll_config.h \|
cc1159bb	118	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
e996b936 MV	119
	120	cat << EOF
	121
	122	#endif /* __SOCFPGA_PLL_CONFIG_H__ */
	123	EOF
	124	) > "${out_dir}/pll_config.h"
	125	}
	126
	127	#
	128	# Filter out only the macros which are actually used by the code
	129	#
	130	grep_sdram_config() {
cc1159bb	131	egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN\|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT\|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT\|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES\|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES\|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ\|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE\|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS\|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS\|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS\|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS\|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH\|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH\|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN\|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK\|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL\|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA\|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH\|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH\|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP\|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP\|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP\|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP\|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR\|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN\|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST\|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE\|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC\|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY\|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0\|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32\|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0\|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14\|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46\|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0\|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0\|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32\|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0\|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4\|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36\|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0\|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32\|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64\|RW_MGR_ACTIVATE_0_AND_1\|RW_MGR_ACTIVATE_0_AND_1_WAIT1\|RW_MGR_ACTIVATE_0_AND_1_WAIT2\|RW_MGR_ACTIVATE_1\|RW_MGR_CLEAR_DQS_ENABLE\|RW_MGR_EMR_OCD_ENABLE\|RW_MGR_EMR\|RW_MGR_EMR2\|RW_MGR_EMR3\|RW_MGR_GUARANTEED_READ\|RW_MGR_GUARANTEED_READ_CONT\|RW_MGR_GUARANTEED_WRITE\|RW_MGR_GUARANTEED_WRITE_WAIT0\|RW_MGR_GUARANTEED_WRITE_WAIT1\|RW_MGR_GUARANTEED_WRITE_WAIT2\|RW_MGR_GUARANTEED_WRITE_WAIT3\|RW_MGR_IDLE\|RW_MGR_IDLE_LOOP1\|RW_MGR_IDLE_LOOP2\|RW_MGR_INIT_RESET_0_CKE_0\|RW_MGR_INIT_RESET_1_CKE_0\|RW_MGR_INIT_CKE_0\|RW_MGR_LFSR_WR_RD_BANK_0\|RW_MGR_LFSR_WR_RD_BANK_0_DATA\|RW_MGR_LFSR_WR_RD_BANK_0_DQS\|RW_MGR_LFSR_WR_RD_BANK_0_NOP\|RW_MGR_LFSR_WR_RD_BANK_0_WAIT\|RW_MGR_LFSR_WR_RD_BANK_0_WL_1\|RW_MGR_LFSR_WR_RD_DM_BANK_0\|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA\|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS\|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP\|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT\|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1\|RW_MGR_MR_CALIB\|RW_MGR_MR_USER\|RW_MGR_MR_DLL_RESET\|RW_MGR_MRS0_DLL_RESET\|RW_MGR_MRS0_DLL_RESET_MIRR\|RW_MGR_MRS0_USER\|RW_MGR_MRS0_USER_MIRR\|RW_MGR_MRS1\|RW_MGR_MRS1_MIRR\|RW_MGR_MRS2\|RW_MGR_MRS2_MIRR\|RW_MGR_MRS3\|RW_MGR_MRS3_MIRR\|RW_MGR_NOP\|RW_MGR_PRECHARGE_ALL\|RW_MGR_READ_B2B\|RW_MGR_READ_B2B_WAIT1\|RW_MGR_READ_B2B_WAIT2\|RW_MGR_REFRESH\|RW_MGR_REFRESH_ALL\|RW_MGR_RETURN\|RW_MGR_SGLE_READ\|RW_MGR_ZQCL\|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH\|RW_MGR_MEM_ADDRESS_MIRRORING\|RW_MGR_MEM_DATA_MASK_WIDTH\|RW_MGR_MEM_DATA_WIDTH\|RW_MGR_MEM_DQ_PER_READ_DQS\|RW_MGR_MEM_DQ_PER_WRITE_DQS\|RW_MGR_MEM_IF_READ_DQS_WIDTH\|RW_MGR_MEM_IF_WRITE_DQS_WIDTH\|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM\|RW_MGR_MEM_NUMBER_OF_RANKS\|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS\|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS\|IO_DELAY_PER_DCHAIN_TAP\|IO_DELAY_PER_DQS_EN_DCHAIN_TAP\|IO_DELAY_PER_OPA_TAP\|IO_DLL_CHAIN_LENGTH\|IO_DQDQS_OUT_PHASE_MAX\|IO_DQS_EN_DELAY_MAX\|IO_DQS_EN_DELAY_OFFSET\|IO_DQS_EN_PHASE_MAX\|IO_DQS_IN_DELAY_MAX\|IO_DQS_IN_RESERVE\|IO_DQS_OUT_RESERVE\|IO_IO_IN_DELAY_MAX\|IO_IO_OUT1_DELAY_MAX\|IO_IO_OUT2_DELAY_MAX\|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS\|AFI_RATE_RATIO\|AFI_CLK_FREQ\|CALIB_LFIFO_OFFSET\|CALIB_VFIFO_OFFSET\|ENABLE_SUPER_QUICK_CALIBRATION\|MAX_LATENCY_COUNT_WIDTH\|READ_VALID_FIFO_SIZE\|REG_FILE_INIT_SEQ_SIGNATURE\|TINIT_CNTR0_VAL\|TINIT_CNTR1_VAL\|TINIT_CNTR2_VAL\|TRESET_CNTR0_VAL\|TRESET_CNTR1_VAL\|TRESET_CNTR2_VAL\|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR\|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC\|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
e996b936 MV	132	}
	133
	134	#
	135	# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
	136	# $1: SoC type (not used)
	137	# $2: Input directory
	138	# $3: Output directory
	139	#
	140	process_sdram_config() {
	141	soc="$1"
217db227 DW	142	in_qts_dir="$2"
	143	in_bsp_dir="$3"
	144	out_dir="$4"
e996b936 MV	145
	146	(
	147	cat << EOF
f739fcd8	148	/* SPDX-License-Identifier: BSD-3-Clause */
e996b936 MV	149	/*
	150	* Altera SoCFPGA SDRAM configuration
	151	*
e996b936 MV	152	*/
	153
	154	#ifndef __SOCFPGA_SDRAM_CONFIG_H__
	155	#define __SOCFPGA_SDRAM_CONFIG_H__
	156
	157	EOF
	158
	159	echo "/* SDRAM configuration */"
	160	# Retrieve the sdram config, zap broken lines and zap parenthesis
27211b60	161	fix_newlines_in_macros \
217db227	162	${in_bsp_dir}/generated/sdram/sdram_config.h \|
27211b60	163	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \|
cc1159bb	164	sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \|
e996b936 MV	165	sort -u \| grep_sdram_config
	166
	167	echo ""
	168	echo "/* Sequencer auto configuration */"
27211b60	169	fix_newlines_in_macros \
217db227	170	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h \|
27211b60	171	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \|
217db227	172	sort -u \| grep_sdram_config
e996b936 MV	173
	174	echo ""
	175	echo "/* Sequencer defines configuration */"
27211b60	176	fix_newlines_in_macros \
217db227	177	${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h \|
27211b60	178	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \|
217db227	179	sort -u \| grep_sdram_config
e996b936 MV	180
	181	echo ""
	182	echo "/* Sequencer ac_rom_init configuration */"
27211b60 BR	183	fix_newlines_in_macros \
	184	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c \|
	185	sed -n '/^const.\[/ !b; :next {/^const.\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
e996b936 MV	186
	187	echo ""
	188	echo "/* Sequencer inst_rom_init configuration */"
27211b60 BR	189	fix_newlines_in_macros \
	190	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c \|
	191	sed -n '/^const.\[/ !b; :next {/^const.\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
e996b936 MV	192
	193	cat << EOF
	194
	195	#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
	196	EOF
	197	) > "${out_dir}/sdram_config.h"
	198	}
	199
	200	usage() {
217db227	201	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
e996b936 MV	202	echo "Process QTS-generated headers into U-Boot compatible ones."
e996b936 MV	203	echo ""
80da8664 MV	204	echo " soc_type - Type of SoC, either 'cyclone5' or 'arria5'."
	205	echo " input_qts_dir - Directory with compiled Quartus project"
	206	echo " and containing the Quartus project file (QPF)."
	207	echo " input_bsp_dir - Directory with generated bsp containing"
	208	echo " the settings.bsp file."
	209	echo " output_dir - Directory to store the U-Boot compatible"
	210	echo " headers."
e996b936 MV	211	echo ""
	212	}
	213
	214	soc="$1"
217db227 DW	215	in_qts_dir="$2"
	216	in_bsp_dir="$3"
	217	out_dir="$4"
e996b936	218
217db227	219	if [ "$#" -ne 4 ] ; then
e996b936 MV	220	usage
	221	exit 1
	222	fi
	223
217db227 DW	224	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
217db227 DW	225	! -d "${out_dir}" -o -z "${soc}" ] ; then
e996b936 MV	226	usage
	227	exit 3
	228	fi
	229
217db227 DW	230	process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	231	process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	232	process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	233	process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"