[J-u-boot.git] / arch / arc / Kconfig

menu "ARC architecture"
	depends on ARC

config SYS_ARCH
	default "arc"

config SYS_CPU
	default "arcv1" if ISA_ARCOMPACT
	default "arcv2" if ISA_ARCV2

choice
	prompt "ARC Instruction Set"
	default ISA_ARCOMPACT

config ISA_ARCOMPACT
	bool "ARCompact ISA"
	help
	  The original ARC ISA of ARC600/700 cores

config ISA_ARCV2
	bool "ARC ISA v2"
	help
	  ISA for the Next Generation ARC-HS cores

endchoice

choice
	prompt "CPU selection"
	default CPU_ARC770D if ISA_ARCOMPACT
	default CPU_ARCHS38 if ISA_ARCV2

config CPU_ARC750D
	bool "ARC 750D"
	select ARC_MMU_V2
	depends on ISA_ARCOMPACT
	help
	  Choose this option to build an U-Boot for ARC750D CPU.

config CPU_ARC770D
	bool "ARC 770D"
	select ARC_MMU_V3
	depends on ISA_ARCOMPACT
	help
	  Choose this option to build an U-Boot for ARC770D CPU.

config CPU_ARCEM6
	bool "ARC EM6"
	select ARC_MMU_ABSENT
	depends on ISA_ARCV2
	help
	  Next Generation ARC Core based on ISA-v2 ISA without MMU.

config CPU_ARCHS36
	bool "ARC HS36"
	select ARC_MMU_ABSENT
	depends on ISA_ARCV2
	help
	  Next Generation ARC Core based on ISA-v2 ISA without MMU.

config CPU_ARCHS38
	bool "ARC HS38"
	select ARC_MMU_V4
	depends on ISA_ARCV2
	help
	  Next Generation ARC Core based on ISA-v2 ISA with MMU.

endchoice

choice
	prompt "MMU Version"
	default ARC_MMU_V3 if CPU_ARC770D
	default ARC_MMU_V2 if CPU_ARC750D
	default ARC_MMU_ABSENT if CPU_ARCEM6
	default ARC_MMU_ABSENT if CPU_ARCHS36
	default ARC_MMU_V4 if CPU_ARCHS38

config ARC_MMU_ABSENT
	bool "No MMU"
	help
	  No MMU

config ARC_MMU_V2
	bool "MMU v2"
	depends on CPU_ARC750D
	help
	  Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
	  when 2 D-TLB and 1 I-TLB entries index into same 2way set.

config ARC_MMU_V3
	bool "MMU v3"
	depends on CPU_ARC770D
	help
	  Introduced with ARC700 4.10: New Features
	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
	  Shared Address Spaces (SASID)

config ARC_MMU_V4
	bool "MMU v4"
	depends on CPU_ARCHS38
	help
	  Introduced as a part of ARC HS38 release.

endchoice

config CPU_BIG_ENDIAN
	bool "Enable Big Endian Mode"
	default n
	help
	  Build kernel for Big Endian Mode of ARC CPU

config SYS_ICACHE_OFF
	bool "Do not use Instruction Cache"
	default n

config SYS_DCACHE_OFF
	bool "Do not use Data Cache"
	default n

config ARC_CACHE_LINE_SHIFT
	int "Cache Line Length (as power of 2)"
	range 5 7
	default "6"
	depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF
	help
	  Starting with ARC700 4.9, Cache line length is configurable,
	  This option specifies "N", with Line-len = 2 power N
	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
	  Linux only supports same line lengths for I and D caches.

choice
	prompt "Target select"
	optional

config TARGET_TB100
	bool "Support tb100"

config TARGET_ARCANGEL4
	bool "Support arcangel4"

config TARGET_AXS101
	bool "Support axs101"

endchoice

source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
source "board/synopsys/axs101/Kconfig"

endmenu
Commit	Line	Data
dd84058d MY	1	menu "ARC architecture"
	2	depends on ARC
	3
	4	config SYS_ARCH
dd84058d MY	5	default "arc"
dd84058d MY	6
e20bcb04	7	config SYS_CPU
f13606b7 AB	8	default "arcv1" if ISA_ARCOMPACT
	9	default "arcv2" if ISA_ARCV2
	10
	11	choice
	12	prompt "ARC Instruction Set"
	13	default ISA_ARCOMPACT
	14
	15	config ISA_ARCOMPACT
	16	bool "ARCompact ISA"
	17	help
	18	The original ARC ISA of ARC600/700 cores
	19
	20	config ISA_ARCV2
	21	bool "ARC ISA v2"
	22	help
	23	ISA for the Next Generation ARC-HS cores
	24
	25	endchoice
e20bcb04	26
812980bd AB	27	choice
812980bd AB	28	prompt "CPU selection"
f13606b7 AB	29	default CPU_ARC770D if ISA_ARCOMPACT
f13606b7 AB	30	default CPU_ARCHS38 if ISA_ARCV2
812980bd AB	31
	32	config CPU_ARC750D
	33	bool "ARC 750D"
	34	select ARC_MMU_V2
f13606b7	35	depends on ISA_ARCOMPACT
812980bd AB	36	help
	37	Choose this option to build an U-Boot for ARC750D CPU.
	38
	39	config CPU_ARC770D
	40	bool "ARC 770D"
	41	select ARC_MMU_V3
f13606b7	42	depends on ISA_ARCOMPACT
812980bd AB	43	help
	44	Choose this option to build an U-Boot for ARC770D CPU.
	45
f13606b7 AB	46	config CPU_ARCEM6
	47	bool "ARC EM6"
	48	select ARC_MMU_ABSENT
	49	depends on ISA_ARCV2
	50	help
	51	Next Generation ARC Core based on ISA-v2 ISA without MMU.
	52
	53	config CPU_ARCHS36
	54	bool "ARC HS36"
	55	select ARC_MMU_ABSENT
	56	depends on ISA_ARCV2
	57	help
	58	Next Generation ARC Core based on ISA-v2 ISA without MMU.
	59
	60	config CPU_ARCHS38
	61	bool "ARC HS38"
	62	select ARC_MMU_V4
	63	depends on ISA_ARCV2
	64	help
	65	Next Generation ARC Core based on ISA-v2 ISA with MMU.
	66
812980bd AB	67	endchoice
	68
	69	choice
	70	prompt "MMU Version"
	71	default ARC_MMU_V3 if CPU_ARC770D
	72	default ARC_MMU_V2 if CPU_ARC750D
f13606b7 AB	73	default ARC_MMU_ABSENT if CPU_ARCEM6
	74	default ARC_MMU_ABSENT if CPU_ARCHS36
	75	default ARC_MMU_V4 if CPU_ARCHS38
	76
	77	config ARC_MMU_ABSENT
	78	bool "No MMU"
	79	help
	80	No MMU
812980bd AB	81
	82	config ARC_MMU_V2
	83	bool "MMU v2"
	84	depends on CPU_ARC750D
	85	help
	86	Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
	87	when 2 D-TLB and 1 I-TLB entries index into same 2way set.
	88
	89	config ARC_MMU_V3
	90	bool "MMU v3"
	91	depends on CPU_ARC770D
	92	help
	93	Introduced with ARC700 4.10: New Features
	94	Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
	95	Shared Address Spaces (SASID)
	96
f13606b7 AB	97	config ARC_MMU_V4
	98	bool "MMU v4"
	99	depends on CPU_ARCHS38
	100	help
	101	Introduced as a part of ARC HS38 release.
	102
812980bd AB	103	endchoice
812980bd AB	104
1f9ad445 AB	105	config CPU_BIG_ENDIAN
	106	bool "Enable Big Endian Mode"
	107	default n
	108	help
	109	Build kernel for Big Endian Mode of ARC CPU
	110
205e7a7b AB	111	config SYS_ICACHE_OFF
	112	bool "Do not use Instruction Cache"
	113	default n
	114
	115	config SYS_DCACHE_OFF
	116	bool "Do not use Data Cache"
	117	default n
	118
	119	config ARC_CACHE_LINE_SHIFT
	120	int "Cache Line Length (as power of 2)"
	121	range 5 7
	122	default "6"
b903792e	123	depends on !SYS_DCACHE_OFF \|\| !SYS_ICACHE_OFF
205e7a7b AB	124	help
	125	Starting with ARC700 4.9, Cache line length is configurable,
	126	This option specifies "N", with Line-len = 2 power N
	127	So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
	128	Linux only supports same line lengths for I and D caches.
	129
dd84058d MY	130	choice
dd84058d MY	131	prompt "Target select"
a26cd049	132	optional
dd84058d MY	133
	134	config TARGET_TB100
	135	bool "Support tb100"
	136
	137	config TARGET_ARCANGEL4
	138	bool "Support arcangel4"
	139
dd84058d MY	140	config TARGET_AXS101
	141	bool "Support axs101"
	142
	143	endchoice
	144
	145	source "board/abilis/tb100/Kconfig"
	146	source "board/synopsys/Kconfig"
	147	source "board/synopsys/axs101/Kconfig"
	148
	149	endmenu