[J-u-boot.git] / drivers / block / sata_sil.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 * Author: Tang Yuantian <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <pci.h>
#include <command.h>
#include <asm/byteorder.h>
#include <malloc.h>
#include <asm/io.h>
#include <fis.h>
#include <sata.h>
#include <libata.h>
#include <sata.h>
#include "sata_sil.h"

/* Convert sectorsize to wordsize */
#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
#define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))

static struct sata_info sata_info;

static struct pci_device_id supported[] = {
	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
	{}
};

static void sil_sata_dump_fis(struct sata_fis_d2h *s)
{
	printf("Status FIS dump:\n");
	printf("fis_type:		%02x\n", s->fis_type);
	printf("pm_port_i:		%02x\n", s->pm_port_i);
	printf("status:			%02x\n", s->status);
	printf("error:			%02x\n", s->error);
	printf("lba_low:		%02x\n", s->lba_low);
	printf("lba_mid:		%02x\n", s->lba_mid);
	printf("lba_high:		%02x\n", s->lba_high);
	printf("device:			%02x\n", s->device);
	printf("lba_low_exp:		%02x\n", s->lba_low_exp);
	printf("lba_mid_exp:		%02x\n", s->lba_mid_exp);
	printf("lba_high_exp:		%02x\n", s->lba_high_exp);
	printf("res1:			%02x\n", s->res1);
	printf("sector_count:		%02x\n", s->sector_count);
	printf("sector_count_exp:	%02x\n", s->sector_count_exp);
}

static const char *sata_spd_string(unsigned int speed)
{
	static const char * const spd_str[] = {
		"1.5 Gbps",
		"3.0 Gbps",
		"6.0 Gbps",
	};

	if ((speed - 1) > 2)
		return "<unknown>";

	return spd_str[speed - 1];
}

static u32 ata_wait_register(void *reg, u32 mask,
			 u32 val, int timeout_msec)
{
	u32 tmp;

	tmp = readl(reg);
	while ((tmp & mask) == val && timeout_msec > 0) {
		mdelay(1);
		timeout_msec--;
		tmp = readl(reg);
	}

	return tmp;
}

static void sil_config_port(void *port)
{
	/* configure IRQ WoC */
	writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);

	/* zero error counters. */
	writew(0x8000, port + PORT_DECODE_ERR_THRESH);
	writew(0x8000, port + PORT_CRC_ERR_THRESH);
	writew(0x8000, port + PORT_HSHK_ERR_THRESH);
	writew(0x0000, port + PORT_DECODE_ERR_CNT);
	writew(0x0000, port + PORT_CRC_ERR_CNT);
	writew(0x0000, port + PORT_HSHK_ERR_CNT);

	/* always use 64bit activation */
	writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);

	/* clear port multiplier enable and resume bits */
	writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
}

static int sil_init_port(void *port)
{
	u32 tmp;

	writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
	ata_wait_register(port + PORT_CTRL_STAT,
			  PORT_CS_INIT, PORT_CS_INIT, 100);
	tmp = ata_wait_register(port + PORT_CTRL_STAT,
				PORT_CS_RDY, 0, 100);

	if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
		return 1;

	return 0;
}

static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	void *port = sata->port;
	struct sil_prb *prb;
	int i;
	u32 *src, *dst;

	prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
	src = (u32 *)&prb->fis;
	dst = (u32 *)fis;
	for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
		*dst++ = readl(src++);
}

static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	void *port = sata->port;
	u64 paddr = virt_to_bus(sata->devno, pcmd);
	u32 irq_mask, irq_stat;
	int rc;

	writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);

	/* better to add momery barrior here */
	writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
	writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);

	irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
	irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
			0, 10000);

	/* clear IRQs */
	writel(irq_mask, port + PORT_IRQ_STAT);
	irq_stat >>= PORT_IRQ_RAW_SHIFT;

	if (irq_stat & PORT_IRQ_COMPLETE)
		rc = 0;
	else {
		/* force port into known state */
		sil_init_port(port);
		if (irq_stat & PORT_IRQ_ERROR)
			rc = 1; /* error */
		else
			rc = 2; /* busy */
	}

	return rc;
}

static int sil_cmd_set_feature(int dev)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	struct sata_fis_d2h fis;
	u8 udma_cap;
	int ret;

	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
	pcmd->prb.fis.features = SETFEATURES_XFER;

	/* First check the device capablity */
	udma_cap = (u8)(sata->udma & 0xff);
	debug("udma_cap %02x\n", udma_cap);

	if (udma_cap == ATA_UDMA6)
		pcmd->prb.fis.sector_count = XFER_UDMA_6;
	if (udma_cap == ATA_UDMA5)
		pcmd->prb.fis.sector_count = XFER_UDMA_5;
	if (udma_cap == ATA_UDMA4)
		pcmd->prb.fis.sector_count = XFER_UDMA_4;
	if (udma_cap == ATA_UDMA3)
		pcmd->prb.fis.sector_count = XFER_UDMA_3;

	ret = sil_exec_cmd(dev, pcmd, 0);
	if (ret) {
		sil_read_fis(dev, 0, &fis);
		printf("Err: exe cmd(0x%x).\n",
				readl(sata->port + PORT_SERROR));
		sil_sata_dump_fis(&fis);
		return 1;
	}

	return 0;
}

static int sil_cmd_identify_device(int dev, u16 *id)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	struct sata_fis_d2h fis;
	int ret;

	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
	pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	pcmd->prb.fis.command = ATA_CMD_ID_ATA;
	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
	pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
	pcmd->sge.flags = cpu_to_le32(SGE_TRM);

	ret = sil_exec_cmd(dev, pcmd, 0);
	if (ret) {
		sil_read_fis(dev, 0, &fis);
		printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
		sil_sata_dump_fis(&fis);
		return 1;
	}
	ata_swap_buf_le16(id, ATA_ID_WORDS);

	return 0;
}

static int sil_cmd_soft_reset(int dev)
{
	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	struct sata_fis_d2h fis;
	void *port = sata->port;
	int ret;

	/* put the port into known state */
	if (sil_init_port(port)) {
		printf("SRST: port %d not ready\n", dev);
		return 1;
	}

	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));

	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = 0xf;

	ret = sil_exec_cmd(dev, &cmdb, 0);
	if (ret) {
		sil_read_fis(dev, 0, &fis);
		printf("SRST cmd error.\n");
		sil_sata_dump_fis(&fis);
		return 1;
	}

	return 0;
}

static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
		u8 *buffer, int is_write)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	struct sata_fis_d2h fis;
	u64 block;
	int ret;

	block = (u64)start;
	memset(pcmd, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	if (is_write) {
		pcmd->prb.fis.command = ATA_CMD_WRITE;
		pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
	} else {
		pcmd->prb.fis.command = ATA_CMD_READ;
		pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
	}

	pcmd->prb.fis.device = ATA_LBA;
	pcmd->prb.fis.device |= (block >> 24) & 0xf;
	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
	pcmd->prb.fis.lba_low = block & 0xff;
	pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;

	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
	pcmd->sge.flags = cpu_to_le32(SGE_TRM);

	ret = sil_exec_cmd(dev, pcmd, 0);
	if (ret) {
		sil_read_fis(dev, 0, &fis);
		printf("Err: rw cmd(0x%08x).\n",
				readl(sata->port + PORT_SERROR));
		sil_sata_dump_fis(&fis);
		return 1;
	}

	return blkcnt;
}

static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
		u8 *buffer, int is_write)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	struct sata_fis_d2h fis;
	u64 block;
	int ret;

	block = (u64)start;
	memset(pcmd, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	if (is_write) {
		pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
		pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
	} else {
		pcmd->prb.fis.command = ATA_CMD_READ_EXT;
		pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
	}

	pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
	pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
	pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
	pcmd->prb.fis.lba_low = block & 0xff;
	pcmd->prb.fis.device = ATA_LBA;
	pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
	pcmd->prb.fis.sector_count = blkcnt & 0xff;

	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
	pcmd->sge.flags = cpu_to_le32(SGE_TRM);

	ret = sil_exec_cmd(dev, pcmd, 0);
	if (ret) {
		sil_read_fis(dev, 0, &fis);
		printf("Err: rw ext cmd(0x%08x).\n",
				readl(sata->port + PORT_SERROR));
		sil_sata_dump_fis(&fis);
		return 1;
	}

	return blkcnt;
}

static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
			       const void *buffer, int is_write)
{
	ulong start, blks, max_blks;
	u8 *addr;

	start = blknr;
	blks = blkcnt;
	addr = (u8 *)buffer;

	max_blks = ATA_MAX_SECTORS;
	do {
		if (blks > max_blks) {
			sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
			start += max_blks;
			blks -= max_blks;
			addr += ATA_SECT_SIZE * max_blks;
		} else {
			sil_sata_rw_cmd(dev, start, blks, addr, is_write);
			start += blks;
			blks = 0;
			addr += ATA_SECT_SIZE * blks;
		}
	} while (blks != 0);

	return blkcnt;
}

static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
			       const void *buffer, int is_write)
{
	ulong start, blks, max_blks;
	u8 *addr;

	start = blknr;
	blks = blkcnt;
	addr = (u8 *)buffer;

	max_blks = ATA_MAX_SECTORS_LBA48;
	do {
		if (blks > max_blks) {
			sil_sata_rw_cmd_ext(dev, start, max_blks,
					addr, is_write);
			start += max_blks;
			blks -= max_blks;
			addr += ATA_SECT_SIZE * max_blks;
		} else {
			sil_sata_rw_cmd_ext(dev, start, blks,
					addr, is_write);
			start += blks;
			blks = 0;
			addr += ATA_SECT_SIZE * blks;
		}
	} while (blks != 0);

	return blkcnt;
}

static void sil_sata_cmd_flush_cache(int dev)
{
	struct sil_cmd_block cmdb, *pcmd = &cmdb;

	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	pcmd->prb.fis.command = ATA_CMD_FLUSH;

	sil_exec_cmd(dev, pcmd, 0);
}

static void sil_sata_cmd_flush_cache_ext(int dev)
{
	struct sil_cmd_block cmdb, *pcmd = &cmdb;

	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	pcmd->prb.fis.pm_port_c = (1 << 7);
	pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;

	sil_exec_cmd(dev, pcmd, 0);
}

static void sil_sata_init_wcache(int dev, u16 *id)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;

	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
		sata->wcache = 1;
	if (ata_id_has_flush(id))
		sata->flush = 1;
	if (ata_id_has_flush_ext(id))
		sata->flush_ext = 1;
}

static int sil_sata_get_wcache(int dev)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;

	return sata->wcache;
}

static int sil_sata_get_flush(int dev)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;

	return sata->flush;
}

static int sil_sata_get_flush_ext(int dev)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;

	return sata->flush_ext;
}

/*
 * SATA interface between low level driver and command layer
 */
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	ulong rc;

	if (sata->lba48)
		rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
	else
		rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);

	return rc;
}

/*
 * SATA interface between low level driver and command layer
 */
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
	struct sil_sata *sata = sata_dev_desc[dev].priv;
	ulong rc;

	if (sata->lba48) {
		rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
		if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
			sil_sata_cmd_flush_cache_ext(dev);
	} else {
		rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
		if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
			sil_sata_cmd_flush_cache(dev);
	}

	return rc;
}

/*
 * SATA interface between low level driver and command layer
 */
int init_sata(int dev)
{
	static int init_done, idx;
	pci_dev_t devno;
	u16 word;

	if (init_done == 1 && dev < sata_info.maxport)
		return 0;

	init_done = 1;

	/* Find PCI device(s) */
	devno = pci_find_devices(supported, idx++);
	if (devno == -1)
		return 1;

	pci_read_config_word(devno, PCI_DEVICE_ID, &word);

	/* get the port count */
	word &= 0xf;

	sata_info.portbase = sata_info.maxport;
	sata_info.maxport = sata_info.portbase + word;
	sata_info.devno = devno;

	/* Read out all BARs */
	sata_info.iobase[0] = (ulong)pci_map_bar(devno,
			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
	sata_info.iobase[1] = (ulong)pci_map_bar(devno,
			PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
	sata_info.iobase[2] = (ulong)pci_map_bar(devno,
			PCI_BASE_ADDRESS_4, PCI_REGION_MEM);

	/* mask out the unused bits */
	sata_info.iobase[0] &= 0xffffff80;
	sata_info.iobase[1] &= 0xfffffc00;
	sata_info.iobase[2] &= 0xffffff80;

	/* Enable Bus Mastering and memory region */
	pci_write_config_word(devno, PCI_COMMAND,
			PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

	/* Check if mem accesses and Bus Mastering are enabled. */
	pci_read_config_word(devno, PCI_COMMAND, &word);
	if (!(word & PCI_COMMAND_MEMORY) ||
			(!(word & PCI_COMMAND_MASTER))) {
		printf("Error: Can not enable MEM access or Bus Mastering.\n");
		debug("PCI command: %04x\n", word);
		return 1;
	}

	/* GPIO off */
	writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
	/* clear global reset & mask interrupts during initialization */
	writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));

	return 0;
}

int reset_sata(int dev)
{
	return 0;
}

/*
 * SATA interface between low level driver and command layer
 */
int scan_sata(int dev)
{
	unsigned char serial[ATA_ID_SERNO_LEN + 1];
	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
	unsigned char product[ATA_ID_PROD_LEN + 1];
	struct sil_sata *sata;
	void *port;
	int cnt;
	u16 *id;
	u32 tmp;

	if (dev >= sata_info.maxport) {
		printf("SATA#%d is not present\n", dev);
		return 1;
	}

	printf("SATA#%d\n", dev);
	port = (void *)sata_info.iobase[1] +
		PORT_REGS_SIZE * (dev - sata_info.portbase);

	/* Initial PHY setting */
	writel(0x20c, port + PORT_PHY_CFG);

	/* clear port RST */
	tmp = readl(port + PORT_CTRL_STAT);
	if (tmp & PORT_CS_PORT_RST) {
		writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
		tmp = ata_wait_register(port + PORT_CTRL_STAT,
				PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
		if (tmp & PORT_CS_PORT_RST)
			printf("Err: Failed to clear port RST\n");
	}

	/* Check if device is present */
	for (cnt = 0; cnt < 100; cnt++) {
		tmp = readl(port + PORT_SSTATUS);
		if ((tmp & 0xF) == 0x3)
			break;
		mdelay(1);
	}

	tmp = readl(port + PORT_SSTATUS);
	if ((tmp & 0xf) != 0x3) {
		printf("	(No RDY)\n");
		return 1;
	}

	/* Wait for port ready */
	tmp = ata_wait_register(port + PORT_CTRL_STAT,
				PORT_CS_RDY, PORT_CS_RDY, 100);
	if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
		printf("%d port not ready.\n", dev);
		return 1;
	}

	/* configure port */
	sil_config_port(port);

	/* Reset port */
	writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
	readl(port + PORT_CTRL_STAT);
	tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
				PORT_CS_DEV_RST, 100);
	if (tmp & PORT_CS_DEV_RST) {
		printf("%d port reset failed.\n", dev);
		return 1;
	}

	sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
	if (!sata) {
		printf("%d no memory.\n", dev);
		return 1;
	}
	memset((void *)sata, 0, sizeof(struct sil_sata));

	/* turn on port interrupt */
	tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
	tmp |= (1 << (dev - sata_info.portbase));
	writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));

	/* Save the private struct to block device struct */
	sata_dev_desc[dev].priv = (void *)sata;
	sata->port = port;
	sata->devno = sata_info.devno;
	sprintf(sata->name, "SATA#%d", dev);
	sil_cmd_soft_reset(dev);
	tmp = readl(port + PORT_SSTATUS);
	tmp = (tmp >> 4) & 0xf;
	printf("	(%s)\n", sata_spd_string(tmp));

	id = (u16 *)malloc(ATA_ID_WORDS * 2);
	if (!id) {
		printf("Id malloc failed\n");
		free((void *)sata);
		return 1;
	}
	sil_cmd_identify_device(dev, id);

#ifdef CONFIG_LBA48
	/* Check if support LBA48 */
	if (ata_id_has_lba48(id)) {
		sata_dev_desc[dev].lba48 = 1;
		sata->lba48 = 1;
		debug("Device supports LBA48\n");
	} else
		debug("Device supports LBA28\n");
#endif

	/* Serial number */
	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
	memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));

	/* Firmware version */
	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
	memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));

	/* Product model */
	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
	memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));

	/* Totoal sectors */
	sata_dev_desc[dev].lba = ata_id_n_sectors(id);

	sil_sata_init_wcache(dev, id);
	sil_cmd_set_feature(dev);

#ifdef DEBUG
	sil_cmd_identify_device(dev, id);
	ata_dump_id(id);
#endif
	free((void *)id);

	return 0;
}
Commit	Line	Data
83c484d7 TY	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	* Author: Tang Yuantian <[email protected]>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
83c484d7 TY	6	*/
	7
	8	#include <common.h>
	9	#include <pci.h>
	10	#include <command.h>
	11	#include <asm/byteorder.h>
	12	#include <malloc.h>
	13	#include <asm/io.h>
	14	#include <fis.h>
e46a4350	15	#include <sata.h>
83c484d7	16	#include <libata.h>
00caa7f5	17	#include <sata.h>
83c484d7 TY	18	#include "sata_sil.h"
	19
	20	/* Convert sectorsize to wordsize */
	21	#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
83c484d7 TY	22	#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
	23
	24	static struct sata_info sata_info;
	25
	26	static struct pci_device_id supported[] = {
	27	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
	28	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
	29	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
	30	{}
	31	};
	32
	33	static void sil_sata_dump_fis(struct sata_fis_d2h *s)
	34	{
	35	printf("Status FIS dump:\n");
	36	printf("fis_type: %02x\n", s->fis_type);
	37	printf("pm_port_i: %02x\n", s->pm_port_i);
	38	printf("status: %02x\n", s->status);
	39	printf("error: %02x\n", s->error);
	40	printf("lba_low: %02x\n", s->lba_low);
	41	printf("lba_mid: %02x\n", s->lba_mid);
	42	printf("lba_high: %02x\n", s->lba_high);
	43	printf("device: %02x\n", s->device);
	44	printf("lba_low_exp: %02x\n", s->lba_low_exp);
	45	printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
	46	printf("lba_high_exp: %02x\n", s->lba_high_exp);
	47	printf("res1: %02x\n", s->res1);
	48	printf("sector_count: %02x\n", s->sector_count);
	49	printf("sector_count_exp: %02x\n", s->sector_count_exp);
	50	}
	51
	52	static const char *sata_spd_string(unsigned int speed)
	53	{
	54	static const char * const spd_str[] = {
	55	"1.5 Gbps",
	56	"3.0 Gbps",
	57	"6.0 Gbps",
	58	};
	59
	60	if ((speed - 1) > 2)
	61	return "<unknown>";
	62
	63	return spd_str[speed - 1];
	64	}
	65
	66	static u32 ata_wait_register(void *reg, u32 mask,
	67	u32 val, int timeout_msec)
	68	{
	69	u32 tmp;
	70
	71	tmp = readl(reg);
	72	while ((tmp & mask) == val && timeout_msec > 0) {
	73	mdelay(1);
	74	timeout_msec--;
	75	tmp = readl(reg);
	76	}
	77
	78	return tmp;
	79	}
	80
	81	static void sil_config_port(void *port)
	82	{
	83	/* configure IRQ WoC */
	84	writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
	85
86	/* zero error counters. */
87	writew(0x8000, port + PORT_DECODE_ERR_THRESH);
88	writew(0x8000, port + PORT_CRC_ERR_THRESH);
89	writew(0x8000, port + PORT_HSHK_ERR_THRESH);
90	writew(0x0000, port + PORT_DECODE_ERR_CNT);
91	writew(0x0000, port + PORT_CRC_ERR_CNT);
92	writew(0x0000, port + PORT_HSHK_ERR_CNT);
93
94	/* always use 64bit activation */
95	writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
96
97	/* clear port multiplier enable and resume bits */
98	writel(PORT_CS_PMP_EN \| PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
99	}
100
101	static int sil_init_port(void *port)
102	{
103	u32 tmp;
104
105	writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
106	ata_wait_register(port + PORT_CTRL_STAT,
107	PORT_CS_INIT, PORT_CS_INIT, 100);
108	tmp = ata_wait_register(port + PORT_CTRL_STAT,
109	PORT_CS_RDY, 0, 100);
110
111	if ((tmp & (PORT_CS_INIT \| PORT_CS_RDY)) != PORT_CS_RDY)
112	return 1;
113
114	return 0;
115	}
116
117	static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
118	{
119	struct sil_sata *sata = sata_dev_desc[dev].priv;
120	void *port = sata->port;
121	struct sil_prb *prb;
122	int i;
123	u32 src, dst;
124
125	prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
126	src = (u32 *)&prb->fis;
127	dst = (u32 *)fis;
128	for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
129	*dst++ = readl(src++);
130	}
131
132	static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
133	{
134	struct sil_sata *sata = sata_dev_desc[dev].priv;
135	void *port = sata->port;
136	u64 paddr = virt_to_bus(sata->devno, pcmd);
137	u32 irq_mask, irq_stat;
138	int rc;
139
140	writel(PORT_IRQ_COMPLETE \| PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
141
142	/* better to add momery barrior here */
143	writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
144	writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
145
146	irq_mask = (PORT_IRQ_COMPLETE \| PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
147	irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
148	0, 10000);
149
150	/* clear IRQs */
151	writel(irq_mask, port + PORT_IRQ_STAT);
152	irq_stat >>= PORT_IRQ_RAW_SHIFT;
153
154	if (irq_stat & PORT_IRQ_COMPLETE)
155	rc = 0;
156	else {
157	/* force port into known state */
158	sil_init_port(port);
159	if (irq_stat & PORT_IRQ_ERROR)
160	rc = 1; /* error */
161	else
162	rc = 2; /* busy */
163	}
164
165	return rc;
166	}
167
168	static int sil_cmd_set_feature(int dev)
169	{
170	struct sil_sata *sata = sata_dev_desc[dev].priv;
171	struct sil_cmd_block cmdb, *pcmd = &cmdb;
172	struct sata_fis_d2h fis;
173	u8 udma_cap;
174	int ret;
175
176	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
177	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
178	pcmd->prb.fis.pm_port_c = (1 << 7);
179	pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
180	pcmd->prb.fis.features = SETFEATURES_XFER;
181
182	/* First check the device capablity */
183	udma_cap = (u8)(sata->udma & 0xff);
184	debug("udma_cap %02x\n", udma_cap);
185
186	if (udma_cap == ATA_UDMA6)
187	pcmd->prb.fis.sector_count = XFER_UDMA_6;
188	if (udma_cap == ATA_UDMA5)
189	pcmd->prb.fis.sector_count = XFER_UDMA_5;
190	if (udma_cap == ATA_UDMA4)
191	pcmd->prb.fis.sector_count = XFER_UDMA_4;
192	if (udma_cap == ATA_UDMA3)
193	pcmd->prb.fis.sector_count = XFER_UDMA_3;
194
195	ret = sil_exec_cmd(dev, pcmd, 0);
196	if (ret) {
197	sil_read_fis(dev, 0, &fis);
198	printf("Err: exe cmd(0x%x).\n",
199	readl(sata->port + PORT_SERROR));
200	sil_sata_dump_fis(&fis);
201	return 1;
202	}
203
204	return 0;
205	}
206
207	static int sil_cmd_identify_device(int dev, u16 *id)
208	{
209	struct sil_sata *sata = sata_dev_desc[dev].priv;
210	struct sil_cmd_block cmdb, *pcmd = &cmdb;
211	struct sata_fis_d2h fis;
212	int ret;
213
214	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
215	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
216	pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
217	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
218	pcmd->prb.fis.pm_port_c = (1 << 7);
219	pcmd->prb.fis.command = ATA_CMD_ID_ATA;
220	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
221	pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
222	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
223
224	ret = sil_exec_cmd(dev, pcmd, 0);
225	if (ret) {
226	sil_read_fis(dev, 0, &fis);
227	printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
228	sil_sata_dump_fis(&fis);
229	return 1;
230	}
231	ata_swap_buf_le16(id, ATA_ID_WORDS);
232
233	return 0;
234	}
235
236	static int sil_cmd_soft_reset(int dev)
237	{
238	struct sil_cmd_block cmdb, *pcmd = &cmdb;
239	struct sil_sata *sata = sata_dev_desc[dev].priv;
240	struct sata_fis_d2h fis;
241	void *port = sata->port;
242	int ret;
243
244	/* put the port into known state */
245	if (sil_init_port(port)) {
246	printf("SRST: port %d not ready\n", dev);
247	return 1;
248	}
249
250	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
251
252	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
253	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
254	pcmd->prb.fis.pm_port_c = 0xf;
255
256	ret = sil_exec_cmd(dev, &cmdb, 0);
257	if (ret) {
258	sil_read_fis(dev, 0, &fis);
259	printf("SRST cmd error.\n");
260	sil_sata_dump_fis(&fis);
261	return 1;
262	}
263
264	return 0;
265	}
266
267	static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
268	u8 *buffer, int is_write)
269	{
270	struct sil_sata *sata = sata_dev_desc[dev].priv;
271	struct sil_cmd_block cmdb, *pcmd = &cmdb;
272	struct sata_fis_d2h fis;
273	u64 block;
274	int ret;
275
276	block = (u64)start;
277	memset(pcmd, 0, sizeof(struct sil_cmd_block));
278	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
279	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
280	pcmd->prb.fis.pm_port_c = (1 << 7);
281	if (is_write) {
282	pcmd->prb.fis.command = ATA_CMD_WRITE;
283	pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
284	} else {
285	pcmd->prb.fis.command = ATA_CMD_READ;
286	pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
287	}
288
289	pcmd->prb.fis.device = ATA_LBA;
290	pcmd->prb.fis.device \|= (block >> 24) & 0xf;
291	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
292	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
293	pcmd->prb.fis.lba_low = block & 0xff;
294	pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
295
296	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
297	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
298	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
299
300	ret = sil_exec_cmd(dev, pcmd, 0);
301	if (ret) {
302	sil_read_fis(dev, 0, &fis);
303	printf("Err: rw cmd(0x%08x).\n",
304	readl(sata->port + PORT_SERROR));
305	sil_sata_dump_fis(&fis);
306	return 1;
307	}
308
309	return blkcnt;
310	}
311
312	static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
313	u8 *buffer, int is_write)
314	{
315	struct sil_sata *sata = sata_dev_desc[dev].priv;
316	struct sil_cmd_block cmdb, *pcmd = &cmdb;
317	struct sata_fis_d2h fis;
318	u64 block;
319	int ret;
320
321	block = (u64)start;
322	memset(pcmd, 0, sizeof(struct sil_cmd_block));
323	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
324	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
325	pcmd->prb.fis.pm_port_c = (1 << 7);
326	if (is_write) {
327	pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
328	pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
329	} else {
330	pcmd->prb.fis.command = ATA_CMD_READ_EXT;
331	pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
332	}
333
334	pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
335	pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
336	pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
337	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
338	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
339	pcmd->prb.fis.lba_low = block & 0xff;
340	pcmd->prb.fis.device = ATA_LBA;
341	pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
342	pcmd->prb.fis.sector_count = blkcnt & 0xff;
343
344	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
345	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
346	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
347
348	ret = sil_exec_cmd(dev, pcmd, 0);
349	if (ret) {
350	sil_read_fis(dev, 0, &fis);
351	printf("Err: rw ext cmd(0x%08x).\n",
352	readl(sata->port + PORT_SERROR));
353	sil_sata_dump_fis(&fis);
354	return 1;
355	}
356
357	return blkcnt;
358	}
359
00caa7f5 KP	360	static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
00caa7f5 KP	361	const void *buffer, int is_write)
83c484d7 TY	362	{
	363	ulong start, blks, max_blks;
	364	u8 *addr;
	365
	366	start = blknr;
	367	blks = blkcnt;
	368	addr = (u8 *)buffer;
	369
	370	max_blks = ATA_MAX_SECTORS;
	371	do {
	372	if (blks > max_blks) {
	373	sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
	374	start += max_blks;
	375	blks -= max_blks;
	376	addr += ATA_SECT_SIZE * max_blks;
	377	} else {
	378	sil_sata_rw_cmd(dev, start, blks, addr, is_write);
	379	start += blks;
	380	blks = 0;
	381	addr += ATA_SECT_SIZE * blks;
	382	}
	383	} while (blks != 0);
	384
	385	return blkcnt;
	386	}
	387
00caa7f5 KP	388	static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
00caa7f5 KP	389	const void *buffer, int is_write)
83c484d7 TY	390	{
	391	ulong start, blks, max_blks;
	392	u8 *addr;
	393
	394	start = blknr;
	395	blks = blkcnt;
	396	addr = (u8 *)buffer;
	397
	398	max_blks = ATA_MAX_SECTORS_LBA48;
	399	do {
	400	if (blks > max_blks) {
	401	sil_sata_rw_cmd_ext(dev, start, max_blks,
	402	addr, is_write);
	403	start += max_blks;
	404	blks -= max_blks;
	405	addr += ATA_SECT_SIZE * max_blks;
	406	} else {
	407	sil_sata_rw_cmd_ext(dev, start, blks,
	408	addr, is_write);
	409	start += blks;
	410	blks = 0;
	411	addr += ATA_SECT_SIZE * blks;
	412	}
	413	} while (blks != 0);
	414
	415	return blkcnt;
	416	}
	417
00caa7f5	418	static void sil_sata_cmd_flush_cache(int dev)
83c484d7 TY	419	{
	420	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	421
	422	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
	423	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	424	pcmd->prb.fis.pm_port_c = (1 << 7);
	425	pcmd->prb.fis.command = ATA_CMD_FLUSH;
	426
	427	sil_exec_cmd(dev, pcmd, 0);
	428	}
	429
00caa7f5	430	static void sil_sata_cmd_flush_cache_ext(int dev)
83c484d7 TY	431	{
	432	struct sil_cmd_block cmdb, *pcmd = &cmdb;
	433
	434	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
	435	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
	436	pcmd->prb.fis.pm_port_c = (1 << 7);
	437	pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
	438
	439	sil_exec_cmd(dev, pcmd, 0);
	440	}
	441
	442	static void sil_sata_init_wcache(int dev, u16 *id)
	443	{
	444	struct sil_sata *sata = sata_dev_desc[dev].priv;
	445
	446	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
	447	sata->wcache = 1;
	448	if (ata_id_has_flush(id))
	449	sata->flush = 1;
	450	if (ata_id_has_flush_ext(id))
	451	sata->flush_ext = 1;
	452	}
	453
	454	static int sil_sata_get_wcache(int dev)
	455	{
	456	struct sil_sata *sata = sata_dev_desc[dev].priv;
	457
	458	return sata->wcache;
	459	}
	460
	461	static int sil_sata_get_flush(int dev)
	462	{
	463	struct sil_sata *sata = sata_dev_desc[dev].priv;
	464
	465	return sata->flush;
	466	}
	467
	468	static int sil_sata_get_flush_ext(int dev)
	469	{
	470	struct sil_sata *sata = sata_dev_desc[dev].priv;
	471
	472	return sata->flush_ext;
	473	}
	474
	475	/*
	476	* SATA interface between low level driver and command layer
	477	*/
	478	ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
	479	{
	480	struct sil_sata *sata = sata_dev_desc[dev].priv;
	481	ulong rc;
	482
	483	if (sata->lba48)
	484	rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
	485	else
	486	rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
	487
	488	return rc;
	489	}
	490
	491	/*
	492	* SATA interface between low level driver and command layer
	493	*/
0e7d856e	494	ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
83c484d7 TY	495	{
	496	struct sil_sata *sata = sata_dev_desc[dev].priv;
	497	ulong rc;
	498
	499	if (sata->lba48) {
	500	rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
	501	if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
	502	sil_sata_cmd_flush_cache_ext(dev);
	503	} else {
	504	rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
	505	if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
	506	sil_sata_cmd_flush_cache(dev);
	507	}
	508
	509	return rc;
	510	}
	511
	512	/*
	513	* SATA interface between low level driver and command layer
	514	*/
	515	int init_sata(int dev)
	516	{
	517	static int init_done, idx;
	518	pci_dev_t devno;
	519	u16 word;
	520
	521	if (init_done == 1 && dev < sata_info.maxport)
1b51d32c	522	return 0;
83c484d7 TY	523
	524	init_done = 1;
	525
	526	/* Find PCI device(s) */
	527	devno = pci_find_devices(supported, idx++);
	528	if (devno == -1)
	529	return 1;
	530
	531	pci_read_config_word(devno, PCI_DEVICE_ID, &word);
	532
	533	/* get the port count */
	534	word &= 0xf;
	535
	536	sata_info.portbase = sata_info.maxport;
	537	sata_info.maxport = sata_info.portbase + word;
	538	sata_info.devno = devno;
	539
	540	/* Read out all BARs */
	541	sata_info.iobase[0] = (ulong)pci_map_bar(devno,
	542	PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
	543	sata_info.iobase[1] = (ulong)pci_map_bar(devno,
	544	PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
	545	sata_info.iobase[2] = (ulong)pci_map_bar(devno,
	546	PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
	547
	548	/* mask out the unused bits */
	549	sata_info.iobase[0] &= 0xffffff80;
	550	sata_info.iobase[1] &= 0xfffffc00;
	551	sata_info.iobase[2] &= 0xffffff80;
	552
	553	/* Enable Bus Mastering and memory region */
	554	pci_write_config_word(devno, PCI_COMMAND,
	555	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	556
	557	/* Check if mem accesses and Bus Mastering are enabled. */
	558	pci_read_config_word(devno, PCI_COMMAND, &word);
	559	if (!(word & PCI_COMMAND_MEMORY) \|\|
	560	(!(word & PCI_COMMAND_MASTER))) {
	561	printf("Error: Can not enable MEM access or Bus Mastering.\n");
	562	debug("PCI command: %04x\n", word);
	563	return 1;
	564	}
	565
	566	/* GPIO off */
	567	writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
	568	/* clear global reset & mask interrupts during initialization */
	569	writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
	570
	571	return 0;
	572	}
	573
10ee8eca NK	574	int reset_sata(int dev)
	575	{
	576	return 0;
	577	}
	578
83c484d7 TY	579	/*
	580	* SATA interface between low level driver and command layer
	581	*/
	582	int scan_sata(int dev)
	583	{
	584	unsigned char serial[ATA_ID_SERNO_LEN + 1];
	585	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
	586	unsigned char product[ATA_ID_PROD_LEN + 1];
	587	struct sil_sata *sata;
	588	void *port;
	589	int cnt;
	590	u16 *id;
	591	u32 tmp;
	592
	593	if (dev >= sata_info.maxport) {
	594	printf("SATA#%d is not present\n", dev);
	595	return 1;
	596	}
	597
	598	printf("SATA#%d\n", dev);
	599	port = (void *)sata_info.iobase[1] +
	600	PORT_REGS_SIZE * (dev - sata_info.portbase);
	601
	602	/* Initial PHY setting */
	603	writel(0x20c, port + PORT_PHY_CFG);
	604
	605	/* clear port RST */
	606	tmp = readl(port + PORT_CTRL_STAT);
	607	if (tmp & PORT_CS_PORT_RST) {
	608	writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
	609	tmp = ata_wait_register(port + PORT_CTRL_STAT,
	610	PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
	611	if (tmp & PORT_CS_PORT_RST)
	612	printf("Err: Failed to clear port RST\n");
	613	}
	614
	615	/* Check if device is present */
	616	for (cnt = 0; cnt < 100; cnt++) {
	617	tmp = readl(port + PORT_SSTATUS);
	618	if ((tmp & 0xF) == 0x3)
	619	break;
	620	mdelay(1);
	621	}
	622
	623	tmp = readl(port + PORT_SSTATUS);
	624	if ((tmp & 0xf) != 0x3) {
	625	printf(" (No RDY)\n");
	626	return 1;
	627	}
	628
	629	/* Wait for port ready */
	630	tmp = ata_wait_register(port + PORT_CTRL_STAT,
	631	PORT_CS_RDY, PORT_CS_RDY, 100);
	632	if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
	633	printf("%d port not ready.\n", dev);
	634	return 1;
	635	}
	636
	637	/* configure port */
	638	sil_config_port(port);
	639
	640	/* Reset port */
	641	writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
	642	readl(port + PORT_CTRL_STAT);
643	tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
644	PORT_CS_DEV_RST, 100);
645	if (tmp & PORT_CS_DEV_RST) {
646	printf("%d port reset failed.\n", dev);
647	return 1;
648	}
649
650	sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
651	if (!sata) {
652	printf("%d no memory.\n", dev);
653	return 1;
654	}
655	memset((void *)sata, 0, sizeof(struct sil_sata));
656
657	/* turn on port interrupt */
658	tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
659	tmp \|= (1 << (dev - sata_info.portbase));
660	writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
661
662	/* Save the private struct to block device struct */
663	sata_dev_desc[dev].priv = (void *)sata;
664	sata->port = port;
665	sata->devno = sata_info.devno;
666	sprintf(sata->name, "SATA#%d", dev);
667	sil_cmd_soft_reset(dev);
668	tmp = readl(port + PORT_SSTATUS);
669	tmp = (tmp >> 4) & 0xf;
670	printf(" (%s)\n", sata_spd_string(tmp));
671
672	id = (u16 )malloc(ATA_ID_WORDS 2);
673	if (!id) {
674	printf("Id malloc failed\n");
675	free((void *)sata);
676	return 1;
677	}
678	sil_cmd_identify_device(dev, id);
679
680	#ifdef CONFIG_LBA48
681	/* Check if support LBA48 */
682	if (ata_id_has_lba48(id)) {
683	sata_dev_desc[dev].lba48 = 1;
684	sata->lba48 = 1;
685	debug("Device supports LBA48\n");
686	} else
687	debug("Device supports LBA28\n");
688	#endif
689
690	/* Serial number */
691	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
692	memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
693
694	/* Firmware version */
695	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
696	memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
697
698	/* Product model */
699	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
700	memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
701
702	/* Totoal sectors */
703	sata_dev_desc[dev].lba = ata_id_n_sectors(id);
704
705	sil_sata_init_wcache(dev, id);
706	sil_cmd_set_feature(dev);
707
708	#ifdef DEBUG
709	sil_cmd_identify_device(dev, id);
710	ata_dump_id(id);
711	#endif
712	free((void *)id);
713
714	return 0;
715	}