[J-u-boot.git] / doc / README.adnpesc1_base32


TODO:	specify IDE i/f


===============================================================================
	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
===============================================================================
see also [1]-[5]

CPU:	"DNP_ESC1"
	32 bit NIOS for 50 MHz
	512 Byte for register file (30 levels)
	with out instruction cache
	with out data cache
	2 KByte On Chip ROM with GERMS boot monitor
	with out On Chip RAM
	MSTEP multiplier
	no Debug Core
	no On Chip Instrumentation (OCI)

	U-Boot CFG:	CFG_NIOS_CPU_CLK	     = 50000000
			CFG_NIOS_CPU_ICACHE	     = (not present)
			CFG_NIOS_CPU_DCACHE	     = (not present)
			CFG_NIOS_CPU_REG_NUMS	     = 512
			CFG_NIOS_CPU_MUL	     = 0
			CFG_NIOS_CPU_MSTEP	     = 1
			CFG_NIOS_CPU_DBG_CORE	     = 0

IRQ:	 Nr.  | used by
	------+--------------------------------------------------------
	 16   | TIMER0	  |  CFG_NIOS_CPU_TIMER0_IRQ = 16
	 17   | UART0	  |  CFG_NIOS_CPU_UART0_IRQ  = 17
	 18   | UART1	  |  CFG_NIOS_CPU_UART1_IRQ  = 18
	 20   | LAN91C111 |  CFG_NIOS_CPU_LAN0_IRQ   =
	      | PIO6	  |  CFG_NIOS_CPU_PIO6_IRQ   = 20
	 25   | SPI0	  |  CFG_NIOS_CPU_SPI0_IRQ   = 25
	 31   | PIO7	  |  CFG_NIOS_CPU_PIO7_IRQ   = 31
	 32   | PIO8	  |  CFG_NIOS_CPU_PIO8_IRQ   = 32
	 33   | PIO9	  |  CFG_NIOS_CPU_PIO9_IRQ   = 33
	 34   | PIO10	  |  CFG_NIOS_CPU_PIO10_IRQ  = 34
	 35   | PIO11	  |  CFG_NIOS_CPU_PIO11_IRQ  = 35
	 36   | PIO12	  |  CFG_NIOS_CPU_PIO12_IRQ  =
	      | IDE0	  |  CFG_NIOS_CPU_IDE0_IRQ   = 36
	 37   | PIO13	  |  CFG_NIOS_CPU_PIO13_IRQ  =
	      | IDE1	  |  CFG_NIOS_CPU_IDE1_IRQ   = 37

MEMORY:	 8 MByte Flash
	16 MByte SDRAM

Timer:	TIMER0: high priority programmable timer (IRQ16)

	U-Boot CFG:	CFG_NIOS_CPU_TICK_TIMER	     = 0
			CFG_NIOS_CPU_USER_TIMER	     = (not present)

PIO:	 Nr.  | description
	------+--------------------------------------------------------
	 PIO0 | PORTA:      8 in/outputs for general purpose usage
	 PIO1 | PORTB:      8 in/outputs for general purpose usage
	 PIO2 | PORTC:      4 in/outputs for general purpose usage
	 PIO3 | RCM:	    1 input for RCM_EN# jumper (Req.Conf.Mon.)
	 PIO4 | WDTENA:	    1 output to enable the on-board watchdog
	 PIO5 | WDTTRIG:    1 output to trigger the on-board watchdog
	 PIO6 | LAN0INT:    1 input for LAN91C111 irq input (IRQ20)
	 PIO7 | INT1:	    1 input for general purpose irq (IRQ31)
	 PIO8 | INT2:	    1 input for general purpose irq (IRQ32)
	 PIO9 | INT3:	    1 input for general purpose irq (IRQ33)
	 PIO10| INT4:	    1 input for general purpose irq (IRQ34)
	 PIO11| INT5:	    1 input for general purpose irq (IRQ35)
	 PIO12| INT6:	    1 input for general purpose irq (IRQ36)
	      | IDE0INT:     (same) for IDE0 irq input
	 PIO13| INT7:	    1 input for general purpose irq (IRQ37)
	      | IDE1INT:     (same) for IDE1 irq input

	U-Boot CFG:	CFG_NIOS_CPU_PORTA_PIO	     = 0
			CFG_NIOS_CPU_PORTB_PIO	     = 1
			CFG_NIOS_CPU_PORTC_PIO	     = 2
			CFG_NIOS_CPU_RCM_PIO	     = 3
			CFG_NIOS_CPU_WDTENA_PIO	     = 4
			CFG_NIOS_CPU_WDTTRIG_PIO     = 5
			CFG_NIOS_CPU_LED_PIO	     = (not present)

UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
	UART1: fixed baudrate of 115200, fixed protocol 8N1,
	       without handshake RTS/CTS (IRQ18)

SPI:	SPI0: master capable, 1 slave selectable, 250kHz target clock,
	      2 usec targets delay between slave select and clock,
	      data is transferred MSB-first / LSB-last (IRQ25)

LAN:	SMsC LAN91C111 with:
	  - without offset
	  - data bus width 16 bit (on-board hard wired at 32 bit bus)
	  - !!! 32 bit bus access --> each address * 2 !!!

IDE:	(TODO)


===============================================================================
	M E M O R Y   M A P
===============================================================================

- - - - - - - - - - -  external extension - - - - - - - - - - - - - - - - - - -

  0x44000000 ---32-----------16|15------------0-
	       |	       |	       | \
	       :  (real size   :	       : |
  EXT3 (CS4)   :   and content :	       :  > CFG_NIOS_CPU_CS3_SIZE
	       :   unknown)    :	       : |   = 0x01000000
	       |	       |	       | /
  0x43000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_CS3_BASE
	       |	       |	       | \
	       :  (real size   :	       : |
  EXT2 (CS3)   :   and content :	       :  > CFG_NIOS_CPU_CS2_SIZE
	       :   unknown)    :	       : |   = 0x01000000
	       |	       |	       | /
  0x42000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_CS2_BASE
	       |	       |	       | \
	       :  (real size   :	       : |
  EXT1 (CS2)   :   and content :	       :  > CFG_NIOS_CPU_CS1_SIZE
	       :   unknown)    :	       : |   = 0x01000000
	       |	       |	       | /
  0x41000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_CS1_BASE
	       |	       |	       | \
	       :  (real size   :	       : |
  EXT0 (CS1)   :   and content :	       :  > CFG_NIOS_CPU_CS0_SIZE
	       :   unknown)    :	       : |   = 0x01000000
	       |	       |	       | /
  0x40000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_CS0_BASE
	       |			       |
	       :	      gap	       :
	       :			       :

- - - - - - - - - - -   external memory   - - - - - - - - - - - - - - - - - - -

	       :			       :
	       :	      gap	       :
	       |			       |
  0x03000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_STACK
	       |	       .	       | \
	       |	       .	       | |  (U-Boot run-time system)
	       |	       .	       | |
	       |	       .	       |  > CFG_MONITOR_LEN
	       |	       .	       | |   = 0x00040000
	       |	       .	       | |
	       |	       .	       | /
  0x02fc0000 --+32-----------16|15------------0+    TEXT_BASE
	       |	       .	       | \
	       |	       .	       |  > CFG_MALLOC_LEN (heap)
	       |	       .	       | /
	     --+32-----------16|15------------0+
	       |	       .	       | \
	       |	       .	       |  > CFG_GBL_DATA_SIZE (global)
	       |	       .	       | /
	     --+32-----------16|15------------0+    CFG_INIT_SP (u-boot stack)
	       |	       .	       | \ \
	       |	       .	       | | |
	       |	       .	       | |  > stack area
	       |	       .	       | | |
	       |	       .	       | | V
	       |	       .	       | |
	       |	       .	       | |
  SDRAM	       |	       .	       |  > CFG_NIOS_CPU_SDRAM_SIZE
	       |	       .	       | |   = 0x01000000
	       |	       .	       | |
  0x02000100   |- - - - - - - - - - - - - - - -+-|-
	       |	       .	       | | \
	       |	       .	       | | |
	       |	       .	       | |  > CFG_NIOS_CPU_VEC_SIZE
	       |	       .	       | | |   = 0x00000100
	       |			       | / /
  0x02000000   |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
  0x02000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SDRAM_BASE
	       |			       | \
	       :	      gap	       :  > (space for 2nd Flash)
	       |			       | /
  0x01800000 ---32-----------16|15------------0-
	       |  sector 127		       | \
    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
	       |	       :	       | |
  Flash	       |-   -	-   -  :  -   -	  -   -|  > CFG_NIOS_CPU_FLASH_SIZE
	       |  sector 1     :	       | |   = 0x00800000
    + 0x010000 |- - - - - - - - - - - - - - - -| |
	       |  sector 0 (size = 0x10000)    | /
  0x01000000 ---8-------------4|3-------------0-    CFG_NIOS_CPU_FLASH_BASE
	       |			       |
	       :	      gap	       :
	       :			       :

- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -

	       :			       :
	       :	      gap	       :
	       |			       |
  0x00010020 ---32-----------16|15------------0-
  	       |			       | \
	       |  register bank		       | |
	       |   size = (real_size << 1)     | |
	       |   real_size = 0x10	       | |
	       | +--------.---.---.---	       | |
	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
	       | |---------------------------+ | |
  LAN91C111    | | BANK	       | RESERVED    | |  > na_enet_size
	       | |- - - - - - -|- - - - - - -| | |   = 0x00000020
	       | | RPCR	       | MIR	     | | |
	       | |- - - - - - -|- - - - - - -| | |
	       | | COUNTER     | RCR	     | | |
	       | |- - - - - - -|- - - - - - -| | |
	       | | EPH STATUS  | TCR	     | | |
	       | +---------------------------+ | /
  0x00010000 ---32-----------16|15------------0-    CFG_NIOS_CPU_LAN0_BASE
	       |			       |
	       :	      gap	       :
	       :			       :

- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -

	       :			       :
	       :	      gap	       :
	       |			       |
  0x00001040 ---32-----------16|15------------0-
	       |	       |	       | \
	       :	       :	       : |
  IDE1 i/f     :	       :	       :  > 0x00000020
  [5]	       :	       :	       : |
	       |	       |	       | /
  0x00001020 ---32-----------16|15------------0-    CFG_NIOS_CPU_IDE1
	       |	       |	       | \
	       :	       :	       : |
  IDE0 i/f     :	       :	       :  > 0x00000020
  [5]	       :	       :	       : |
	       |	       |	       | /
  0x00001000 ---32-----------16|15------------0-    CFG_NIOS_CPU_IDE0
	       |			       |
	       :	      gap	       :
	       |			       |
  0x00000980 ---32-----------16|15------------0-
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO13        |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000970 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO13
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO12        |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000960 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO12
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO11        |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000950 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO11
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO10        |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000940 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO10
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO9         |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000930 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO9
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO8         |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000920 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO8
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO7         |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000910 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO7
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO6         |  interruptmask (1 bit)	 (rw)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000900 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO6
	       |			       |
	       :	      gap	       :
	       |			       |
  0x000008e0 ---32-----------16|15------------0-
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |  endofpacket (16 bit)	 (rw)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |  slaveselect (1 bit)	 (rw)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  SPI0	       |  		   (reserved)  | |
  [4]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
	       |  control (11 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (9 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (16 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (16 bit)	 (ro)  | /
  0x000008c0 ---32-----------16|15------------0-    CFG_NIOS_CPU_SPI0
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO5	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (wo)  | /
  0x000008b0 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO5
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO4	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (wo)  | /
  0x000008a0 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO4
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO3	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x00000890 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO3
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO2	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (4 bit)      (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (4 bit)		 (rw)  | /
  0x00000880 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO2
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO1	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (8 bit)      (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (8 bit)		 (rw)  | /
  0x00000870 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO1
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO0	       |		     (unused)  | |
  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (8 bit)      (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (8 bit)		 (rw)  | /
  0x00000860 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO0
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |  snaph (16 bit)	 (rw)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  TIMER0       |  snapl (16 bit)	 (rw)  | |
  [2]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
	       |  periodh (16 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  periodl (16 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  control (4 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  status (2 bit)	 (rw)  | /
  0x00000840 ---32-----------16|15------------0-    CFG_NIOS_CPU_TIMER0
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  UART1	       |		     (unused)  |  > 0x00000020
  [1]	+ 0x10 |- - - - - - - - - - - - - - - -| |
	       |  control (10 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (10 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (8 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (8 bit)	 (ro)  | /
  0x00000820 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART1
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  UART0	       |		     (unused)  |  > 0x00000020
  [1]	+ 0x10 |- - - - - - - - - - - - - - - -| |
	       |  control (10 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (10 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (8 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (8 bit)	 (ro)  | /
  0x00000800 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART0

- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -

  0x00000800 ---32-----------16|15------------0-
	       |	       :	       | \
	       |	       :	       | |
  GERMS	       |	       :	       |  > CFG_NIOS_CPU_ROM_SIZE
	       |	       :	       | |   = 0x00000800
	       |	       :	       | /
  0x00000000   |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
  0x00000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_ROM_BASE


===============================================================================
	F L A S H   M E M O R Y	  A L L O C A T I O N
===============================================================================

  0x01800000 ---8-------------4|3-------------0-
	       |	       :	       | \
	       |	       :	       | |
	       |	       :	       |  > 6 MByte ROM FS
	       |	       :	       | |
	       |	       :	       | /
  0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
	       |	       :	       | \
	       |	       :	       | |
	       |	       :	       |  > 1728 kByte ucLinux
	       |	       :	       | |
	       |	       :	       | /
  0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
	       |	       :	       | \
  0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
	       |	       :	       | |
	       |	       :	       |  > 320 kByte U-Boot
	       |	       :	       | |
	       |	       :	       | |
	       |	       :	       | /
  0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
  0x01000000 ---8-------------4|3-------------0-


===============================================================================
	R E F E R E N C E S
===============================================================================
[1]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
[2]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
[3]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
[4]	http://www.altera.com/literature/ds/ds_nios_spi.pdf
[5]	http://www.t13.org/index.html


===============================================================================
Stephan Linz <[email protected]>
Commit	Line	Data
aaf224ab WD	1
	2	TODO: specify IDE i/f
	3
	4
	5	===============================================================================
	6	C P U , M E M O R Y , I N / O U T C O M P O N E N T S
	7	===============================================================================
	8	see also [1]-[5]
	9
	10	CPU: "DNP_ESC1"
	11	32 bit NIOS for 50 MHz
	12	512 Byte for register file (30 levels)
	13	with out instruction cache
	14	with out data cache
	15	2 KByte On Chip ROM with GERMS boot monitor
	16	with out On Chip RAM
	17	MSTEP multiplier
	18	no Debug Core
	19	no On Chip Instrumentation (OCI)
	20
	21	U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
	22	CFG_NIOS_CPU_ICACHE = (not present)
	23	CFG_NIOS_CPU_DCACHE = (not present)
	24	CFG_NIOS_CPU_REG_NUMS = 512
	25	CFG_NIOS_CPU_MUL = 0
	26	CFG_NIOS_CPU_MSTEP = 1
	27	CFG_NIOS_CPU_DBG_CORE = 0
	28
	29	IRQ: Nr. \| used by
	30	------+--------------------------------------------------------
	31	16 \| TIMER0 \| CFG_NIOS_CPU_TIMER0_IRQ = 16
	32	17 \| UART0 \| CFG_NIOS_CPU_UART0_IRQ = 17
	33	18 \| UART1 \| CFG_NIOS_CPU_UART1_IRQ = 18
	34	20 \| LAN91C111 \| CFG_NIOS_CPU_LAN0_IRQ =
	35	\| PIO6 \| CFG_NIOS_CPU_PIO6_IRQ = 20
	36	25 \| SPI0 \| CFG_NIOS_CPU_SPI0_IRQ = 25
	37	31 \| PIO7 \| CFG_NIOS_CPU_PIO7_IRQ = 31
	38	32 \| PIO8 \| CFG_NIOS_CPU_PIO8_IRQ = 32
	39	33 \| PIO9 \| CFG_NIOS_CPU_PIO9_IRQ = 33
	40	34 \| PIO10 \| CFG_NIOS_CPU_PIO10_IRQ = 34
	41	35 \| PIO11 \| CFG_NIOS_CPU_PIO11_IRQ = 35
	42	36 \| PIO12 \| CFG_NIOS_CPU_PIO12_IRQ =
	43	\| IDE0 \| CFG_NIOS_CPU_IDE0_IRQ = 36
	44	37 \| PIO13 \| CFG_NIOS_CPU_PIO13_IRQ =
	45	\| IDE1 \| CFG_NIOS_CPU_IDE1_IRQ = 37
	46
	47	MEMORY: 8 MByte Flash
	48	16 MByte SDRAM
	49
	50	Timer: TIMER0: high priority programmable timer (IRQ16)
	51
	52	U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
	53	CFG_NIOS_CPU_USER_TIMER = (not present)
	54
	55	PIO: Nr. \| description
	56	------+--------------------------------------------------------
	57	PIO0 \| PORTA: 8 in/outputs for general purpose usage
	58	PIO1 \| PORTB: 8 in/outputs for general purpose usage
	59	PIO2 \| PORTC: 4 in/outputs for general purpose usage
	60	PIO3 \| RCM: 1 input for RCM_EN# jumper (Req.Conf.Mon.)
	61	PIO4 \| WDTENA: 1 output to enable the on-board watchdog
	62	PIO5 \| WDTTRIG: 1 output to trigger the on-board watchdog
	63	PIO6 \| LAN0INT: 1 input for LAN91C111 irq input (IRQ20)
	64	PIO7 \| INT1: 1 input for general purpose irq (IRQ31)
65	PIO8 \| INT2: 1 input for general purpose irq (IRQ32)
66	PIO9 \| INT3: 1 input for general purpose irq (IRQ33)
67	PIO10\| INT4: 1 input for general purpose irq (IRQ34)
68	PIO11\| INT5: 1 input for general purpose irq (IRQ35)
69	PIO12\| INT6: 1 input for general purpose irq (IRQ36)
70	\| IDE0INT: (same) for IDE0 irq input
71	PIO13\| INT7: 1 input for general purpose irq (IRQ37)
72	\| IDE1INT: (same) for IDE1 irq input
73
74	U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0
75	CFG_NIOS_CPU_PORTB_PIO = 1
76	CFG_NIOS_CPU_PORTC_PIO = 2
77	CFG_NIOS_CPU_RCM_PIO = 3
78	CFG_NIOS_CPU_WDTENA_PIO = 4
79	CFG_NIOS_CPU_WDTTRIG_PIO = 5
80	CFG_NIOS_CPU_LED_PIO = (not present)
81
82	UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
83	UART1: fixed baudrate of 115200, fixed protocol 8N1,
84	without handshake RTS/CTS (IRQ18)
85
86	SPI: SPI0: master capable, 1 slave selectable, 250kHz target clock,
87	2 usec targets delay between slave select and clock,
88	data is transferred MSB-first / LSB-last (IRQ25)
89
90	LAN: SMsC LAN91C111 with:
91	- without offset
92	- data bus width 16 bit (on-board hard wired at 32 bit bus)
93	- !!! 32 bit bus access --> each address * 2 !!!
94
95	IDE: (TODO)
96
97
98	===============================================================================
99	M E M O R Y M A P
100	===============================================================================
101
102	- - - - - - - - - - - external extension - - - - - - - - - - - - - - - - - - -
103
104	0x44000000 ---32-----------16\|15------------0-
105	\| \| \| \
106	: (real size : : \|
107	EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE
108	: unknown) : : \| = 0x01000000
109	\| \| \| /
110	0x43000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_CS3_BASE
111	\| \| \| \
112	: (real size : : \|
113	EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE
114	: unknown) : : \| = 0x01000000
115	\| \| \| /
116	0x42000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_CS2_BASE
117	\| \| \| \
118	: (real size : : \|
119	EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE
120	: unknown) : : \| = 0x01000000
121	\| \| \| /
122	0x41000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_CS1_BASE
123	\| \| \| \
124	: (real size : : \|
125	EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE
126	: unknown) : : \| = 0x01000000
127	\| \| \| /
128	0x40000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_CS0_BASE
129	\| \|
130	: gap :
131	: :
132
133	- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
134
135	: :
136	: gap :
137	\| \|
138	0x03000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_STACK
139	\| . \| \
140	\| . \| \| (U-Boot run-time system)
141	\| . \| \|
142	\| . \| > CFG_MONITOR_LEN
143	\| . \| \| = 0x00040000
144	\| . \| \|
145	\| . \| /
146	0x02fc0000 --+32-----------16\|15------------0+ TEXT_BASE
147	\| . \| \
148	\| . \| > CFG_MALLOC_LEN (heap)
149	\| . \| /
150	--+32-----------16\|15------------0+
151	\| . \| \
152	\| . \| > CFG_GBL_DATA_SIZE (global)
153	\| . \| /
154	--+32-----------16\|15------------0+ CFG_INIT_SP (u-boot stack)
155	\| . \| \ \
156	\| . \| \| \|
157	\| . \| \| > stack area
158	\| . \| \| \|
159	\| . \| \| V
160	\| . \| \|
161	\| . \| \|
162	SDRAM \| . \| > CFG_NIOS_CPU_SDRAM_SIZE
163	\| . \| \| = 0x01000000
164	\| . \| \|
165	0x02000100 \|- - - - - - - - - - - - - - - -+-\|-
166	\| . \| \| \
167	\| . \| \| \|
168	\| . \| \| > CFG_NIOS_CPU_VEC_SIZE
169	\| . \| \| \| = 0x00000100
170	\| \| / /
171	0x02000000 \|- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
172	0x02000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_SDRAM_BASE
173	\| \| \
174	: gap : > (space for 2nd Flash)
175	\| \| /
176	0x01800000 ---32-----------16\|15------------0-
177	\| sector 127 \| \
178	+ 0x7f0000 \|- - - - - - - - - - - - - - - -\| \|
179	\| : \| \|
180	Flash \|- - - - : - - - -\| > CFG_NIOS_CPU_FLASH_SIZE
181	\| sector 1 : \| \| = 0x00800000
182	+ 0x010000 \|- - - - - - - - - - - - - - - -\| \|
183	\| sector 0 (size = 0x10000) \| /
184	0x01000000 ---8-------------4\|3-------------0- CFG_NIOS_CPU_FLASH_BASE
185	\| \|
186	: gap :
187	: :
188
189	- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
190
191	: :
192	: gap :
193	\| \|
194	0x00010020 ---32-----------16\|15------------0-
195	\| \| \
196	\| register bank \| \|
197	\| size = (real_size << 1) \| \|
198	\| real_size = 0x10 \| \|
199	\| +--------.---.---.--- \| \|
200	\| \| bank 0 \ 1 \ 2 \ 3 \ \| \|
201	\| \|---------------------------+ \| \|
202	LAN91C111 \| \| BANK \| RESERVED \| \| > na_enet_size
203	\| \|- - - - - - -\|- - - - - - -\| \| \| = 0x00000020
204	\| \| RPCR \| MIR \| \| \|
205	\| \|- - - - - - -\|- - - - - - -\| \| \|
206	\| \| COUNTER \| RCR \| \| \|
207	\| \|- - - - - - -\|- - - - - - -\| \| \|
208	\| \| EPH STATUS \| TCR \| \| \|
209	\| +---------------------------+ \| /
210	0x00010000 ---32-----------16\|15------------0- CFG_NIOS_CPU_LAN0_BASE
211	\| \|
212	: gap :
213	: :
214
215	- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
216
217	: :
218	: gap :
219	\| \|
220	0x00001040 ---32-----------16\|15------------0-
221	\| \| \| \
222	: : : \|
223	IDE1 i/f : : : > 0x00000020
224	[5] : : : \|
225	\| \| \| /
226	0x00001020 ---32-----------16\|15------------0- CFG_NIOS_CPU_IDE1
227	\| \| \| \
228	: : : \|
229	IDE0 i/f : : : > 0x00000020
230	[5] : : : \|
231	\| \| \| /
232	0x00001000 ---32-----------16\|15------------0- CFG_NIOS_CPU_IDE0
233	\| \|
234	: gap :
235	\| \|
236	0x00000980 ---32-----------16\|15------------0-
237	\| edgecapture (1 bit) (rw) \| \
238	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
239	PIO13 \| interruptmask (1 bit) (rw) \| \|
240	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
241	\| (unused) \| \|
242	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
243	\| data (1 bit) (ro) \| /
244	0x00000970 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO13
245	\| edgecapture (1 bit) (rw) \| \
246	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
247	PIO12 \| interruptmask (1 bit) (rw) \| \|
248	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
249	\| (unused) \| \|
250	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
251	\| data (1 bit) (ro) \| /
252	0x00000960 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO12
253	\| edgecapture (1 bit) (rw) \| \
254	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
255	PIO11 \| interruptmask (1 bit) (rw) \| \|
256	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
257	\| (unused) \| \|
258	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
259	\| data (1 bit) (ro) \| /
260	0x00000950 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO11
261	\| edgecapture (1 bit) (rw) \| \
262	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
263	PIO10 \| interruptmask (1 bit) (rw) \| \|
264	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
265	\| (unused) \| \|
266	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
267	\| data (1 bit) (ro) \| /
268	0x00000940 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO10
269	\| edgecapture (1 bit) (rw) \| \
270	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
271	PIO9 \| interruptmask (1 bit) (rw) \| \|
272	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
273	\| (unused) \| \|
274	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
275	\| data (1 bit) (ro) \| /
276	0x00000930 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO9
277	\| edgecapture (1 bit) (rw) \| \
278	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
279	PIO8 \| interruptmask (1 bit) (rw) \| \|
280	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
281	\| (unused) \| \|
282	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
283	\| data (1 bit) (ro) \| /
284	0x00000920 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO8
285	\| edgecapture (1 bit) (rw) \| \
286	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
287	PIO7 \| interruptmask (1 bit) (rw) \| \|
288	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
289	\| (unused) \| \|
290	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
291	\| data (1 bit) (ro) \| /
292	0x00000910 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO7
293	\| edgecapture (1 bit) (rw) \| \
294	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
295	PIO6 \| interruptmask (1 bit) (rw) \| \|
296	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
297	\| (unused) \| \|
298	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
299	\| data (1 bit) (ro) \| /
300	0x00000900 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO6
301	\| \|
302	: gap :
303	\| \|
304	0x000008e0 ---32-----------16\|15------------0-
305	\| (unused) \| \
306	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
307	\| endofpacket (16 bit) (rw) \| \|
308	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
309	\| slaveselect (1 bit) (rw) \| \|
310	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
311	SPI0 \| (reserved) \| \|
312	[4] + 0x10 \|- - - - - - - - - - - - - - - -\| > 0x00000020
313	\| control (11 bit) (rw) \| \|
314	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
315	\| status (9 bit) (rw) \| \|
316	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
317	\| txdata (16 bit) (wo) \| \|
318	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
319	\| rxdata (16 bit) (ro) \| /
320	0x000008c0 ---32-----------16\|15------------0- CFG_NIOS_CPU_SPI0
321	\| (unused) \| \
322	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
323	PIO5 \| (unused) \| \|
324	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
325	\| (unused) \| \|
326	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
327	\| data (1 bit) (wo) \| /
328	0x000008b0 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO5
329	\| (unused) \| \
330	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
331	PIO4 \| (unused) \| \|
332	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
333	\| (unused) \| \|
334	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
335	\| data (1 bit) (wo) \| /
336	0x000008a0 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO4
337	\| (unused) \| \
338	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
339	PIO3 \| (unused) \| \|
340	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
341	\| (unused) \| \|
342	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
343	\| data (1 bit) (ro) \| /
344	0x00000890 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO3
345	\| (unused) \| \
346	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
347	PIO2 \| (unused) \| \|
348	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
349	\| direction (4 bit) (rw) \| \|
350	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
351	\| data (4 bit) (rw) \| /
352	0x00000880 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO2
353	\| (unused) \| \
354	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
355	PIO1 \| (unused) \| \|
356	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
357	\| direction (8 bit) (rw) \| \|
358	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
359	\| data (8 bit) (rw) \| /
360	0x00000870 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO1
361	\| (unused) \| \
362	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
363	PIO0 \| (unused) \| \|
364	[3] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
365	\| direction (8 bit) (rw) \| \|
366	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
367	\| data (8 bit) (rw) \| /
368	0x00000860 ---32-----------16\|15------------0- CFG_NIOS_CPU_PIO0
369	\| (unused) \| \
370	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
371	\| (unused) \| \|
372	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
373	\| snaph (16 bit) (rw) \| \|
374	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
375	TIMER0 \| snapl (16 bit) (rw) \| \|
376	[2] + 0x10 \|- - - - - - - - - - - - - - - -\| > 0x00000020
377	\| periodh (16 bit) (rw) \| \|
378	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
379	\| periodl (16 bit) (rw) \| \|
380	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
381	\| control (4 bit) (rw) \| \|
382	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
383	\| status (2 bit) (rw) \| /
384	0x00000840 ---32-----------16\|15------------0- CFG_NIOS_CPU_TIMER0
385	\| (unused) \| \
386	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
387	\| (unused) \| \|
388	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
389	\| (unused) \| \|
390	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
391	UART1 \| (unused) \| > 0x00000020
392	[1] + 0x10 \|- - - - - - - - - - - - - - - -\| \|
393	\| control (10 bit) (rw) \| \|
394	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
395	\| status (10 bit) (rw) \| \|
396	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
397	\| txdata (8 bit) (wo) \| \|
398	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
399	\| rxdata (8 bit) (ro) \| /
400	0x00000820 ---32-----------16\|15------------0- CFG_NIOS_CPU_UART1
401	\| (unused) \| \
402	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
403	\| (unused) \| \|
404	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
405	\| (unused) \| \|
406	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
407	UART0 \| (unused) \| > 0x00000020
408	[1] + 0x10 \|- - - - - - - - - - - - - - - -\| \|
409	\| control (10 bit) (rw) \| \|
410	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
411	\| status (10 bit) (rw) \| \|
412	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
413	\| txdata (8 bit) (wo) \| \|
414	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
415	\| rxdata (8 bit) (ro) \| /
416	0x00000800 ---32-----------16\|15------------0- CFG_NIOS_CPU_UART0
417
418	- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
419
420	0x00000800 ---32-----------16\|15------------0-
421	\| : \| \
422	\| : \| \|
423	GERMS \| : \| > CFG_NIOS_CPU_ROM_SIZE
424	\| : \| \| = 0x00000800
425	\| : \| /
426	0x00000000 \|- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
427	0x00000000 ---32-----------16\|15------------0- CFG_NIOS_CPU_ROM_BASE
428
429
430	===============================================================================
431	F L A S H M E M O R Y A L L O C A T I O N
432	===============================================================================
433
434	0x01800000 ---8-------------4\|3-------------0-
435	\| : \| \
436	\| : \| \|
437	\| : \| > 6 MByte ROM FS
438	\| : \| \|
439	\| : \| /
440	0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
441	\| : \| \
442	\| : \| \|
443	\| : \| > 1728 kByte ucLinux
444	\| : \| \|
445	\| : \| /
446	0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
447	\| : \| \
448	0x01040000 --+- - - - - - - -:- - - - - - - -+-\|- u-boot environment
449	\| : \| \|
450	\| : \| > 320 kByte U-Boot
451	\| : \| \|
452	\| : \| \|
453	\| : \| /
454	0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
455	0x01000000 ---8-------------4\|3-------------0-
456
457
458	===============================================================================
459	R E F E R E N C E S
460	===============================================================================
461	[1] http://www.altera.com/literature/ds/ds_nios_uart.pdf
462	[2] http://www.altera.com/literature/ds/ds_nios_timer.pdf
463	[3] http://www.altera.com/literature/ds/ds_nios_pio.pdf
464	[4] http://www.altera.com/literature/ds/ds_nios_spi.pdf
465	[5] http://www.t13.org/index.html
466
467
468	===============================================================================
469	Stephan Linz <[email protected]>