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MCC200 board: support console on any one of the Quad UART ports.
[J-u-boot.git] / cpu / mpc8xx / fec.c
CommitLineData
c609719b
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <commproc.h>
27#include <net.h>
28#include <command.h>
29
d87080b7
WD		 30DECLARE_GLOBAL_DATA_PTR;
31
c609719b
WD		 32#undef ET_DEBUG
33
a6ab4bf9
WD		 34#if (CONFIG_COMMANDS & CFG_CMD_NET) && \
35 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
c609719b 36
a6ab4bf9
WD		 37/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
38#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
39#define CONFIG_ETHER_ON_FEC1 1
40#endif
41
42/* define WANT_MII when MII support is required */
43#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
44#define WANT_MII
45#else
46#undef WANT_MII
47#endif
48
49#if defined(WANT_MII)
c609719b 50#include <miiphy.h>
63ff004c
MB		 51
52#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
53#error "CONFIG_MII has to be defined!"
54#endif
55
c609719b
WD		 56#endif
57
a6ab4bf9
WD		 58#if defined(CONFIG_RMII) && !defined(WANT_MII)
59#error RMII support is unusable without a working PHY.
60#endif
61
62#ifdef CFG_DISCOVER_PHY
63static int mii_discover_phy(struct eth_device *dev);
64#endif
65
63ff004c
MB		 66int fec8xx_miiphy_read(char *devname, unsigned char addr,
67 unsigned char reg, unsigned short *value);
68int fec8xx_miiphy_write(char *devname, unsigned char addr,
69 unsigned char reg, unsigned short value);
70
a6ab4bf9
WD		 71static struct ether_fcc_info_s
72{
73 int ether_index;
74 int fecp_offset;
a6ab4bf9
WD		 75 int phy_addr;
76 int actual_phy_addr;
c26e454d 77 int initialized;
a6ab4bf9
WD		 78}
79 ether_fcc_info[] = {
80#if defined(CONFIG_ETHER_ON_FEC1)
81 {
82 0,
83 offsetof(immap_t, im_cpm.cp_fec1),
a6ab4bf9
WD		 84#if defined(CONFIG_FEC1_PHY)
85 CONFIG_FEC1_PHY,
86#else
87 -1, /* discover */
88#endif
89 -1,
c26e454d 90 0,
a6ab4bf9
WD		 91
92 },
93#endif
94#if defined(CONFIG_ETHER_ON_FEC2)
95 {
96 1,
97 offsetof(immap_t, im_cpm.cp_fec2),
a6ab4bf9
WD		 98#if defined(CONFIG_FEC2_PHY)
99 CONFIG_FEC2_PHY,
100#else
101 -1,
102#endif
103 -1,
c26e454d 104 0,
a6ab4bf9
WD		 105 },
106#endif
107};
108
c609719b
WD		 109/* Ethernet Transmit and Receive Buffers */
110#define DBUF_LENGTH 1520
111
112#define TX_BUF_CNT 2
113
114#define TOUT_LOOP 100
115
116#define PKT_MAXBUF_SIZE 1518
117#define PKT_MINBUF_SIZE 64
118#define PKT_MAXBLR_SIZE 1520
119
a6ab4bf9
WD		 120#ifdef __GNUC__
121static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
122#else
123#error txbuf must be aligned.
124#endif
c609719b
WD		 125
126static uint rxIdx; /* index of the current RX buffer */
127static uint txIdx; /* index of the current TX buffer */
128
129/*
130 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
131 * immr->udata_bd address on Dual-Port RAM
132 * Provide for Double Buffering
133 */
134
135typedef volatile struct CommonBufferDescriptor {
136 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
137 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
138} RTXBD;
139
140static RTXBD *rtx = NULL;
141
142static int fec_send(struct eth_device* dev, volatile void *packet, int length);
143static int fec_recv(struct eth_device* dev);
144static int fec_init(struct eth_device* dev, bd_t * bd);
145static void fec_halt(struct eth_device* dev);
146
147int fec_initialize(bd_t *bis)
148{
149 struct eth_device* dev;
a6ab4bf9
WD		 150 struct ether_fcc_info_s *efis;
151 int i;
c609719b 152
a6ab4bf9 153 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
c609719b 154
a6ab4bf9
WD		 155 dev = malloc(sizeof(*dev));
156 if (dev == NULL)
157 hang();
158
159 memset(dev, 0, sizeof(*dev));
160
161 /* for FEC1 make sure that the name of the interface is the same
162 as the old one for compatibility reasons */
163 if (i == 0) {
164 sprintf (dev->name, "FEC ETHERNET");
165 } else {
166 sprintf (dev->name, "FEC%d ETHERNET",
167 ether_fcc_info[i].ether_index + 1);
168 }
c609719b 169
a6ab4bf9 170 efis = &ether_fcc_info[i];
c609719b 171
a6ab4bf9
WD		 172 /*
173 * reset actual phy addr
174 */
175 efis->actual_phy_addr = -1;
176
177 dev->priv = efis;
178 dev->init = fec_init;
179 dev->halt = fec_halt;
180 dev->send = fec_send;
181 dev->recv = fec_recv;
182
183 eth_register(dev);
63ff004c
MB		 184
185#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
186 miiphy_register(dev->name,
187 fec8xx_miiphy_read, fec8xx_miiphy_write);
188#endif
a6ab4bf9 189 }
c609719b
WD		 190 return 1;
191}
192
193static int fec_send(struct eth_device* dev, volatile void *packet, int length)
194{
195 int j, rc;
a6ab4bf9
WD		 196 struct ether_fcc_info_s *efis = dev->priv;
197 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
c609719b
WD		 198
199 /* section 16.9.23.3
200 * Wait for ready
201 */
202 j = 0;
203 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
204 udelay(1);
205 j++;
206 }
207 if (j>=TOUT_LOOP) {
208 printf("TX not ready\n");
209 }
210
211 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
212 rtx->txbd[txIdx].cbd_datlen = length;
213 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
214 __asm__ ("eieio");
215
216 /* Activate transmit Buffer Descriptor polling */
217 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
218
219 j = 0;
220 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
221#if defined(CONFIG_ICU862)
222 udelay(10);
223#else
224 udelay(1);
225#endif
226 j++;
227 }
228 if (j>=TOUT_LOOP) {
229 printf("TX timeout\n");
230 }
231#ifdef ET_DEBUG
232 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
233 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
234 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
235#endif
236 /* return only status bits */;
237 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
238
239 txIdx = (txIdx + 1) % TX_BUF_CNT;
240
241 return rc;
242}
243
a6ab4bf9 244static int fec_recv (struct eth_device *dev)
c609719b 245{
a6ab4bf9
WD		 246 struct ether_fcc_info_s *efis = dev->priv;
247 volatile fec_t *fecp =
248 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
c609719b 249 int length;
c609719b 250
a6ab4bf9
WD		 251 for (;;) {
252 /* section 16.9.23.2 */
253 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
254 length = -1;
255 break; /* nothing received - leave for() loop */
256 }
c609719b 257
a6ab4bf9 258 length = rtx->rxbd[rxIdx].cbd_datlen;
c609719b 259
a6ab4bf9 260 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
c609719b 261#ifdef ET_DEBUG
a6ab4bf9
WD		 262 printf ("%s[%d] err: %x\n",
263 __FUNCTION__, __LINE__,
264 rtx->rxbd[rxIdx].cbd_sc);
c609719b 265#endif
a6ab4bf9
WD		 266 } else {
267 volatile uchar *rx = NetRxPackets[rxIdx];
c609719b 268
a6ab4bf9 269 length -= 4;
c609719b 270
a6ab4bf9
WD		 271#if (CONFIG_COMMANDS & CFG_CMD_CDP)
272 if ((rx[0] & 1) != 0
273 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
274 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
275 rx = NULL;
276#endif
277 /*
278 * Pass the packet up to the protocol layers.
279 */
280 if (rx != NULL)
281 NetReceive (rx, length);
282 }
c609719b 283
a6ab4bf9
WD		 284 /* Give the buffer back to the FEC. */
285 rtx->rxbd[rxIdx].cbd_datlen = 0;
286
287 /* wrap around buffer index when necessary */
288 if ((rxIdx + 1) >= PKTBUFSRX) {
289 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
290 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
291 rxIdx = 0;
292 } else {
293 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
294 rxIdx++;
295 }
296
297 __asm__ ("eieio");
c609719b 298
a6ab4bf9
WD		 299 /* Try to fill Buffer Descriptors */
300 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
301 }
c609719b 302
a6ab4bf9 303 return length;
c609719b
WD		 304}
305
306/**************************************************************
307 *
308 * FEC Ethernet Initialization Routine
309 *
310 *************************************************************/
311
312#define FEC_ECNTRL_PINMUX 0x00000004
313#define FEC_ECNTRL_ETHER_EN 0x00000002
314#define FEC_ECNTRL_RESET 0x00000001
315
316#define FEC_RCNTRL_BC_REJ 0x00000010
317#define FEC_RCNTRL_PROM 0x00000008
318#define FEC_RCNTRL_MII_MODE 0x00000004
319#define FEC_RCNTRL_DRT 0x00000002
320#define FEC_RCNTRL_LOOP 0x00000001
321
322#define FEC_TCNTRL_FDEN 0x00000004
323#define FEC_TCNTRL_HBC 0x00000002
324#define FEC_TCNTRL_GTS 0x00000001
325
326#define FEC_RESET_DELAY 50
327
a6ab4bf9
WD		 328#if defined(CONFIG_RMII)
329
330static inline void fec_10Mbps(struct eth_device *dev)
c609719b 331{
a6ab4bf9
WD		 332 struct ether_fcc_info_s *efis = dev->priv;
333 int fecidx = efis->ether_index;
334 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
c609719b 335
a6ab4bf9
WD		 336 if ((unsigned int)fecidx >= 2)
337 hang();
338
339 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
340}
341
342static inline void fec_100Mbps(struct eth_device *dev)
343{
344 struct ether_fcc_info_s *efis = dev->priv;
345 int fecidx = efis->ether_index;
346 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
347
348 if ((unsigned int)fecidx >= 2)
349 hang();
350
351 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
352}
353
354#endif
355
356static inline void fec_full_duplex(struct eth_device *dev)
357{
358 struct ether_fcc_info_s *efis = dev->priv;
359 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
360
361 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
362 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
363}
364
365static inline void fec_half_duplex(struct eth_device *dev)
366{
367 struct ether_fcc_info_s *efis = dev->priv;
368 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
369
370 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
371 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
372}
373
374static void fec_pin_init(int fecidx)
375{
a6ab4bf9 376 bd_t *bd = gd->bd;
c609719b 377 volatile immap_t *immr = (immap_t *) CFG_IMMR;
a6ab4bf9 378 volatile fec_t *fecp;
c609719b 379
a6ab4bf9
WD		 380 /*
381 * only two FECs please
c609719b 382 */
a6ab4bf9
WD		 383 if ((unsigned int)fecidx >= 2)
384 hang();
385
386 if (fecidx == 0)
387 fecp = &immr->im_cpm.cp_fec1;
388 else
389 fecp = &immr->im_cpm.cp_fec2;
390
391 /*
392 * Set MII speed to 2.5 MHz or slightly below.
393 * * According to the MPC860T (Rev. D) Fast ethernet controller user
394 * * manual (6.2.14),
395 * * the MII management interface clock must be less than or equal
396 * * to 2.5 MHz.
397 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
398 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
399 */
400 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
401
79fa88f3 402#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
c26e454d
WD		 403 /* our PHYs are the limit at 2.5 MHz */
404 fecp->fec_mii_speed <<= 1;
405#endif
406
1114257c 407#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
a6ab4bf9
WD		 408 /* use MDC for MII */
409 immr->im_ioport.iop_pdpar |= 0x0080;
410 immr->im_ioport.iop_pddir &= ~0x0080;
411#endif
412
413 if (fecidx == 0) {
414#if defined(CONFIG_ETHER_ON_FEC1)
415
1114257c 416#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
a6ab4bf9
WD		 417
418#if !defined(CONFIG_RMII)
419
420 immr->im_ioport.iop_papar |= 0xf830;
421 immr->im_ioport.iop_padir |= 0x0830;
422 immr->im_ioport.iop_padir &= ~0xf000;
423
424 immr->im_cpm.cp_pbpar |= 0x00001001;
425 immr->im_cpm.cp_pbdir &= ~0x00001001;
426
427 immr->im_ioport.iop_pcpar |= 0x000c;
428 immr->im_ioport.iop_pcdir &= ~0x000c;
429
430 immr->im_cpm.cp_pepar |= 0x00000003;
431 immr->im_cpm.cp_pedir |= 0x00000003;
432 immr->im_cpm.cp_peso &= ~0x00000003;
433
434 immr->im_cpm.cp_cptr &= ~0x00000100;
435
436#else
437
438#if !defined(CONFIG_FEC1_PHY_NORXERR)
439 immr->im_ioport.iop_papar |= 0x1000;
440 immr->im_ioport.iop_padir &= ~0x1000;
441#endif
442 immr->im_ioport.iop_papar |= 0xe810;
443 immr->im_ioport.iop_padir |= 0x0810;
444 immr->im_ioport.iop_padir &= ~0xe000;
445
446 immr->im_cpm.cp_pbpar |= 0x00000001;
447 immr->im_cpm.cp_pbdir &= ~0x00000001;
448
449 immr->im_cpm.cp_cptr |= 0x00000100;
450 immr->im_cpm.cp_cptr &= ~0x00000050;
451
452#endif /* !CONFIG_RMII */
453
454#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
455 /*
456 * Configure all of port D for MII.
457 */
458 immr->im_ioport.iop_pdpar = 0x1fff;
459
460 /*
461 * Bits moved from Rev. D onward
462 */
463 if ((get_immr(0) & 0xffff) < 0x0501)
464 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
465 else
466 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
467#else
468 /*
469 * Configure port A for MII.
470 */
471
472#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
473
474 /*
475 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
476 * * of CPU, so for this board we need to configure Utopia and
477 * * enable PD8 to MII-MDC function
478 */
479 immr->im_ioport.iop_pdpar |= 0x4080;
480#endif
481
482 /*
483 * Has Utopia been configured?
484 */
485 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
486 /*
487 * YES - Use MUXED mode for UTOPIA bus.
488 * This frees Port A for use by MII (see 862UM table 41-6).
489 */
490 immr->im_ioport.utmode &= ~0x80;
491 } else {
492 /*
493 * NO - set SPLIT mode for UTOPIA bus.
494 *
495 * This doesn't really effect UTOPIA (which isn't
496 * enabled anyway) but just tells the 862
497 * to use port A for MII (see 862UM table 41-6).
498 */
499 immr->im_ioport.utmode |= 0x80;
500 }
501#endif /* !defined(CONFIG_ICU862) */
502
503#endif /* CONFIG_ETHER_ON_FEC1 */
504 } else if (fecidx == 1) {
505
506#if defined(CONFIG_ETHER_ON_FEC2)
507
1114257c 508#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
a6ab4bf9
WD		 509
510#if !defined(CONFIG_RMII)
511
512#warning this configuration is not tested; please report if it works
513 immr->im_cpm.cp_pepar |= 0x0003fffc;
514 immr->im_cpm.cp_pedir |= 0x0003fffc;
515 immr->im_cpm.cp_peso &= ~0x000087fc;
516 immr->im_cpm.cp_peso |= 0x00037800;
517
518 immr->im_cpm.cp_cptr &= ~0x00000080;
519#else
520
521#if !defined(CONFIG_FEC2_PHY_NORXERR)
522 immr->im_cpm.cp_pepar |= 0x00000010;
523 immr->im_cpm.cp_pedir |= 0x00000010;
524 immr->im_cpm.cp_peso &= ~0x00000010;
525#endif
526 immr->im_cpm.cp_pepar |= 0x00039620;
527 immr->im_cpm.cp_pedir |= 0x00039620;
528 immr->im_cpm.cp_peso |= 0x00031000;
529 immr->im_cpm.cp_peso &= ~0x00008620;
530
531 immr->im_cpm.cp_cptr |= 0x00000080;
532 immr->im_cpm.cp_cptr &= ~0x00000028;
533#endif /* CONFIG_RMII */
534
1114257c 535#endif /* CONFIG_MPC885_FAMILY */
a6ab4bf9
WD		 536
537#endif /* CONFIG_ETHER_ON_FEC2 */
538
c609719b 539 }
a6ab4bf9
WD		 540}
541
542static int fec_init (struct eth_device *dev, bd_t * bd)
543{
544 struct ether_fcc_info_s *efis = dev->priv;
545 volatile immap_t *immr = (immap_t *) CFG_IMMR;
546 volatile fec_t *fecp =
547 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
548 int i;
549
550 if (efis->ether_index == 0) {
551#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
1114257c 552#if defined(CONFIG_MPC885ADS)
a6ab4bf9
WD		 553 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
554#else
555 /* configure FADS for fast (FEC) ethernet, half-duplex */
556 /* The LXT970 needs about 50ms to recover from reset, so
557 * wait for it by discovering the PHY before leaving eth_init().
558 */
559 {
560 volatile uint *bcsr4 = (volatile uint *) BCSR4;
561
562 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
563 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
564 BCSR4_FETHRST);
565
566 /* reset the LXT970 PHY */
567 *bcsr4 &= ~BCSR4_FETHRST;
568 udelay (10);
569 *bcsr4 |= BCSR4_FETHRST;
570 udelay (10);
571 }
1114257c 572#endif /* CONFIG_MPC885ADS */
180d3f74 573#endif /* CONFIG_FADS */
a6ab4bf9
WD		 574 }
575
c609719b
WD		 576 /* Whack a reset.
577 * A delay is required between a reset of the FEC block and
578 * initialization of other FEC registers because the reset takes
579 * some time to complete. If you don't delay, subsequent writes
580 * to FEC registers might get killed by the reset routine which is
581 * still in progress.
582 */
583 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
584 for (i = 0;
585 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
586 ++i) {
587 udelay (1);
588 }
589 if (i == FEC_RESET_DELAY) {
590 printf ("FEC_RESET_DELAY timeout\n");
591 return 0;
592 }
593
594 /* We use strictly polling mode only
595 */
596 fecp->fec_imask = 0;
597
598 /* Clear any pending interrupt
599 */
600 fecp->fec_ievent = 0xffc0;
601
602 /* No need to set the IVEC register */
603
604 /* Set station address
605 */
606#define ea eth_get_dev()->enetaddr
a6ab4bf9
WD		 607 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
608 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
c609719b
WD		 609#undef ea
610
a6ab4bf9
WD		 611#if (CONFIG_COMMANDS & CFG_CMD_CDP)
612 /*
613 * Turn on multicast address hash table
614 */
615 fecp->fec_hash_table_high = 0xffffffff;
616 fecp->fec_hash_table_low = 0xffffffff;
617#else
c609719b
WD		 618 /* Clear multicast address hash table
619 */
620 fecp->fec_hash_table_high = 0;
a6ab4bf9
WD		 621 fecp->fec_hash_table_low = 0;
622#endif
c609719b
WD		 623
624 /* Set maximum receive buffer size.
625 */
626 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
627
628 /* Set maximum frame length
629 */
630 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
631
632 /*
633 * Setup Buffers and Buffer Desriptors
634 */
635 rxIdx = 0;
636 txIdx = 0;
637
638 if (!rtx) {
639#ifdef CFG_ALLOC_DPRAM
a6ab4bf9
WD		 640 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
641 dpram_alloc_align (sizeof (RTXBD), 8));
c609719b 642#else
a6ab4bf9 643 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
c609719b
WD		 644#endif
645 }
646 /*
647 * Setup Receiver Buffer Descriptors (13.14.24.18)
648 * Settings:
649 * Empty, Wrap
650 */
651 for (i = 0; i < PKTBUFSRX; i++) {
a6ab4bf9
WD		 652 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
653 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
c609719b
WD		 654 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
655 }
656 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
657
658 /*
659 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
660 * Settings:
661 * Last, Tx CRC
662 */
663 for (i = 0; i < TX_BUF_CNT; i++) {
a6ab4bf9
WD		 664 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
665 rtx->txbd[i].cbd_datlen = 0; /* Reset */
c609719b
WD		 666 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
667 }
668 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
669
670 /* Set receive and transmit descriptor base
671 */
672 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
673 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
674
675 /* Enable MII mode
676 */
a6ab4bf9 677#if 0 /* Full duplex mode */
c609719b
WD		 678 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
679 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
a6ab4bf9 680#else /* Half duplex mode */
c609719b
WD		 681 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
682 fecp->fec_x_cntrl = 0;
683#endif
684
685 /* Enable big endian and don't care about SDMA FC.
686 */
687 fecp->fec_fun_code = 0x78000000;
688
a6ab4bf9
WD		 689 /*
690 * Setup the pin configuration of the FEC
c609719b 691 */
a6ab4bf9 692 fec_pin_init (efis->ether_index);
c609719b 693
a6ab4bf9
WD		 694 rxIdx = 0;
695 txIdx = 0;
c609719b 696
a6ab4bf9
WD		 697 /*
698 * Now enable the transmit and receive processing
699 */
700 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
c609719b 701
a6ab4bf9
WD		 702 if (efis->phy_addr == -1) {
703#ifdef CFG_DISCOVER_PHY
c609719b 704 /*
a6ab4bf9 705 * wait for the PHY to wake up after reset
c609719b 706 */
a6ab4bf9 707 efis->actual_phy_addr = mii_discover_phy (dev);
62b4ac98 708
a6ab4bf9
WD		 709 if (efis->actual_phy_addr == -1) {
710 printf ("Unable to discover phy!\n");
711 return 0;
712 }
62b4ac98
WD		 713#else
714 efis->actual_phy_addr = -1;
715#endif
c609719b 716 } else {
a6ab4bf9 717 efis->actual_phy_addr = efis->phy_addr;
c609719b 718 }
a6ab4bf9 719#if defined(CONFIG_MII) && defined(CONFIG_RMII)
c26e454d
WD		 720
721 /* the MII interface is connected to FEC1
6e592385
WD		 722 * so for the miiphy_xxx function to work we must
723 * call mii_init since fec_halt messes the thing up
724 */
c26e454d
WD		 725 if (efis->ether_index != 0)
726 mii_init();
727
a6ab4bf9
WD		 728 /*
729 * adapt the RMII speed to the speed of the phy
c609719b 730 */
63ff004c 731 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
a6ab4bf9
WD		 732 fec_100Mbps (dev);
733 } else {
734 fec_10Mbps (dev);
735 }
736#endif
c609719b 737
a6ab4bf9
WD		 738#if defined(CONFIG_MII)
739 /*
740 * adapt to the half/full speed settings
c609719b 741 */
63ff004c 742 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
a6ab4bf9
WD		 743 fec_full_duplex (dev);
744 } else {
745 fec_half_duplex (dev);
746 }
c609719b
WD		 747#endif
748
749 /* And last, try to fill Rx Buffer Descriptors */
a6ab4bf9 750 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
c609719b 751
c26e454d
WD		 752 efis->initialized = 1;
753
c609719b
WD		 754 return 1;
755}
756
757
c609719b
WD		 758static void fec_halt(struct eth_device* dev)
759{
c26e454d
WD		 760 struct ether_fcc_info_s *efis = dev->priv;
761 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
762 int i;
c609719b 763
c26e454d
WD		 764 /* avoid halt if initialized; mii gets stuck otherwise */
765 if (!efis->initialized)
766 return;
767
768 /* Whack a reset.
769 * A delay is required between a reset of the FEC block and
770 * initialization of other FEC registers because the reset takes
771 * some time to complete. If you don't delay, subsequent writes
772 * to FEC registers might get killed by the reset routine which is
773 * still in progress.
774 */
775
776 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
777 for (i = 0;
778 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
779 ++i) {
780 udelay (1);
781 }
782 if (i == FEC_RESET_DELAY) {
783 printf ("FEC_RESET_DELAY timeout\n");
784 return;
785 }
786
787 efis->initialized = 0;
c609719b 788}
c609719b 789
a6ab4bf9 790#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
c609719b
WD		 791
792/* Make MII read/write commands for the FEC.
793*/
794
795#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
796 (REG & 0x1f) << 18))
797
798#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
799 (REG & 0x1f) << 18) | \
800 (VAL & 0xffff))
801
802/* Interrupt events/masks.
803*/
804#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
805#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
806#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
807#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
808#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
809#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
810#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
811#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
812#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
813#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
814
815/* PHY identification
816 */
817#define PHY_ID_LXT970 0x78100000 /* LXT970 */
818#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
819#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
820#define PHY_ID_QS6612 0x01814400 /* QS6612 */
821#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
822#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
823#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
180d3f74 824#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
c609719b
WD		 825
826/* send command to phy using mii, wait for result */
827static uint
828mii_send(uint mii_cmd)
829{
830 uint mii_reply;
831 volatile fec_t *ep;
c26e454d 832 int cnt;
c609719b
WD		 833
834 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
835
836 ep->fec_mii_data = mii_cmd; /* command to phy */
837
838 /* wait for mii complete */
c26e454d
WD		 839 cnt = 0;
840 while (!(ep->fec_ievent & FEC_ENET_MII)) {
841 if (++cnt > 1000) {
842 printf("mii_send STUCK!\n");
843 break;
844 }
845 }
c609719b
WD		 846 mii_reply = ep->fec_mii_data; /* result from phy */
847 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
848#if 0
849 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
850 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
851#endif
852 return (mii_reply & 0xffff); /* data read from phy */
853}
854#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
855
856#if defined(CFG_DISCOVER_PHY)
a6ab4bf9 857static int mii_discover_phy(struct eth_device *dev)
c609719b
WD		 858{
859#define MAX_PHY_PASSES 11
860 uint phyno;
861 int pass;
a6ab4bf9
WD		 862 uint phytype;
863 int phyaddr;
c609719b
WD		 864
865 phyaddr = -1; /* didn't find a PHY yet */
866 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
867 if (pass > 1) {
868 /* PHY may need more time to recover from reset.
869 * The LXT970 needs 50ms typical, no maximum is
870 * specified, so wait 10ms before try again.
871 * With 11 passes this gives it 100ms to wake up.
872 */
873 udelay(10000); /* wait 10ms */
874 }
875 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
876 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
877#ifdef ET_DEBUG
878 printf("PHY type 0x%x pass %d type ", phytype, pass);
879#endif
880 if (phytype != 0xffff) {
881 phyaddr = phyno;
882 phytype <<= 16;
883 phytype |= mii_send(mk_mii_read(phyno,
884 PHY_PHYIDR2));
885
886#ifdef ET_DEBUG
887 printf("PHY @ 0x%x pass %d type ",phyno,pass);
888 switch (phytype & 0xfffffff0) {
889 case PHY_ID_LXT970:
890 printf("LXT970\n");
891 break;
892 case PHY_ID_LXT971:
893 printf("LXT971\n");
894 break;
895 case PHY_ID_82555:
896 printf("82555\n");
897 break;
898 case PHY_ID_QS6612:
899 printf("QS6612\n");
900 break;
901 case PHY_ID_AMD79C784:
902 printf("AMD79C784\n");
903 break;
904 case PHY_ID_LSI80225B:
905 printf("LSI L80225/B\n");
906 break;
180d3f74
WD		 907 case PHY_ID_DM9161:
908 printf("Davicom DM9161\n");
909 break;
c609719b
WD		 910 default:
911 printf("0x%08x\n", phytype);
912 break;
913 }
914#endif
915 }
916 }
917 }
918 if (phyaddr < 0) {
919 printf("No PHY device found.\n");
920 }
a6ab4bf9 921 return phyaddr;
c609719b
WD		 922}
923#endif /* CFG_DISCOVER_PHY */
924
a6ab4bf9 925#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
c609719b 926
c609719b
WD		 927/****************************************************************************
928 * mii_init -- Initialize the MII for MII command without ethernet
929 * This function is a subset of eth_init
930 ****************************************************************************
931 */
932void mii_init (void)
933{
c609719b
WD		 934 volatile immap_t *immr = (immap_t *) CFG_IMMR;
935 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
a6ab4bf9 936 int i, j;
c609719b 937
a6ab4bf9
WD		 938 for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
939
c609719b
WD		 940 /* Whack a reset.
941 * A delay is required between a reset of the FEC block and
942 * initialization of other FEC registers because the reset takes
943 * some time to complete. If you don't delay, subsequent writes
944 * to FEC registers might get killed by the reset routine which is
945 * still in progress.
946 */
947
948 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
949 for (i = 0;
950 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
951 ++i) {
952 udelay (1);
953 }
954 if (i == FEC_RESET_DELAY) {
955 printf ("FEC_RESET_DELAY timeout\n");
956 return;
957 }
958
959 /* We use strictly polling mode only
960 */
961 fecp->fec_imask = 0;
962
963 /* Clear any pending interrupt
964 */
965 fecp->fec_ievent = 0xffc0;
966
1114257c 967 /* Setup the pin configuration of the FEC(s)
c609719b 968 */
a6ab4bf9 969 fec_pin_init(ether_fcc_info[i].ether_index);
c609719b 970
c609719b
WD		 971 /* Now enable the transmit and receive processing
972 */
973 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
a6ab4bf9 974 }
c609719b 975}
a6ab4bf9 976
c609719b
WD		 977/*****************************************************************************
978 * Read and write a MII PHY register, routines used by MII Utilities
979 *
980 * FIXME: These routines are expected to return 0 on success, but mii_send
981 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
982 * no PHY connected...
983 * For now always return 0.
984 * FIXME: These routines only work after calling eth_init() at least once!
985 * Otherwise they hang in mii_send() !!! Sorry!
986 *****************************************************************************/
987
63ff004c
MB		 988int fec8xx_miiphy_read(char *devname, unsigned char addr,
989 unsigned char reg, unsigned short *value)
c609719b
WD		 990{
991 short rdreg; /* register working value */
992
993#ifdef MII_DEBUG
994 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
995#endif
996 rdreg = mii_send(mk_mii_read(addr, reg));
997
998 *value = rdreg;
c609719b
WD		 999#ifdef MII_DEBUG
1000 printf ("0x%04x\n", *value);
1001#endif
c609719b
WD		 1002 return 0;
1003}
1004
63ff004c
MB		 1005int fec8xx_miiphy_write(char *devname, unsigned char addr,
1006 unsigned char reg, unsigned short value)
c609719b
WD		 1007{
1008 short rdreg; /* register working value */
c609719b
WD		 1009#ifdef MII_DEBUG
1010 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
1011#endif
c609719b
WD		 1012 rdreg = mii_send(mk_mii_write(addr, reg, value));
1013
1014#ifdef MII_DEBUG
1015 printf ("0x%04x\n", value);
1016#endif
c609719b
WD		 1017 return 0;
1018}
1019#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
1020
1021#endif /* CFG_CMD_NET, FEC_ENET */
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