[J-u-boot.git] / drivers / mtd / nand / raw / Kconfig


menuconfig MTD_RAW_NAND
	bool "Raw NAND Device Support"
if MTD_RAW_NAND

config SYS_NAND_SELF_INIT
	bool
	help
	  This option, if enabled, provides more flexible and linux-like
	  NAND initialization process.

config SYS_NAND_DRIVER_ECC_LAYOUT
	bool
	help
	  Omit standard ECC layouts to safe space. Select this if your driver
	  is known to provide its own ECC layout.

config SYS_NAND_USE_FLASH_BBT
	bool "Enable BBT (Bad Block Table) support"
	help
	  Enable the BBT (Bad Block Table) usage.

config NAND_ATMEL
	bool "Support Atmel NAND controller"
	imply SYS_NAND_USE_FLASH_BBT
	help
	  Enable this driver for NAND flash platforms using an Atmel NAND
	  controller.

if NAND_ATMEL

config ATMEL_NAND_HWECC
	bool "Atmel Hardware ECC"

config ATMEL_NAND_HW_PMECC
	bool "Atmel Programmable Multibit ECC (PMECC)"
	select ATMEL_NAND_HWECC
	help
	  The Programmable Multibit ECC (PMECC) controller is a programmable
	  binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.

config PMECC_CAP
	int "PMECC Correctable ECC Bits"
	depends on ATMEL_NAND_HW_PMECC
	default 2
	help
	  Correctable ECC bits, can be 2, 4, 8, 12, and 24.

config PMECC_SECTOR_SIZE
	int "PMECC Sector Size"
	depends on ATMEL_NAND_HW_PMECC
	default 512
	help
	  Sector size, in bytes, can be 512 or 1024.

config SPL_GENERATE_ATMEL_PMECC_HEADER
	bool "Atmel PMECC Header Generation"
	select ATMEL_NAND_HWECC
	select ATMEL_NAND_HW_PMECC
	help
	  Generate Programmable Multibit ECC (PMECC) header for SPL image.

endif

config NAND_BRCMNAND
	bool "Support Broadcom NAND controller"
	depends on OF_CONTROL && DM && DM_MTD
	help
	  Enable the driver for NAND flash on platforms using a Broadcom NAND
	  controller.

config NAND_BRCMNAND_6368
	bool "Support Broadcom NAND controller on bcm6368"
	depends on NAND_BRCMNAND && ARCH_BMIPS
	help
	  Enable support for broadcom nand driver on bcm6368.

config NAND_BRCMNAND_68360
       bool "Support Broadcom NAND controller on bcm68360"
       depends on NAND_BRCMNAND && ARCH_BCM68360
       help
         Enable support for broadcom nand driver on bcm68360.

config NAND_BRCMNAND_6838
       bool "Support Broadcom NAND controller on bcm6838"
       depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
       help
         Enable support for broadcom nand driver on bcm6838.

config NAND_BRCMNAND_6858
       bool "Support Broadcom NAND controller on bcm6858"
       depends on NAND_BRCMNAND && ARCH_BCM6858
       help
         Enable support for broadcom nand driver on bcm6858.

config NAND_BRCMNAND_63158
       bool "Support Broadcom NAND controller on bcm63158"
       depends on NAND_BRCMNAND && ARCH_BCM63158
       help
         Enable support for broadcom nand driver on bcm63158.

config NAND_DAVINCI
	bool "Support TI Davinci NAND controller"
	help
	  Enable this driver for NAND flash controllers available in TI Davinci
	  and Keystone2 platforms

config KEYSTONE_RBL_NAND
	depends on ARCH_KEYSTONE
	def_bool y

config SPL_NAND_LOAD
	def_bool y
	depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT

config NAND_DENALI
	bool
	select SYS_NAND_SELF_INIT
	imply CMD_NAND

config NAND_DENALI_DT
	bool "Support Denali NAND controller as a DT device"
	select NAND_DENALI
	depends on OF_CONTROL && DM_MTD
	help
	  Enable the driver for NAND flash on platforms using a Denali NAND
	  controller as a DT device.

config NAND_FSL_ELBC
	bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
	depends on FSL_ELBC
	help
	  Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.

config NAND_FSL_IFC
	bool "Support Freescale Integrated Flash Controller NAND driver"
	help
	  Enable the Freescale Integrated Flash Controller NAND driver.

config NAND_LPC32XX_MLC
	bool "Support LPC32XX_MLC controller"
	help
	  Enable the LPC32XX MLC NAND controller.

config NAND_LPC32XX_SLC
	bool "Support LPC32XX_SLC controller"
	help
	  Enable the LPC32XX SLC NAND controller.

config NAND_OMAP_GPMC
	bool "Support OMAP GPMC NAND controller"
	depends on ARCH_OMAP2PLUS
	help
	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	  GPMC controller is used for parallel NAND flash devices, and can
	  do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	  and BCH16 ECC algorithms.

config NAND_OMAP_GPMC_PREFETCH
	bool "Enable GPMC Prefetch"
	depends on NAND_OMAP_GPMC
	default y
	help
	  On OMAP platforms that use the GPMC controller
	  (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	  uses the prefetch mode to speed up read operations.

config NAND_OMAP_ELM
	bool "Enable ELM driver for OMAPxx and AMxx platforms."
	depends on NAND_OMAP_GPMC && !OMAP34XX
	help
	  ELM controller is used for ECC error detection (not ECC calculation)
	  of BCH4, BCH8 and BCH16 ECC algorithms.
	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	  thus such SoC platforms need to depend on software library for ECC error
	  detection. However ECC calculation on such plaforms would still be
	  done by GPMC controller.

config NAND_VF610_NFC
	bool "Support for Freescale NFC for VF610"
	select SYS_NAND_SELF_INIT
	select SYS_NAND_DRIVER_ECC_LAYOUT
	imply CMD_NAND
	help
	  Enables support for NAND Flash Controller on some Freescale
	  processors like the VF610, MCF54418 or Kinetis K70.
	  The driver supports a maximum 2k page size. The driver
	  currently does not support hardware ECC.

if NAND_VF610_NFC

config NAND_VF610_NFC_DT
        bool "Support Vybrid's vf610 NAND controller as a DT device"
        depends on OF_CONTROL && DM_MTD
        help
          Enable the driver for Vybrid's vf610 NAND flash on platforms
	  using device tree.

choice
	prompt "Hardware ECC strength"
	depends on NAND_VF610_NFC
	default SYS_NAND_VF610_NFC_45_ECC_BYTES
	help
	  Select the ECC strength used in the hardware BCH ECC block.

config SYS_NAND_VF610_NFC_45_ECC_BYTES
	bool "24-error correction (45 ECC bytes)"

config SYS_NAND_VF610_NFC_60_ECC_BYTES
	bool "32-error correction (60 ECC bytes)"

endchoice

endif

config NAND_PXA3XX
	bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
	select SYS_NAND_SELF_INIT
	select DM_MTD
	select REGMAP
	select SYSCON
	imply CMD_NAND
	help
	  This enables the driver for the NAND flash device found on
	  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).

config NAND_SUNXI
	bool "Support for NAND on Allwinner SoCs"
	default ARCH_SUNXI
	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
	select SYS_NAND_SELF_INIT
	select SYS_NAND_U_BOOT_LOCATIONS
	select SPL_NAND_SUPPORT
	imply CMD_NAND
	---help---
	Enable support for NAND. This option enables the standard and
	SPL drivers.
	The SPL driver only supports reading from the NAND using DMA
	transfers.

if NAND_SUNXI

config NAND_SUNXI_SPL_ECC_STRENGTH
	int "Allwinner NAND SPL ECC Strength"
	default 64

config NAND_SUNXI_SPL_ECC_SIZE
	int "Allwinner NAND SPL ECC Step Size"
	default 1024

config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
	int "Allwinner NAND SPL Usable Page Size"
	default 1024

endif

config NAND_ARASAN
	bool "Configure Arasan Nand"
	select SYS_NAND_SELF_INIT
	depends on DM_MTD
	imply CMD_NAND
	help
	  This enables Nand driver support for Arasan nand flash
	  controller. This uses the hardware ECC for read and
	  write operations.

config NAND_MXC
	bool "MXC NAND support"
	depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
	imply CMD_NAND
	help
	  This enables the NAND driver for the NAND flash controller on the
	  i.MX27 / i.MX31 / i.MX5 rocessors.

config NAND_MXS
	bool "MXS NAND support"
	depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
	select SYS_NAND_SELF_INIT
	imply CMD_NAND
	select APBH_DMA
	select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
	select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
	help
	  This enables NAND driver for the NAND flash controller on the
	  MXS processors.

if NAND_MXS

config NAND_MXS_DT
	bool "Support MXS NAND controller as a DT device"
	depends on OF_CONTROL && DM_MTD
	help
	  Enable the driver for MXS NAND flash on platforms using
	  device tree.

config NAND_MXS_USE_MINIMUM_ECC
	bool "Use minimum ECC strength supported by the controller"
	default false

endif

config NAND_ZYNQ
	bool "Support for Zynq Nand controller"
	select SYS_NAND_SELF_INIT
	select DM_MTD
	imply CMD_NAND
	help
	  This enables Nand driver support for Nand flash controller
	  found on Zynq SoC.

config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
	bool "Enable use of 1st stage bootloader timing for NAND"
	depends on NAND_ZYNQ
	help
	  This flag prevent U-boot reconfigure NAND flash controller and reuse
	  the NAND timing from 1st stage bootloader.

config NAND_OCTEONTX
	bool "Support for OcteonTX NAND controller"
	select SYS_NAND_SELF_INIT
	imply CMD_NAND
	help
	 This enables Nand flash controller hardware found on the OcteonTX
	 processors.

config NAND_OCTEONTX_HW_ECC
	bool "Support Hardware ECC for OcteonTX NAND controller"
	depends on NAND_OCTEONTX
	default y
	help
	 This enables Hardware BCH engine found on the OcteonTX processors to
	 support ECC for NAND flash controller.

config NAND_STM32_FMC2
	bool "Support for NAND controller on STM32MP SoCs"
	depends on ARCH_STM32MP
	select SYS_NAND_SELF_INIT
	imply CMD_NAND
	help
	  Enables support for NAND Flash chips on SoCs containing the FMC2
	  NAND controller. This controller is found on STM32MP SoCs.
	  The controller supports a maximum 8k page size and supports
	  a maximum 8-bit correction error per sector of 512 bytes.

config CORTINA_NAND
	bool "Support for NAND controller on Cortina-Access SoCs"
	depends on CORTINA_PLATFORM
	select SYS_NAND_SELF_INIT
	select DM_MTD
	imply CMD_NAND
	help
	  Enables support for NAND Flash chips on Coartina-Access SoCs platform
	  This controller is found on Presidio/Venus SoCs.
	  The controller supports a maximum 8k page size and supports
	  a maximum 40-bit error correction per sector of 1024 bytes.

config ROCKCHIP_NAND
	bool "Support for NAND controller on Rockchip SoCs"
	depends on ARCH_ROCKCHIP
	select SYS_NAND_SELF_INIT
	select DM_MTD
	imply CMD_NAND
	help
	  Enables support for NAND Flash chips on Rockchip SoCs platform.
	  This controller is found on Rockchip SoCs.
	  There are four different versions of NAND FLASH Controllers,
	  including:
	    NFC v600: RK2928, RK3066, RK3188
	    NFC v622: RK3036, RK3128
	    NFC v800: RK3308, RV1108
	    NFC v900: PX30, RK3326

comment "Generic NAND options"

config SYS_NAND_BLOCK_SIZE
	hex "NAND chip eraseblock size"
	depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
	help
	  Number of data bytes in one eraseblock for the NAND chip on the
	  board. This is the multiple of NAND_PAGE_SIZE and the number of
	  pages.

config SYS_NAND_ONFI_DETECTION
	bool "Enable detection of ONFI compliant devices during probe"
	help
	  Enables detection of ONFI compliant devices during probe.
	  And fetching device parameters flashed on device, by parsing
	  ONFI parameter page.

config SYS_NAND_PAGE_COUNT
	hex "NAND chip page count"
	depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
		SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
	help
	  Number of pages in the NAND chip.

config SYS_NAND_PAGE_SIZE
	hex "NAND chip page size"
	depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
		SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
		(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
	help
	  Number of data bytes in one page for the NAND chip on the
	  board, not including the OOB area.

config SYS_NAND_OOBSIZE
	hex "NAND chip OOB size"
	depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
		SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
		(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
	help
	  Number of bytes in the Out-Of-Band area for the NAND chip on
	  the board.

# Enhance depends when converting drivers to Kconfig which use this config
# option (mxc_nand, ndfc, omap_gpmc).
config SYS_NAND_BUSWIDTH_16BIT
	bool "Use 16-bit NAND interface"
	depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
	help
	  Indicates that NAND device has 16-bit wide data-bus. In absence of this
	  config, bus-width of NAND device is assumed to be either 8-bit and later
	  determined by reading ONFI params.
	  Above config is useful when NAND device's bus-width information cannot
	  be determined from on-chip ONFI params, like in following scenarios:
	  - SPL boot does not support reading of ONFI parameters. This is done to
	    keep SPL code foot-print small.
	  - In current U-Boot flow using nand_init(), driver initialization
	    happens in board_nand_init() which is called before any device probe
	    (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
	    not available while configuring controller. So a static CONFIG_NAND_xx
	    is needed to know the device's bus-width in advance.

if SPL

config SYS_NAND_5_ADDR_CYCLE
	bool "Wait 5 address cycles during NAND commands"
	depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
		(SPL_NAND_SUPPORT && NAND_ATMEL)
	default y
	help
	  Some controllers require waiting for 5 address cycles when issuing
	  some commands, on NAND chips larger than 128MiB.

choice
	prompt "NAND bad block marker/indicator position in the OOB"
	depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
		SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
	default HAS_NAND_LARGE_BADBLOCK_POS
	help
	  In the OOB, which position contains the badblock information.

config HAS_NAND_LARGE_BADBLOCK_POS
	bool "Set the bad block marker/indicator to the 'large' position"

config HAS_NAND_SMALL_BADBLOCK_POS
	bool "Set the bad block marker/indicator to the 'small' position"

endchoice

config SYS_NAND_BAD_BLOCK_POS
	int
	default 0 if HAS_NAND_LARGE_BADBLOCK_POS
	default 5 if HAS_NAND_SMALL_BADBLOCK_POS

config SYS_NAND_U_BOOT_LOCATIONS
	bool "Define U-boot binaries locations in NAND"
	help
	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
	This option should not be enabled when compiling U-boot for boards
	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
	file.

config SYS_NAND_U_BOOT_OFFS
	hex "Location in NAND to read U-Boot from"
	default 0x800000 if NAND_SUNXI
	depends on SYS_NAND_U_BOOT_LOCATIONS
	help
	Set the offset from the start of the nand where u-boot should be
	loaded from.

config SYS_NAND_U_BOOT_OFFS_REDUND
	hex "Location in NAND to read U-Boot from"
	default SYS_NAND_U_BOOT_OFFS
	depends on SYS_NAND_U_BOOT_LOCATIONS
	help
	Set the offset from the start of the nand where the redundant u-boot
	should be loaded from.

config SPL_NAND_AM33XX_BCH
	bool "Enables SPL-NAND driver which supports ELM based"
	depends on NAND_OMAP_GPMC && !OMAP34XX
	default y
        help
	  Hardware ECC correction. This is useful for platforms which have ELM
	  hardware engine and use NAND boot mode.
	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
          SPL-NAND driver with software ECC correction support.

config SPL_NAND_DENALI
	bool "Support Denali NAND controller for SPL"
	help
	  This is a small implementation of the Denali NAND controller
	  for use on SPL.

config NAND_DENALI_SPARE_AREA_SKIP_BYTES
	int "Number of bytes skipped in OOB area"
	depends on SPL_NAND_DENALI
	range 0 63
	help
	  This option specifies the number of bytes to skip from the beginning
	  of OOB area before last ECC sector data starts.  This is potentially
	  used to preserve the bad block marker in the OOB area.

config SPL_NAND_SIMPLE
	bool "Use simple SPL NAND driver"
	depends on !SPL_NAND_AM33XX_BCH
	help
	  Support for NAND boot using simple NAND drivers that
	  expose the cmd_ctrl() interface.
endif

endif   # if NAND
Commit	Line	Data
a430fa06	1
88718be3	2	menuconfig MTD_RAW_NAND
3657b2f4	3	bool "Raw NAND Device Support"
88718be3	4	if MTD_RAW_NAND
a430fa06 MR	5
	6	config SYS_NAND_SELF_INIT
	7	bool
	8	help
	9	This option, if enabled, provides more flexible and linux-like
	10	NAND initialization process.
	11
a38c3af8 SA	12	config SYS_NAND_DRIVER_ECC_LAYOUT
	13	bool
	14	help
	15	Omit standard ECC layouts to safe space. Select this if your driver
	16	is known to provide its own ECC layout.
	17
c680df7e SR	18	config SYS_NAND_USE_FLASH_BBT
	19	bool "Enable BBT (Bad Block Table) support"
	20	help
	21	Enable the BBT (Bad Block Table) usage.
	22
a430fa06 MR	23	config NAND_ATMEL
	24	bool "Support Atmel NAND controller"
	25	imply SYS_NAND_USE_FLASH_BBT
	26	help
	27	Enable this driver for NAND flash platforms using an Atmel NAND
	28	controller.
	29
49ad4029 DW	30	if NAND_ATMEL
	31
	32	config ATMEL_NAND_HWECC
	33	bool "Atmel Hardware ECC"
49ad4029 DW	34
	35	config ATMEL_NAND_HW_PMECC
	36	bool "Atmel Programmable Multibit ECC (PMECC)"
	37	select ATMEL_NAND_HWECC
49ad4029 DW	38	help
	39	The Programmable Multibit ECC (PMECC) controller is a programmable
	40	binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
	41
	42	config PMECC_CAP
	43	int "PMECC Correctable ECC Bits"
	44	depends on ATMEL_NAND_HW_PMECC
	45	default 2
	46	help
	47	Correctable ECC bits, can be 2, 4, 8, 12, and 24.
	48
	49	config PMECC_SECTOR_SIZE
	50	int "PMECC Sector Size"
	51	depends on ATMEL_NAND_HW_PMECC
	52	default 512
	53	help
	54	Sector size, in bytes, can be 512 or 1024.
	55
	56	config SPL_GENERATE_ATMEL_PMECC_HEADER
	57	bool "Atmel PMECC Header Generation"
	58	select ATMEL_NAND_HWECC
	59	select ATMEL_NAND_HW_PMECC
49ad4029 DW	60	help
	61	Generate Programmable Multibit ECC (PMECC) header for SPL image.
	62
	63	endif
	64
22daafba PR	65	config NAND_BRCMNAND
22daafba PR	66	bool "Support Broadcom NAND controller"
1de770d5	67	depends on OF_CONTROL && DM && DM_MTD
22daafba PR	68	help
	69	Enable the driver for NAND flash on platforms using a Broadcom NAND
	70	controller.
	71
a9f80cf9 ÁFR	72	config NAND_BRCMNAND_6368
	73	bool "Support Broadcom NAND controller on bcm6368"
	74	depends on NAND_BRCMNAND && ARCH_BMIPS
	75	help
	76	Enable support for broadcom nand driver on bcm6368.
	77
14533011 PR	78	config NAND_BRCMNAND_68360
	79	bool "Support Broadcom NAND controller on bcm68360"
	80	depends on NAND_BRCMNAND && ARCH_BCM68360
	81	help
	82	Enable support for broadcom nand driver on bcm68360.
	83
22daafba PR	84	config NAND_BRCMNAND_6838
	85	bool "Support Broadcom NAND controller on bcm6838"
	86	depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
	87	help
	88	Enable support for broadcom nand driver on bcm6838.
	89
	90	config NAND_BRCMNAND_6858
	91	bool "Support Broadcom NAND controller on bcm6858"
	92	depends on NAND_BRCMNAND && ARCH_BCM6858
	93	help
	94	Enable support for broadcom nand driver on bcm6858.
	95
	96	config NAND_BRCMNAND_63158
	97	bool "Support Broadcom NAND controller on bcm63158"
	98	depends on NAND_BRCMNAND && ARCH_BCM63158
	99	help
	100	Enable support for broadcom nand driver on bcm63158.
	101
a430fa06 MR	102	config NAND_DAVINCI
	103	bool "Support TI Davinci NAND controller"
	104	help
	105	Enable this driver for NAND flash controllers available in TI Davinci
	106	and Keystone2 platforms
	107
c8c934b9 TR	108	config KEYSTONE_RBL_NAND
	109	depends on ARCH_KEYSTONE
	110	def_bool y
	111
a0de0753 TR	112	config SPL_NAND_LOAD
	113	def_bool y
	114	depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
	115
a430fa06 MR	116	config NAND_DENALI
	117	bool
	118	select SYS_NAND_SELF_INIT
	119	imply CMD_NAND
	120
	121	config NAND_DENALI_DT
	122	bool "Support Denali NAND controller as a DT device"
	123	select NAND_DENALI
407b01b3	124	depends on OF_CONTROL && DM_MTD
a430fa06 MR	125	help
	126	Enable the driver for NAND flash on platforms using a Denali NAND
	127	controller as a DT device.
	128
53f06134 TR	129	config NAND_FSL_ELBC
	130	bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
	131	depends on FSL_ELBC
	132	help
	133	Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
	134
	135	config NAND_FSL_IFC
	136	bool "Support Freescale Integrated Flash Controller NAND driver"
	137	help
	138	Enable the Freescale Integrated Flash Controller NAND driver.
	139
ccdc7cfb TR	140	config NAND_LPC32XX_MLC
	141	bool "Support LPC32XX_MLC controller"
	142	help
	143	Enable the LPC32XX MLC NAND controller.
	144
a430fa06 MR	145	config NAND_LPC32XX_SLC
	146	bool "Support LPC32XX_SLC controller"
	147	help
	148	Enable the LPC32XX SLC NAND controller.
	149
	150	config NAND_OMAP_GPMC
	151	bool "Support OMAP GPMC NAND controller"
	152	depends on ARCH_OMAP2PLUS
	153	help
	154	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	155	GPMC controller is used for parallel NAND flash devices, and can
	156	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	157	and BCH16 ECC algorithms.
	158
	159	config NAND_OMAP_GPMC_PREFETCH
	160	bool "Enable GPMC Prefetch"
	161	depends on NAND_OMAP_GPMC
	162	default y
	163	help
	164	On OMAP platforms that use the GPMC controller
	165	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	166	uses the prefetch mode to speed up read operations.
	167
	168	config NAND_OMAP_ELM
	169	bool "Enable ELM driver for OMAPxx and AMxx platforms."
	170	depends on NAND_OMAP_GPMC && !OMAP34XX
	171	help
	172	ELM controller is used for ECC error detection (not ECC calculation)
	173	of BCH4, BCH8 and BCH16 ECC algorithms.
	174	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	175	thus such SoC platforms need to depend on software library for ECC error
	176	detection. However ECC calculation on such plaforms would still be
	177	done by GPMC controller.
	178
	179	config NAND_VF610_NFC
	180	bool "Support for Freescale NFC for VF610"
	181	select SYS_NAND_SELF_INIT
a38c3af8	182	select SYS_NAND_DRIVER_ECC_LAYOUT
a430fa06 MR	183	imply CMD_NAND
	184	help
	185	Enables support for NAND Flash Controller on some Freescale
	186	processors like the VF610, MCF54418 or Kinetis K70.
	187	The driver supports a maximum 2k page size. The driver
	188	currently does not support hardware ECC.
	189
8a12d127 LM	190	if NAND_VF610_NFC
	191
	192	config NAND_VF610_NFC_DT
	193	bool "Support Vybrid's vf610 NAND controller as a DT device"
1de770d5	194	depends on OF_CONTROL && DM_MTD
8a12d127 LM	195	help
	196	Enable the driver for Vybrid's vf610 NAND flash on platforms
	197	using device tree.
	198
a430fa06 MR	199	choice
	200	prompt "Hardware ECC strength"
	201	depends on NAND_VF610_NFC
	202	default SYS_NAND_VF610_NFC_45_ECC_BYTES
	203	help
	204	Select the ECC strength used in the hardware BCH ECC block.
	205
	206	config SYS_NAND_VF610_NFC_45_ECC_BYTES
	207	bool "24-error correction (45 ECC bytes)"
	208
	209	config SYS_NAND_VF610_NFC_60_ECC_BYTES
	210	bool "32-error correction (60 ECC bytes)"
	211
	212	endchoice
	213
8a12d127 LM	214	endif
8a12d127 LM	215
a430fa06 MR	216	config NAND_PXA3XX
	217	bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
	218	select SYS_NAND_SELF_INIT
8dddfff4	219	select DM_MTD
aaedaaae SH	220	select REGMAP
aaedaaae SH	221	select SYSCON
a430fa06 MR	222	imply CMD_NAND
	223	help
	224	This enables the driver for the NAND flash device found on
	225	PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
	226
	227	config NAND_SUNXI
	228	bool "Support for NAND on Allwinner SoCs"
	229	default ARCH_SUNXI
	230	depends on MACH_SUN4I \|\| MACH_SUN5I \|\| MACH_SUN7I \|\| MACH_SUN8I
	231	select SYS_NAND_SELF_INIT
	232	select SYS_NAND_U_BOOT_LOCATIONS
	233	select SPL_NAND_SUPPORT
	234	imply CMD_NAND
	235	---help---
	236	Enable support for NAND. This option enables the standard and
	237	SPL drivers.
	238	The SPL driver only supports reading from the NAND using DMA
	239	transfers.
	240
	241	if NAND_SUNXI
	242
	243	config NAND_SUNXI_SPL_ECC_STRENGTH
	244	int "Allwinner NAND SPL ECC Strength"
	245	default 64
	246
	247	config NAND_SUNXI_SPL_ECC_SIZE
	248	int "Allwinner NAND SPL ECC Step Size"
	249	default 1024
	250
	251	config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
	252	int "Allwinner NAND SPL Usable Page Size"
	253	default 1024
	254
	255	endif
	256
	257	config NAND_ARASAN
	258	bool "Configure Arasan Nand"
	259	select SYS_NAND_SELF_INIT
a253092d	260	depends on DM_MTD
a430fa06 MR	261	imply CMD_NAND
	262	help
	263	This enables Nand driver support for Arasan nand flash
	264	controller. This uses the hardware ECC for read and
	265	write operations.
	266
	267	config NAND_MXC
	268	bool "MXC NAND support"
	269	depends on CPU_ARM926EJS \|\| CPU_ARM1136 \|\| MX5
	270	imply CMD_NAND
	271	help
	272	This enables the NAND driver for the NAND flash controller on the
	273	i.MX27 / i.MX31 / i.MX5 rocessors.
	274
	275	config NAND_MXS
	276	bool "MXS NAND support"
39320e72	277	depends on MX23 \|\| MX28 \|\| MX6 \|\| MX7 \|\| IMX8 \|\| IMX8M
a430fa06 MR	278	select SYS_NAND_SELF_INIT
	279	imply CMD_NAND
	280	select APBH_DMA
39320e72 PF	281	select APBH_DMA_BURST if ARCH_MX6 \|\| ARCH_MX7 \|\| ARCH_IMX8 \|\| ARCH_IMX8M
39320e72 PF	282	select APBH_DMA_BURST8 if ARCH_MX6 \|\| ARCH_MX7 \|\| ARCH_IMX8 \|\| ARCH_IMX8M
a430fa06 MR	283	help
	284	This enables NAND driver for the NAND flash controller on the
	285	MXS processors.
	286
	287	if NAND_MXS
	288
	289	config NAND_MXS_DT
	290	bool "Support MXS NAND controller as a DT device"
1de770d5	291	depends on OF_CONTROL && DM_MTD
a430fa06 MR	292	help
	293	Enable the driver for MXS NAND flash on platforms using
	294	device tree.
	295
	296	config NAND_MXS_USE_MINIMUM_ECC
	297	bool "Use minimum ECC strength supported by the controller"
	298	default false
	299
	300	endif
	301
	302	config NAND_ZYNQ
	303	bool "Support for Zynq Nand controller"
	304	select SYS_NAND_SELF_INIT
45397a6e	305	select DM_MTD
a430fa06 MR	306	imply CMD_NAND
	307	help
	308	This enables Nand driver support for Nand flash controller
	309	found on Zynq SoC.
	310
	311	config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
	312	bool "Enable use of 1st stage bootloader timing for NAND"
	313	depends on NAND_ZYNQ
	314	help
	315	This flag prevent U-boot reconfigure NAND flash controller and reuse
	316	the NAND timing from 1st stage bootloader.
	317
05c7606a SG	318	config NAND_OCTEONTX
	319	bool "Support for OcteonTX NAND controller"
	320	select SYS_NAND_SELF_INIT
	321	imply CMD_NAND
	322	help
	323	This enables Nand flash controller hardware found on the OcteonTX
	324	processors.
	325
	326	config NAND_OCTEONTX_HW_ECC
	327	bool "Support Hardware ECC for OcteonTX NAND controller"
	328	depends on NAND_OCTEONTX
	329	default y
	330	help
	331	This enables Hardware BCH engine found on the OcteonTX processors to
	332	support ECC for NAND flash controller.
	333
7bb75023 CK	334	config NAND_STM32_FMC2
	335	bool "Support for NAND controller on STM32MP SoCs"
	336	depends on ARCH_STM32MP
	337	select SYS_NAND_SELF_INIT
	338	imply CMD_NAND
	339	help
	340	Enables support for NAND Flash chips on SoCs containing the FMC2
	341	NAND controller. This controller is found on STM32MP SoCs.
	342	The controller supports a maximum 8k page size and supports
	343	a maximum 8-bit correction error per sector of 512 bytes.
	344
161df94b KL	345	config CORTINA_NAND
	346	bool "Support for NAND controller on Cortina-Access SoCs"
	347	depends on CORTINA_PLATFORM
	348	select SYS_NAND_SELF_INIT
	349	select DM_MTD
	350	imply CMD_NAND
	351	help
	352	Enables support for NAND Flash chips on Coartina-Access SoCs platform
	353	This controller is found on Presidio/Venus SoCs.
	354	The controller supports a maximum 8k page size and supports
	355	a maximum 40-bit error correction per sector of 1024 bytes.
	356
b12dc5d6 YZ	357	config ROCKCHIP_NAND
	358	bool "Support for NAND controller on Rockchip SoCs"
	359	depends on ARCH_ROCKCHIP
	360	select SYS_NAND_SELF_INIT
	361	select DM_MTD
	362	imply CMD_NAND
	363	help
	364	Enables support for NAND Flash chips on Rockchip SoCs platform.
	365	This controller is found on Rockchip SoCs.
	366	There are four different versions of NAND FLASH Controllers,
	367	including:
	368	NFC v600: RK2928, RK3066, RK3188
	369	NFC v622: RK3036, RK3128
	370	NFC v800: RK3308, RV1108
	371	NFC v900: PX30, RK3326
	372
a430fa06 MR	373	comment "Generic NAND options"
	374
	375	config SYS_NAND_BLOCK_SIZE
	376	hex "NAND chip eraseblock size"
a0de0753 TR	377	depends on ARCH_SUNXI \|\| SPL_NAND_SUPPORT \|\| TPL_NAND_SUPPORT
a0de0753 TR	378	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
a430fa06 MR	379	help
	380	Number of data bytes in one eraseblock for the NAND chip on the
	381	board. This is the multiple of NAND_PAGE_SIZE and the number of
	382	pages.
	383
c0ad62c5 TR	384	config SYS_NAND_ONFI_DETECTION
	385	bool "Enable detection of ONFI compliant devices during probe"
	386	help
	387	Enables detection of ONFI compliant devices during probe.
	388	And fetching device parameters flashed on device, by parsing
	389	ONFI parameter page.
	390
8db73ec1 TR	391	config SYS_NAND_PAGE_COUNT
	392	hex "NAND chip page count"
	393	depends on SPL_NAND_SUPPORT && (NAND_ATMEL \|\| NAND_MXC \|\| \
	394	SPL_NAND_AM33XX_BCH \|\| SPL_NAND_LOAD \|\| SPL_NAND_SIMPLE)
	395	help
	396	Number of pages in the NAND chip.
	397
a430fa06 MR	398	config SYS_NAND_PAGE_SIZE
a430fa06 MR	399	hex "NAND chip page size"
a0de0753 TR	400	depends on ARCH_SUNXI \|\| NAND_OMAP_GPMC \|\| NAND_LPC32XX_SLC \|\| \
	401	SPL_NAND_SIMPLE \|\| (NAND_MXC && SPL_NAND_SUPPORT) \|\| \
	402	(NAND_ATMEL && SPL_NAND_SUPPORT) \|\| SPL_GENERATE_ATMEL_PMECC_HEADER
	403	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
a430fa06 MR	404	help
	405	Number of data bytes in one page for the NAND chip on the
	406	board, not including the OOB area.
	407
	408	config SYS_NAND_OOBSIZE
	409	hex "NAND chip OOB size"
a0de0753 TR	410	depends on ARCH_SUNXI \|\| NAND_OMAP_GPMC \|\| NAND_LPC32XX_SLC \|\| \
	411	SPL_NAND_SIMPLE \|\| (NAND_MXC && SPL_NAND_SUPPORT) \|\| \
	412	(NAND_ATMEL && SPL_NAND_SUPPORT) \|\| SPL_GENERATE_ATMEL_PMECC_HEADER
	413	depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
a430fa06 MR	414	help
	415	Number of bytes in the Out-Of-Band area for the NAND chip on
	416	the board.
	417
	418	# Enhance depends when converting drivers to Kconfig which use this config
	419	# option (mxc_nand, ndfc, omap_gpmc).
	420	config SYS_NAND_BUSWIDTH_16BIT
	421	bool "Use 16-bit NAND interface"
	422	depends on NAND_VF610_NFC \|\| NAND_OMAP_GPMC \|\| NAND_MXC \|\| ARCH_DAVINCI
	423	help
	424	Indicates that NAND device has 16-bit wide data-bus. In absence of this
	425	config, bus-width of NAND device is assumed to be either 8-bit and later
	426	determined by reading ONFI params.
	427	Above config is useful when NAND device's bus-width information cannot
	428	be determined from on-chip ONFI params, like in following scenarios:
	429	- SPL boot does not support reading of ONFI parameters. This is done to
	430	keep SPL code foot-print small.
	431	- In current U-Boot flow using nand_init(), driver initialization
	432	happens in board_nand_init() which is called before any device probe
	433	(nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
	434	not available while configuring controller. So a static CONFIG_NAND_xx
	435	is needed to know the device's bus-width in advance.
	436
	437	if SPL
	438
4884d829 TR	439	config SYS_NAND_5_ADDR_CYCLE
	440	bool "Wait 5 address cycles during NAND commands"
	441	depends on SPL_NAND_AM33XX_BCH \|\| SPL_NAND_SIMPLE \|\| \
	442	(SPL_NAND_SUPPORT && NAND_ATMEL)
	443	default y
	444	help
	445	Some controllers require waiting for 5 address cycles when issuing
	446	some commands, on NAND chips larger than 128MiB.
	447
9d9f59dd	448	choice
c0ad62c5	449	prompt "NAND bad block marker/indicator position in the OOB"
9d9f59dd TR	450	depends on SPL_NAND_AM33XX_BCH \|\| SPL_NAND_DENALI \|\| SPL_NAND_SIMPLE \|\| \
	451	SPL_NAND_SUPPORT && (NAND_ATMEL \|\| NAND_MXC)
	452	default HAS_NAND_LARGE_BADBLOCK_POS
	453	help
	454	In the OOB, which position contains the badblock information.
	455
	456	config HAS_NAND_LARGE_BADBLOCK_POS
	457	bool "Set the bad block marker/indicator to the 'large' position"
	458
	459	config HAS_NAND_SMALL_BADBLOCK_POS
	460	bool "Set the bad block marker/indicator to the 'small' position"
	461
	462	endchoice
	463
	464	config SYS_NAND_BAD_BLOCK_POS
	465	int
	466	default 0 if HAS_NAND_LARGE_BADBLOCK_POS
	467	default 5 if HAS_NAND_SMALL_BADBLOCK_POS
	468
a430fa06 MR	469	config SYS_NAND_U_BOOT_LOCATIONS
	470	bool "Define U-boot binaries locations in NAND"
	471	help
	472	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
	473	This option should not be enabled when compiling U-boot for boards
	474	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
	475	file.
	476
	477	config SYS_NAND_U_BOOT_OFFS
	478	hex "Location in NAND to read U-Boot from"
	479	default 0x800000 if NAND_SUNXI
	480	depends on SYS_NAND_U_BOOT_LOCATIONS
	481	help
	482	Set the offset from the start of the nand where u-boot should be
	483	loaded from.
	484
	485	config SYS_NAND_U_BOOT_OFFS_REDUND
	486	hex "Location in NAND to read U-Boot from"
	487	default SYS_NAND_U_BOOT_OFFS
	488	depends on SYS_NAND_U_BOOT_LOCATIONS
	489	help
	490	Set the offset from the start of the nand where the redundant u-boot
	491	should be loaded from.
	492
	493	config SPL_NAND_AM33XX_BCH
	494	bool "Enables SPL-NAND driver which supports ELM based"
	495	depends on NAND_OMAP_GPMC && !OMAP34XX
	496	default y
	497	help
	498	Hardware ECC correction. This is useful for platforms which have ELM
	499	hardware engine and use NAND boot mode.
	500	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	501	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
	502	SPL-NAND driver with software ECC correction support.
	503
	504	config SPL_NAND_DENALI
	505	bool "Support Denali NAND controller for SPL"
	506	help
	507	This is a small implementation of the Denali NAND controller
	508	for use on SPL.
	509
7a270436 MY	510	config NAND_DENALI_SPARE_AREA_SKIP_BYTES
	511	int "Number of bytes skipped in OOB area"
	512	depends on SPL_NAND_DENALI
	513	range 0 63
	514	help
	515	This option specifies the number of bytes to skip from the beginning
	516	of OOB area before last ECC sector data starts. This is potentially
	517	used to preserve the bad block marker in the OOB area.
	518
a430fa06 MR	519	config SPL_NAND_SIMPLE
	520	bool "Use simple SPL NAND driver"
	521	depends on !SPL_NAND_AM33XX_BCH
	522	help
	523	Support for NAND boot using simple NAND drivers that
	524	expose the cmd_ctrl() interface.
	525	endif
	526
	527	endif # if NAND