[J-u-boot.git] / drivers / mmc / xenon_sdhci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
 *
 * Copyright (C) 2016 Marvell, All Rights Reserved.
 *
 * Author:	Victor Gu <[email protected]>
 * Date:	2016-8-24
 *
 * Included parts of the Linux driver version which was written by:
 * Hu Ziji <[email protected]>
 *
 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
 * Stefan Roese <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <linux/printk.h>
#include <power/regulator.h>

DECLARE_GLOBAL_DATA_PTR;

/* Register Offset of SD Host Controller SOCP self-defined register */
#define SDHC_SYS_CFG_INFO			0x0104
#define SLOT_TYPE_SDIO_SHIFT			24
#define SLOT_TYPE_EMMC_MASK			0xFF
#define SLOT_TYPE_EMMC_SHIFT			16
#define SLOT_TYPE_SD_SDIO_MMC_MASK		0xFF
#define SLOT_TYPE_SD_SDIO_MMC_SHIFT		8
#define NR_SUPPORTED_SLOT_MASK			0x7

#define SDHC_SYS_OP_CTRL			0x0108
#define AUTO_CLKGATE_DISABLE_MASK		BIT(20)
#define SDCLK_IDLEOFF_ENABLE_SHIFT		8
#define SLOT_ENABLE_SHIFT			0

#define SDHC_SYS_EXT_OP_CTRL			0x010C
#define MASK_CMD_CONFLICT_ERROR			BIT(8)

#define SDHC_SLOT_EMMC_CTRL			0x0130
#define ENABLE_DATA_STROBE_SHIFT		24
#define SET_EMMC_RSTN_SHIFT			16
#define EMMC_VCCQ_MASK				0x3
#define EMMC_VCCQ_1_8V				0x1
#define EMMC_VCCQ_1_2V				0x2
#define	EMMC_VCCQ_3_3V				0x3

#define SDHC_SLOT_RETUNING_REQ_CTRL		0x0144
/* retuning compatible */
#define RETUNING_COMPATIBLE			0x1

/* Xenon specific Mode Select value */
#define XENON_SDHCI_CTRL_HS200			0x5
#define XENON_SDHCI_CTRL_HS400			0x6

#define EMMC_PHY_REG_BASE			0x170
#define EMMC_PHY_TIMING_ADJUST			EMMC_PHY_REG_BASE
#define OUTPUT_QSN_PHASE_SELECT			BIT(17)
#define SAMPL_INV_QSP_PHASE_SELECT		BIT(18)
#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT	18
#define EMMC_PHY_SLOW_MODE			BIT(29)
#define PHY_INITIALIZAION			BIT(31)
#define WAIT_CYCLE_BEFORE_USING_MASK		0xf
#define WAIT_CYCLE_BEFORE_USING_SHIFT		12
#define FC_SYNC_EN_DURATION_MASK		0xf
#define FC_SYNC_EN_DURATION_SHIFT		8
#define FC_SYNC_RST_EN_DURATION_MASK		0xf
#define FC_SYNC_RST_EN_DURATION_SHIFT		4
#define FC_SYNC_RST_DURATION_MASK		0xf
#define FC_SYNC_RST_DURATION_SHIFT		0

#define EMMC_PHY_FUNC_CONTROL			(EMMC_PHY_REG_BASE + 0x4)
#define DQ_ASYNC_MODE				BIT(4)
#define DQ_DDR_MODE_SHIFT			8
#define DQ_DDR_MODE_MASK			0xff
#define CMD_DDR_MODE				BIT(16)

#define EMMC_PHY_PAD_CONTROL			(EMMC_PHY_REG_BASE + 0x8)
#define REC_EN_SHIFT				24
#define REC_EN_MASK				0xf
#define FC_DQ_RECEN				BIT(24)
#define FC_CMD_RECEN				BIT(25)
#define FC_QSP_RECEN				BIT(26)
#define FC_QSN_RECEN				BIT(27)
#define OEN_QSN					BIT(28)
#define AUTO_RECEN_CTRL				BIT(30)

#define EMMC_PHY_PAD_CONTROL1			(EMMC_PHY_REG_BASE + 0xc)
#define EMMC5_1_FC_QSP_PD			BIT(9)
#define EMMC5_1_FC_QSP_PU			BIT(25)
#define EMMC5_1_FC_CMD_PD			BIT(8)
#define EMMC5_1_FC_CMD_PU			BIT(24)
#define EMMC5_1_FC_DQ_PD			0xff
#define EMMC5_1_FC_DQ_PU			(0xff << 16)

#define SDHCI_RETUNE_EVT_INTSIG			0x00001000

/* Hyperion only have one slot 0 */
#define XENON_MMC_SLOT_ID_HYPERION		0

#define XENON_MMC_MAX_CLK	400000000
#define XENON_MMC_3V3_UV	3300000
#define XENON_MMC_1V8_UV	1800000

enum soc_pad_ctrl_type {
	SOC_PAD_SD,
	SOC_PAD_FIXED_1_8V,
};

struct xenon_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

struct xenon_sdhci_priv {
	struct sdhci_host host;

	u8 timing;

	unsigned int clock;

	void *pad_ctrl_reg;
	int pad_type;

	struct udevice *vqmmc;
};

static int xenon_mmc_phy_init(struct sdhci_host *host)
{
	struct xenon_sdhci_priv *priv = host->mmc->priv;
	u32 clock = priv->clock;
	u32 time;
	u32 var;

	/* Enable QSP PHASE SELECT */
	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	var |= SAMPL_INV_QSP_PHASE_SELECT;
	if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
	    (priv->timing == MMC_TIMING_UHS_SDR25) ||
	    (priv->timing == MMC_TIMING_UHS_SDR12) ||
	    (priv->timing == MMC_TIMING_SD_HS) ||
	    (priv->timing == MMC_TIMING_LEGACY))
		var |= EMMC_PHY_SLOW_MODE;
	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);

	/* Poll for host MMC PHY clock init to be stable */
	/* Wait up to 10ms */
	time = 100;
	while (time--) {
		var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
		if (var & SDHCI_CLOCK_INT_STABLE)
			break;

		udelay(100);
	}

	if (time <= 0) {
		pr_err("Failed to enable MMC internal clock in time\n");
		return -ETIMEDOUT;
	}

	/* Init PHY */
	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	var |= PHY_INITIALIZAION;
	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);

	if (clock == 0) {
		/* Use the possibly slowest bus frequency value */
		clock = 100000;
	}

	/* Poll for host eMMC PHY init to complete */
	/* Wait up to 10ms */
	time = 100;
	while (time--) {
		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
		var &= PHY_INITIALIZAION;
		if (!var)
			break;

		/* wait for host eMMC PHY init to complete */
		udelay(100);
	}

	if (time <= 0) {
		pr_err("Failed to init MMC PHY in time\n");
		return -ETIMEDOUT;
	}

	return 0;
}

#define ARMADA_3700_SOC_PAD_1_8V	0x1
#define ARMADA_3700_SOC_PAD_3_3V	0x0

static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
{
	struct xenon_sdhci_priv *priv = host->mmc->priv;

	if (priv->pad_type == SOC_PAD_FIXED_1_8V)
		writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
	else if (priv->pad_type == SOC_PAD_SD)
		writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
}

static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
{
	struct xenon_sdhci_priv *priv = host->mmc->priv;
	u8 voltage;
	u32 ctrl;
	int ret = 0;

	/* If there is no vqmmc regulator, return */
	if (!priv->vqmmc)
		return 0;

	if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
		/* Switch to 1.8v */
		ret = regulator_set_value(priv->vqmmc,
					  XENON_MMC_1V8_UV);
	} else if (priv->pad_type == SOC_PAD_SD) {
		/* Get voltage info */
		voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
		voltage &= ~SDHCI_POWER_ON;

		if (voltage == SDHCI_POWER_330) {
			/* Switch to 3.3v */
			ret = regulator_set_value(priv->vqmmc,
						  XENON_MMC_3V3_UV);
		} else {
			/* Switch to 1.8v */
			ret = regulator_set_value(priv->vqmmc,
						  XENON_MMC_1V8_UV);
		}
	}

	/* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
	ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
	if (IS_SD(host->mmc))
		ctrl |= EMMC_VCCQ_3_3V;
	else
		ctrl |= EMMC_VCCQ_1_8V;
	sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);

	if (ret)
		printf("Signal voltage switch fail\n");

	return ret;
}

static void xenon_mmc_phy_set(struct sdhci_host *host)
{
	struct xenon_sdhci_priv *priv = host->mmc->priv;
	u32 var;

	/* Setup pad, set bit[30], bit[28] and bits[26:24] */
	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
	var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
		FC_CMD_RECEN | FC_DQ_RECEN;
	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);

	/* Set CMD and DQ Pull Up */
	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
	var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
	var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);

	/*
	 * If timing belongs to high speed, set bit[17] of
	 * EMMC_PHY_TIMING_ADJUST register
	 */
	if ((priv->timing == MMC_TIMING_MMC_HS400) ||
	    (priv->timing == MMC_TIMING_MMC_HS200) ||
	    (priv->timing == MMC_TIMING_UHS_SDR50) ||
	    (priv->timing == MMC_TIMING_UHS_SDR104) ||
	    (priv->timing == MMC_TIMING_UHS_DDR50) ||
	    (priv->timing == MMC_TIMING_UHS_SDR25) ||
	    (priv->timing == MMC_TIMING_MMC_DDR52)) {
		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
		var |= OUTPUT_QSN_PHASE_SELECT;
		sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
	}

	/*
	 * When setting EMMC_PHY_FUNC_CONTROL register,
	 * SD clock should be disabled
	 */
	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	var &= ~SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);

	var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
	if (host->mmc->ddr_mode) {
		var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
	} else {
		var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
			 CMD_DDR_MODE);
	}
	sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);

	/* Enable bus clock */
	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	var |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);

	xenon_mmc_phy_init(host);
}

/* Enable/Disable the Auto Clock Gating function of this slot */
static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
{
	u32 var;

	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
	if (enable)
		var &= ~AUTO_CLKGATE_DISABLE_MASK;
	else
		var |= AUTO_CLKGATE_DISABLE_MASK;

	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
}

#define SLOT_MASK(slot)		BIT(slot)

/* Enable specific slot */
static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
{
	u32 var;

	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
	var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
}

/* Disable specific slot */
static void xenon_mmc_disable_slot(struct sdhci_host *host, u8 slot)
{
	u32 var;

	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
	var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT);
	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
}

/* Enable Parallel Transfer Mode */
static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
{
	u32 var;

	var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
	var |= SLOT_MASK(slot);
	sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
}

static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
{
	u32 var;

	/* Clear the Re-Tuning Request functionality */
	var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
	var &= ~RETUNING_COMPATIBLE;
	sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);

	/* Clear the Re-tuning Event Signal Enable */
	var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
	var &= ~SDHCI_RETUNE_EVT_INTSIG;
	sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
}

/* Mask command conflict error */
static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
{
	u32  reg;

	reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
	reg |= MASK_CMD_CONFLICT_ERROR;
	sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
}

/* Platform specific function for post set_ios configuration */
static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
{
	struct xenon_sdhci_priv *priv = host->mmc->priv;
	uint speed = host->mmc->tran_speed;
	int pwr_18v = 0;

	/*
	 * Signal Voltage Switching is only applicable for Host Controllers
	 * v3.00 and above.
	 */
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
		xenon_mmc_start_signal_voltage_switch(host);

	if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
	    SDHCI_POWER_180)
		pwr_18v = 1;

	/* Set timing variable according to the configured speed */
	if (IS_SD(host->mmc)) {
		/* SD/SDIO */
		if (pwr_18v) {
			if (host->mmc->ddr_mode)
				priv->timing = MMC_TIMING_UHS_DDR50;
			else if (speed <= 25000000)
				priv->timing = MMC_TIMING_UHS_SDR25;
			else
				priv->timing = MMC_TIMING_UHS_SDR50;
		} else {
			if (speed <= 25000000)
				priv->timing = MMC_TIMING_LEGACY;
			else
				priv->timing = MMC_TIMING_SD_HS;
		}
	} else {
		/* eMMC */
		if (host->mmc->ddr_mode)
			priv->timing = MMC_TIMING_MMC_DDR52;
		else if (speed <= 26000000)
			priv->timing = MMC_TIMING_LEGACY;
		else
			priv->timing = MMC_TIMING_MMC_HS;
	}

	/* Re-init the PHY */
	xenon_mmc_phy_set(host);

	return 0;
}

/* Install a driver specific handler for post set_ios configuration */
static const struct sdhci_ops xenon_sdhci_ops = {
	.set_ios_post = xenon_sdhci_set_ios_post
};

static struct dm_mmc_ops xenon_mmc_ops;

static int xenon_sdhci_probe(struct udevice *dev)
{
	struct xenon_sdhci_plat *plat = dev_get_plat(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct xenon_sdhci_priv *priv = dev_get_priv(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	int ret;

	host->mmc = &plat->mmc;
	host->mmc->priv = host;
	host->mmc->dev = dev;
	upriv->mmc = host->mmc;

	xenon_mmc_ops = sdhci_ops;
	xenon_mmc_ops.wait_dat0 = NULL;

	/* Set quirks */
	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;

	/* Set default timing */
	priv->timing = MMC_TIMING_LEGACY;

	/* Get the vqmmc regulator if there is */
	device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
	/* Set the initial voltage value to 3.3V if there is regulator */
	if (priv->vqmmc) {
		ret = regulator_set_value(priv->vqmmc,
					  XENON_MMC_3V3_UV);
		if (ret) {
			printf("Failed to set VQMMC regulator to 3.3V\n");
			return ret;
		}
	}

	/* Disable auto clock gating during init */
	xenon_mmc_set_acg(host, false);

	/* Enable slot */
	xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);

	/*
	 * Set default power on SoC PHY PAD register (currently only
	 * available on the Armada 3700)
	 */
	if (priv->pad_ctrl_reg)
		armada_3700_soc_pad_voltage_set(host);

	host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;

	ret = mmc_of_parse(dev, &plat->cfg);
	if (ret)
		return ret;

	host->ops = &xenon_sdhci_ops;

	host->max_clk = XENON_MMC_MAX_CLK;
	ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
	if (ret)
		return ret;

	ret = sdhci_probe(dev);
	if (ret)
		return ret;

	/* Enable parallel transfer */
	xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);

	/* Disable tuning functionality of this slot */
	xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);

	/* Enable auto clock gating after init */
	xenon_mmc_set_acg(host, true);

	xenon_mask_cmd_conflict_err(host);

	return ret;
}

static int xenon_sdhci_remove(struct udevice *dev)
{
	struct sdhci_host *host = dev_get_priv(dev);

	xenon_mmc_disable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
	return 0;
}

static int xenon_sdhci_of_to_plat(struct udevice *dev)
{
	struct sdhci_host *host = dev_get_priv(dev);
	struct xenon_sdhci_priv *priv = dev_get_priv(dev);
	const char *name;

	host->name = dev->name;
	host->ioaddr = dev_read_addr_ptr(dev);

	if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
		priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);

	name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
			   NULL);
	if (name) {
		if (0 == strncmp(name, "sd", 2)) {
			priv->pad_type = SOC_PAD_SD;
		} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
			priv->pad_type = SOC_PAD_FIXED_1_8V;
		} else {
			printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
			return -EINVAL;
		}
	}

	return 0;
}

static int xenon_sdhci_bind(struct udevice *dev)
{
	struct xenon_sdhci_plat *plat = dev_get_plat(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id xenon_sdhci_ids[] = {
	{ .compatible = "marvell,armada-8k-sdhci",},
	{ .compatible = "marvell,armada-3700-sdhci",},
	{ }
};

U_BOOT_DRIVER(xenon_sdhci_drv) = {
	.name		= "xenon_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= xenon_sdhci_ids,
	.of_to_plat = xenon_sdhci_of_to_plat,
	.ops		= &xenon_mmc_ops,
	.bind		= xenon_sdhci_bind,
	.probe		= xenon_sdhci_probe,
	.remove		= xenon_sdhci_remove,
	.priv_auto	= sizeof(struct xenon_sdhci_priv),
	.plat_auto	= sizeof(struct xenon_sdhci_plat),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
b6acb5f1 SR	2	/*
	3	* Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
	4	*
	5	* Copyright (C) 2016 Marvell, All Rights Reserved.
	6	*
	7	* Author: Victor Gu <[email protected]>
	8	* Date: 2016-8-24
	9	*
	10	* Included parts of the Linux driver version which was written by:
	11	* Hu Ziji <[email protected]>
	12	*
	13	* Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
	14	* Stefan Roese <[email protected]>
b6acb5f1 SR	15	*/
	16
	17	#include <common.h>
	18	#include <dm.h>
	19	#include <fdtdec.h>
401d1c4f	20	#include <asm/global_data.h>
cd93d625	21	#include <linux/bitops.h>
c05ed00a	22	#include <linux/delay.h>
b08c8c48	23	#include <linux/libfdt.h>
b6acb5f1 SR	24	#include <malloc.h>
b6acb5f1 SR	25	#include <sdhci.h>
1e94b46f	26	#include <linux/printk.h>
91b85e25	27	#include <power/regulator.h>
b6acb5f1 SR	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	/* Register Offset of SD Host Controller SOCP self-defined register */
	32	#define SDHC_SYS_CFG_INFO 0x0104
	33	#define SLOT_TYPE_SDIO_SHIFT 24
	34	#define SLOT_TYPE_EMMC_MASK 0xFF
	35	#define SLOT_TYPE_EMMC_SHIFT 16
	36	#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
	37	#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
	38	#define NR_SUPPORTED_SLOT_MASK 0x7
	39
	40	#define SDHC_SYS_OP_CTRL 0x0108
	41	#define AUTO_CLKGATE_DISABLE_MASK BIT(20)
	42	#define SDCLK_IDLEOFF_ENABLE_SHIFT 8
	43	#define SLOT_ENABLE_SHIFT 0
	44
	45	#define SDHC_SYS_EXT_OP_CTRL 0x010C
	46	#define MASK_CMD_CONFLICT_ERROR BIT(8)
	47
91b85e25 EW	48	#define SDHC_SLOT_EMMC_CTRL 0x0130
	49	#define ENABLE_DATA_STROBE_SHIFT 24
	50	#define SET_EMMC_RSTN_SHIFT 16
	51	#define EMMC_VCCQ_MASK 0x3
	52	#define EMMC_VCCQ_1_8V 0x1
	53	#define EMMC_VCCQ_1_2V 0x2
	54	#define EMMC_VCCQ_3_3V 0x3
	55
b6acb5f1 SR	56	#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
	57	/* retuning compatible */
	58	#define RETUNING_COMPATIBLE 0x1
	59
	60	/* Xenon specific Mode Select value */
	61	#define XENON_SDHCI_CTRL_HS200 0x5
	62	#define XENON_SDHCI_CTRL_HS400 0x6
	63
	64	#define EMMC_PHY_REG_BASE 0x170
	65	#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE
	66	#define OUTPUT_QSN_PHASE_SELECT BIT(17)
	67	#define SAMPL_INV_QSP_PHASE_SELECT BIT(18)
	68	#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
	69	#define EMMC_PHY_SLOW_MODE BIT(29)
	70	#define PHY_INITIALIZAION BIT(31)
	71	#define WAIT_CYCLE_BEFORE_USING_MASK 0xf
	72	#define WAIT_CYCLE_BEFORE_USING_SHIFT 12
	73	#define FC_SYNC_EN_DURATION_MASK 0xf
	74	#define FC_SYNC_EN_DURATION_SHIFT 8
	75	#define FC_SYNC_RST_EN_DURATION_MASK 0xf
	76	#define FC_SYNC_RST_EN_DURATION_SHIFT 4
	77	#define FC_SYNC_RST_DURATION_MASK 0xf
	78	#define FC_SYNC_RST_DURATION_SHIFT 0
	79
	80	#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4)
	81	#define DQ_ASYNC_MODE BIT(4)
	82	#define DQ_DDR_MODE_SHIFT 8
	83	#define DQ_DDR_MODE_MASK 0xff
	84	#define CMD_DDR_MODE BIT(16)
	85
	86	#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8)
	87	#define REC_EN_SHIFT 24
	88	#define REC_EN_MASK 0xf
	89	#define FC_DQ_RECEN BIT(24)
	90	#define FC_CMD_RECEN BIT(25)
	91	#define FC_QSP_RECEN BIT(26)
	92	#define FC_QSN_RECEN BIT(27)
	93	#define OEN_QSN BIT(28)
	94	#define AUTO_RECEN_CTRL BIT(30)
	95
	96	#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc)
	97	#define EMMC5_1_FC_QSP_PD BIT(9)
	98	#define EMMC5_1_FC_QSP_PU BIT(25)
	99	#define EMMC5_1_FC_CMD_PD BIT(8)
	100	#define EMMC5_1_FC_CMD_PU BIT(24)
	101	#define EMMC5_1_FC_DQ_PD 0xff
	102	#define EMMC5_1_FC_DQ_PU (0xff << 16)
	103
	104	#define SDHCI_RETUNE_EVT_INTSIG 0x00001000
	105
	106	/* Hyperion only have one slot 0 */
	107	#define XENON_MMC_SLOT_ID_HYPERION 0
	108
b6acb5f1	109	#define XENON_MMC_MAX_CLK 400000000
91b85e25 EW	110	#define XENON_MMC_3V3_UV 3300000
91b85e25 EW	111	#define XENON_MMC_1V8_UV 1800000
b6acb5f1 SR	112
	113	enum soc_pad_ctrl_type {
	114	SOC_PAD_SD,
	115	SOC_PAD_FIXED_1_8V,
	116	};
	117
	118	struct xenon_sdhci_plat {
	119	struct mmc_config cfg;
	120	struct mmc mmc;
	121	};
	122
	123	struct xenon_sdhci_priv {
	124	struct sdhci_host host;
	125
	126	u8 timing;
	127
	128	unsigned int clock;
	129
	130	void *pad_ctrl_reg;
	131	int pad_type;
91b85e25 EW	132
91b85e25 EW	133	struct udevice *vqmmc;
b6acb5f1 SR	134	};
	135
	136	static int xenon_mmc_phy_init(struct sdhci_host *host)
	137	{
	138	struct xenon_sdhci_priv *priv = host->mmc->priv;
	139	u32 clock = priv->clock;
	140	u32 time;
	141	u32 var;
	142
	143	/* Enable QSP PHASE SELECT */
	144	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	145	var \|= SAMPL_INV_QSP_PHASE_SELECT;
	146	if ((priv->timing == MMC_TIMING_UHS_SDR50) \|\|
	147	(priv->timing == MMC_TIMING_UHS_SDR25) \|\|
	148	(priv->timing == MMC_TIMING_UHS_SDR12) \|\|
	149	(priv->timing == MMC_TIMING_SD_HS) \|\|
	150	(priv->timing == MMC_TIMING_LEGACY))
	151	var \|= EMMC_PHY_SLOW_MODE;
	152	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
	153
	154	/* Poll for host MMC PHY clock init to be stable */
	155	/* Wait up to 10ms */
	156	time = 100;
	157	while (time--) {
	158	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	159	if (var & SDHCI_CLOCK_INT_STABLE)
	160	break;
	161
	162	udelay(100);
	163	}
	164
	165	if (time <= 0) {
9b643e31	166	pr_err("Failed to enable MMC internal clock in time\n");
b6acb5f1 SR	167	return -ETIMEDOUT;
	168	}
	169
	170	/* Init PHY */
	171	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	172	var \|= PHY_INITIALIZAION;
	173	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
	174
	175	if (clock == 0) {
	176	/* Use the possibly slowest bus frequency value */
	177	clock = 100000;
	178	}
	179
	180	/* Poll for host eMMC PHY init to complete */
	181	/* Wait up to 10ms */
	182	time = 100;
	183	while (time--) {
	184	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	185	var &= PHY_INITIALIZAION;
	186	if (!var)
	187	break;
	188
	189	/* wait for host eMMC PHY init to complete */
	190	udelay(100);
	191	}
	192
	193	if (time <= 0) {
9b643e31	194	pr_err("Failed to init MMC PHY in time\n");
b6acb5f1 SR	195	return -ETIMEDOUT;
	196	}
	197
	198	return 0;
	199	}
	200
	201	#define ARMADA_3700_SOC_PAD_1_8V 0x1
	202	#define ARMADA_3700_SOC_PAD_3_3V 0x0
	203
	204	static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
	205	{
	206	struct xenon_sdhci_priv *priv = host->mmc->priv;
	207
	208	if (priv->pad_type == SOC_PAD_FIXED_1_8V)
	209	writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
	210	else if (priv->pad_type == SOC_PAD_SD)
	211	writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
	212	}
	213
91b85e25 EW	214	static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
	215	{
	216	struct xenon_sdhci_priv *priv = host->mmc->priv;
	217	u8 voltage;
	218	u32 ctrl;
	219	int ret = 0;
	220
	221	/* If there is no vqmmc regulator, return */
	222	if (!priv->vqmmc)
	223	return 0;
	224
	225	if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
	226	/* Switch to 1.8v */
	227	ret = regulator_set_value(priv->vqmmc,
	228	XENON_MMC_1V8_UV);
	229	} else if (priv->pad_type == SOC_PAD_SD) {
	230	/* Get voltage info */
	231	voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
	232	voltage &= ~SDHCI_POWER_ON;
	233
	234	if (voltage == SDHCI_POWER_330) {
	235	/* Switch to 3.3v */
	236	ret = regulator_set_value(priv->vqmmc,
	237	XENON_MMC_3V3_UV);
	238	} else {
	239	/* Switch to 1.8v */
	240	ret = regulator_set_value(priv->vqmmc,
	241	XENON_MMC_1V8_UV);
	242	}
	243	}
	244
	245	/* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
	246	ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
	247	if (IS_SD(host->mmc))
	248	ctrl \|= EMMC_VCCQ_3_3V;
	249	else
	250	ctrl \|= EMMC_VCCQ_1_8V;
	251	sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
	252
	253	if (ret)
	254	printf("Signal voltage switch fail\n");
	255
	256	return ret;
	257	}
	258
b6acb5f1 SR	259	static void xenon_mmc_phy_set(struct sdhci_host *host)
	260	{
	261	struct xenon_sdhci_priv *priv = host->mmc->priv;
	262	u32 var;
	263
	264	/* Setup pad, set bit[30], bit[28] and bits[26:24] */
	265	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
	266	var \|= AUTO_RECEN_CTRL \| OEN_QSN \| FC_QSP_RECEN \|
	267	FC_CMD_RECEN \| FC_DQ_RECEN;
	268	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
	269
	270	/* Set CMD and DQ Pull Up */
	271	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
	272	var \|= (EMMC5_1_FC_CMD_PU \| EMMC5_1_FC_DQ_PU);
	273	var &= ~(EMMC5_1_FC_CMD_PD \| EMMC5_1_FC_DQ_PD);
	274	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
	275
	276	/*
	277	* If timing belongs to high speed, set bit[17] of
	278	* EMMC_PHY_TIMING_ADJUST register
	279	*/
	280	if ((priv->timing == MMC_TIMING_MMC_HS400) \|\|
	281	(priv->timing == MMC_TIMING_MMC_HS200) \|\|
	282	(priv->timing == MMC_TIMING_UHS_SDR50) \|\|
	283	(priv->timing == MMC_TIMING_UHS_SDR104) \|\|
	284	(priv->timing == MMC_TIMING_UHS_DDR50) \|\|
	285	(priv->timing == MMC_TIMING_UHS_SDR25) \|\|
	286	(priv->timing == MMC_TIMING_MMC_DDR52)) {
	287	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
	288	var \|= OUTPUT_QSN_PHASE_SELECT;
	289	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
	290	}
	291
	292	/*
	293	* When setting EMMC_PHY_FUNC_CONTROL register,
	294	* SD clock should be disabled
	295	*/
	296	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	297	var &= ~SDHCI_CLOCK_CARD_EN;
	298	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
	299
	300	var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
	301	if (host->mmc->ddr_mode) {
	302	var \|= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) \| CMD_DDR_MODE;
	303	} else {
	304	var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) \|
	305	CMD_DDR_MODE);
	306	}
	307	sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
	308
	309	/* Enable bus clock */
	310	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	311	var \|= SDHCI_CLOCK_CARD_EN;
	312	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
	313
	314	xenon_mmc_phy_init(host);
	315	}
	316
	317	/* Enable/Disable the Auto Clock Gating function of this slot */
	318	static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
	319	{
	320	u32 var;
	321
	322	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
323	if (enable)
324	var &= ~AUTO_CLKGATE_DISABLE_MASK;
325	else
326	var \|= AUTO_CLKGATE_DISABLE_MASK;
327
328	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
329	}
330
331	#define SLOT_MASK(slot) BIT(slot)
332
333	/* Enable specific slot */
334	static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
335	{
336	u32 var;
337
338	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
339	var \|= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
340	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
341	}
342
9d716339 T	343	/* Disable specific slot */
	344	static void xenon_mmc_disable_slot(struct sdhci_host *host, u8 slot)
	345	{
	346	u32 var;
	347
	348	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
	349	var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT);
	350	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
	351	}
	352
b6acb5f1 SR	353	/* Enable Parallel Transfer Mode */
	354	static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
	355	{
	356	u32 var;
	357
	358	var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
	359	var \|= SLOT_MASK(slot);
	360	sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
	361	}
	362
	363	static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
	364	{
	365	u32 var;
	366
	367	/* Clear the Re-Tuning Request functionality */
	368	var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
	369	var &= ~RETUNING_COMPATIBLE;
	370	sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
	371
	372	/* Clear the Re-tuning Event Signal Enable */
	373	var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
	374	var &= ~SDHCI_RETUNE_EVT_INTSIG;
	375	sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
	376	}
	377
	378	/* Mask command conflict error */
	379	static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
	380	{
	381	u32 reg;
	382
	383	reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
	384	reg \|= MASK_CMD_CONFLICT_ERROR;
	385	sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
	386	}
	387
	388	/* Platform specific function for post set_ios configuration */
a8185c50	389	static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
b6acb5f1 SR	390	{
	391	struct xenon_sdhci_priv *priv = host->mmc->priv;
	392	uint speed = host->mmc->tran_speed;
	393	int pwr_18v = 0;
	394
91b85e25 EW	395	/*
	396	* Signal Voltage Switching is only applicable for Host Controllers
	397	* v3.00 and above.
	398	*/
	399	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
	400	xenon_mmc_start_signal_voltage_switch(host);
	401
b6acb5f1 SR	402	if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
	403	SDHCI_POWER_180)
	404	pwr_18v = 1;
	405
	406	/* Set timing variable according to the configured speed */
	407	if (IS_SD(host->mmc)) {
	408	/* SD/SDIO */
	409	if (pwr_18v) {
	410	if (host->mmc->ddr_mode)
	411	priv->timing = MMC_TIMING_UHS_DDR50;
	412	else if (speed <= 25000000)
	413	priv->timing = MMC_TIMING_UHS_SDR25;
	414	else
	415	priv->timing = MMC_TIMING_UHS_SDR50;
	416	} else {
	417	if (speed <= 25000000)
	418	priv->timing = MMC_TIMING_LEGACY;
	419	else
	420	priv->timing = MMC_TIMING_SD_HS;
	421	}
	422	} else {
	423	/* eMMC */
	424	if (host->mmc->ddr_mode)
	425	priv->timing = MMC_TIMING_MMC_DDR52;
	426	else if (speed <= 26000000)
	427	priv->timing = MMC_TIMING_LEGACY;
	428	else
	429	priv->timing = MMC_TIMING_MMC_HS;
	430	}
	431
	432	/* Re-init the PHY */
	433	xenon_mmc_phy_set(host);
a8185c50 FA	434
a8185c50 FA	435	return 0;
b6acb5f1 SR	436	}
	437
	438	/* Install a driver specific handler for post set_ios configuration */
	439	static const struct sdhci_ops xenon_sdhci_ops = {
	440	.set_ios_post = xenon_sdhci_set_ios_post
	441	};
	442
0f3466f5 RM	443	static struct dm_mmc_ops xenon_mmc_ops;
0f3466f5 RM	444
b6acb5f1 SR	445	static int xenon_sdhci_probe(struct udevice *dev)
b6acb5f1 SR	446	{
c69cda25	447	struct xenon_sdhci_plat *plat = dev_get_plat(dev);
b6acb5f1 SR	448	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	449	struct xenon_sdhci_priv *priv = dev_get_priv(dev);
	450	struct sdhci_host *host = dev_get_priv(dev);
	451	int ret;
	452
	453	host->mmc = &plat->mmc;
	454	host->mmc->priv = host;
	455	host->mmc->dev = dev;
	456	upriv->mmc = host->mmc;
	457
0f3466f5 RM	458	xenon_mmc_ops = sdhci_ops;
	459	xenon_mmc_ops.wait_dat0 = NULL;
	460
b6acb5f1 SR	461	/* Set quirks */
	462	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \| SDHCI_QUIRK_32BIT_DMA_ADDR;
	463
	464	/* Set default timing */
	465	priv->timing = MMC_TIMING_LEGACY;
	466
91b85e25 EW	467	/* Get the vqmmc regulator if there is */
	468	device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
	469	/* Set the initial voltage value to 3.3V if there is regulator */
	470	if (priv->vqmmc) {
	471	ret = regulator_set_value(priv->vqmmc,
	472	XENON_MMC_3V3_UV);
	473	if (ret) {
	474	printf("Failed to set VQMMC regulator to 3.3V\n");
	475	return ret;
	476	}
	477	}
	478
b6acb5f1 SR	479	/* Disable auto clock gating during init */
	480	xenon_mmc_set_acg(host, false);
	481
	482	/* Enable slot */
	483	xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
	484
	485	/*
	486	* Set default power on SoC PHY PAD register (currently only
	487	* available on the Armada 3700)
	488	*/
	489	if (priv->pad_ctrl_reg)
	490	armada_3700_soc_pad_voltage_set(host);
	491
	492	host->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_DDR_52MHz;
e79c59c0 AH	493
	494	ret = mmc_of_parse(dev, &plat->cfg);
	495	if (ret)
	496	return ret;
b6acb5f1 SR	497
	498	host->ops = &xenon_sdhci_ops;
	499
de0359c2	500	host->max_clk = XENON_MMC_MAX_CLK;
91b85e25	501	ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
b6acb5f1 SR	502	if (ret)
	503	return ret;
	504
	505	ret = sdhci_probe(dev);
	506	if (ret)
	507	return ret;
	508
	509	/* Enable parallel transfer */
	510	xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
	511
	512	/* Disable tuning functionality of this slot */
	513	xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
	514
	515	/* Enable auto clock gating after init */
	516	xenon_mmc_set_acg(host, true);
	517
	518	xenon_mask_cmd_conflict_err(host);
	519
	520	return ret;
	521	}
	522
9d716339 T	523	static int xenon_sdhci_remove(struct udevice *dev)
	524	{
	525	struct sdhci_host *host = dev_get_priv(dev);
	526
	527	xenon_mmc_disable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
	528	return 0;
	529	}
	530
d1998a9f	531	static int xenon_sdhci_of_to_plat(struct udevice *dev)
b6acb5f1 SR	532	{
	533	struct sdhci_host *host = dev_get_priv(dev);
	534	struct xenon_sdhci_priv *priv = dev_get_priv(dev);
	535	const char *name;
	536
	537	host->name = dev->name;
8613c8d8	538	host->ioaddr = dev_read_addr_ptr(dev);
b6acb5f1	539
911f3aef	540	if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
320a1938	541	priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);
b6acb5f1	542
e160f7d4	543	name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
b6acb5f1 SR	544	NULL);
	545	if (name) {
	546	if (0 == strncmp(name, "sd", 2)) {
	547	priv->pad_type = SOC_PAD_SD;
	548	} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
	549	priv->pad_type = SOC_PAD_FIXED_1_8V;
	550	} else {
	551	printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
	552	return -EINVAL;
	553	}
	554	}
	555
	556	return 0;
	557	}
	558
	559	static int xenon_sdhci_bind(struct udevice *dev)
	560	{
c69cda25	561	struct xenon_sdhci_plat *plat = dev_get_plat(dev);
b6acb5f1 SR	562
	563	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
	564	}
	565
	566	static const struct udevice_id xenon_sdhci_ids[] = {
	567	{ .compatible = "marvell,armada-8k-sdhci",},
	568	{ .compatible = "marvell,armada-3700-sdhci",},
	569	{ }
	570	};
	571
	572	U_BOOT_DRIVER(xenon_sdhci_drv) = {
	573	.name = "xenon_sdhci",
	574	.id = UCLASS_MMC,
	575	.of_match = xenon_sdhci_ids,
d1998a9f	576	.of_to_plat = xenon_sdhci_of_to_plat,
0f3466f5	577	.ops = &xenon_mmc_ops,
b6acb5f1 SR	578	.bind = xenon_sdhci_bind,
b6acb5f1 SR	579	.probe = xenon_sdhci_probe,
9d716339	580	.remove = xenon_sdhci_remove,
41575d8e	581	.priv_auto = sizeof(struct xenon_sdhci_priv),
caa4daa2	582	.plat_auto = sizeof(struct xenon_sdhci_plat),
b6acb5f1	583	};