[J-u-boot.git] / drivers / fpga / Kconfig

menu "FPGA support"

config FPGA
	bool

config FPGA_ALTERA
	bool "Enable Altera FPGA drivers"
	select FPGA
	help
	  Say Y here to enable the Altera FPGA driver

	  This provides basic infrastructure to support Altera FPGA devices.
	  Enable Altera FPGA specific functions which includes bitstream
	  (in BIT format), fpga and device validation.

config FPGA_SOCFPGA
	bool "Enable Gen5 and Arria10 common FPGA drivers"
	select FPGA_ALTERA
	help
	  Say Y here to enable the Gen5 and Arria10 common FPGA driver

	  This provides common functionality for Gen5 and Arria10 devices.

config FPGA_STRATIX_II
	bool "Enable Stratix II FPGA drivers"
	depends on FPGA_ALTERA
	help
	  Say Y here to enable the Altera Stratix II FPGA-specific driver.

config FPGA_STRATIX_V
	bool "Enable Stratix V FPGA drivers"
	depends on FPGA_ALTERA
	help
	  Say Y here to enable the Altera Stratix V FPGA specific driver.

config FPGA_ACEX1K
	bool "Enable Altera ACEX 1K driver"
	depends on FPGA_ALTERA
	help
	  Say Y here to enable the Altera ACEX 1K FPGA specific driver.

config FPGA_CYCLON2
	bool "Enable Altera FPGA driver for Cyclone II"
	depends on FPGA_ALTERA
	help
	  Say Y here to enable the Altera Cyclone II FPGA specific driver

	  This provides common functionality for Altera Cyclone II devices.
	  Enable FPGA driver for loading bitstream in BIT and BIN format
	  on Altera Cyclone II device.

config FPGA_INTEL_SDM_MAILBOX
	bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
	depends on TARGET_SOCFPGA_SOC64
	select FPGA_ALTERA
	help
	  Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver

	  This provides common functionality for Intel FPGA devices.
	  Enable FPGA driver for writing full bitstream into Intel FPGA
	  devices through SDM (Secure Device Manager) Mailbox.

config FPGA_LATTICE
	bool "Enable Lattice FPGA driver"
	help
	  This is used for the lattice FPGAs. Please check the source code as
	  there is no documentation for this at present.

config FPGA_XILINX
	bool "Enable Xilinx FPGA drivers"
	select FPGA
	help
	  Enable Xilinx FPGA specific functions which includes bitstream
	  (in BIT format), fpga and device validation.

config FPGA_ZYNQMPPL
	bool "Enable Xilinx FPGA driver for ZynqMP"
	depends on FPGA_XILINX && ZYNQMP_FIRMWARE
	help
	  Enable FPGA driver for loading bitstream in BIT and BIN format
	  on Xilinx Zynq UltraScale+ (ZynqMP) device.

config FPGA_VERSALPL
	bool "Enable Xilinx FPGA driver for Versal"
	depends on FPGA_XILINX
	help
	  Enable FPGA driver for loading bitstream in PDI format on Xilinx
	  Versal device. PDI is a new programmable device image format for
	  Versal. The bitstream will only be generated as PDI for Versal
	  platform.

config FPGA_SPARTAN2
	bool "Enable Spartan2 FPGA driver"
	depends on FPGA_XILINX
	help
	  Enable Spartan2 FPGA driver.

config FPGA_SPARTAN3
	bool "Enable Spartan3 FPGA driver"
	depends on FPGA_XILINX
	help
	  Enable Spartan3 FPGA driver for loading in BIT format.

config FPGA_VIRTEX2
	bool "Enable Xilinx Virtex-II and later FPGA driver"
	depends on FPGA_XILINX
	help
	  Enable Virtex-II FPGA driver for loading in BIT format. This driver
	  also supports many newer Xilinx FPGA families.

config SYS_FPGA_CHECK_BUSY
	bool "Perform busy check during load from FPGA"
	depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2

config FPGA_ZYNQPL
	bool "Enable Xilinx FPGA for Zynq"
	depends on ARCH_ZYNQ
	help
	  Enable FPGA driver for loading bitstream in BIT and BIN format
	  on Xilinx Zynq devices.

config SYS_FPGA_CHECK_CTRLC
	bool "Allow Control-C to interrupt FPGA configuration"
	depends on FPGA
	help
	  User can interrupt FPGA configuration by pressing CTRL+C.

config SYS_FPGA_PROG_FEEDBACK
	bool "Progress output during FPGA configuration"
	depends on FPGA
	default y if FPGA_VIRTEX2
	help
	  Enable printing of hash marks during FPGA configuration.

config FPGA_LOAD_SECURE
	bool "Enable loading secure bitstreams"
	depends on FPGA
	help
	  Enables the fpga loads() functions that are used to load secure
	  (authenticated or encrypted or both) bitstreams on to FPGA.

config SPL_FPGA_LOAD_SECURE
	bool "Enable loading secure bitstreams for SPL"
	depends on SPL_FPGA
	help
	  Enables the fpga loads() functions that are used to load secure
	  (authenticated or encrypted or both) bitstreams on to FPGA.

config DM_FPGA
	bool "Enable Driver Model for FPGA drivers"
	depends on DM
	select FPGA
	help
	  Enable driver model for Field-Programmable Gate Array (FPGA) devices.
	  The devices cover a wide range of applications and are configured at
	  runtime by loading a bitstream into the FPGA device.
	  Loading a bitstream from any kind of storage is the main task of the
	  FPGA drivers.
	  For now this uclass has no methods yet.

config SANDBOX_FPGA
	bool "Enable sandbox FPGA driver"
	depends on SANDBOX && DM_FPGA
	help
	  This is a driver model based FPGA driver for sandbox.
	  Currently it is a stub only, as there are no usable uclass methods yet.

config MAX_FPGA_DEVICES
	int "Maximum number of FPGA devices"
	depends on FPGA
	default 5

endmenu
Commit	Line	Data
6ded73aa MS	1	menu "FPGA support"
6ded73aa MS	2
6b245014 SDPP	3	config FPGA
	4	bool
	5
98d62e61 PB	6	config FPGA_ALTERA
	7	bool "Enable Altera FPGA drivers"
	8	select FPGA
	9	help
	10	Say Y here to enable the Altera FPGA driver
	11
	12	This provides basic infrastructure to support Altera FPGA devices.
	13	Enable Altera FPGA specific functions which includes bitstream
	14	(in BIT format), fpga and device validation.
	15
fa23ba1a TFC	16	config FPGA_SOCFPGA
	17	bool "Enable Gen5 and Arria10 common FPGA drivers"
	18	select FPGA_ALTERA
	19	help
	20	Say Y here to enable the Gen5 and Arria10 common FPGA driver
	21
	22	This provides common functionality for Gen5 and Arria10 devices.
	23
1edc21a7 SG	24	config FPGA_STRATIX_II
	25	bool "Enable Stratix II FPGA drivers"
	26	depends on FPGA_ALTERA
	27	help
	28	Say Y here to enable the Altera Stratix II FPGA-specific driver.
	29
6e52cb25 TR	30	config FPGA_STRATIX_V
	31	bool "Enable Stratix V FPGA drivers"
	32	depends on FPGA_ALTERA
	33	help
	34	Say Y here to enable the Altera Stratix V FPGA specific driver.
	35
312c4b11 AD	36	config FPGA_ACEX1K
	37	bool "Enable Altera ACEX 1K driver"
	38	depends on FPGA_ALTERA
	39	help
	40	Say Y here to enable the Altera ACEX 1K FPGA specific driver.
	41
98d62e61 PB	42	config FPGA_CYCLON2
	43	bool "Enable Altera FPGA driver for Cyclone II"
	44	depends on FPGA_ALTERA
	45	help
	46	Say Y here to enable the Altera Cyclone II FPGA specific driver
	47
	48	This provides common functionality for Altera Cyclone II devices.
	49	Enable FPGA driver for loading bitstream in BIT and BIN format
	50	on Altera Cyclone II device.
	51
d2170168 CHA	52	config FPGA_INTEL_SDM_MAILBOX
d2170168 CHA	53	bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
9a5bbdfd	54	depends on TARGET_SOCFPGA_SOC64
c41e660b ACH	55	select FPGA_ALTERA
c41e660b ACH	56	help
d2170168	57	Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
c41e660b	58
d2170168 CHA	59	This provides common functionality for Intel FPGA devices.
	60	Enable FPGA driver for writing full bitstream into Intel FPGA
	61	devices through SDM (Secure Device Manager) Mailbox.
c41e660b	62
8badd336 SG	63	config FPGA_LATTICE
	64	bool "Enable Lattice FPGA driver"
	65	help
	66	This is used for the lattice FPGAs. Please check the source code as
	67	there is no documentation for this at present.
	68
6b245014 SDPP	69	config FPGA_XILINX
	70	bool "Enable Xilinx FPGA drivers"
	71	select FPGA
	72	help
	73	Enable Xilinx FPGA specific functions which includes bitstream
	74	(in BIT format), fpga and device validation.
	75
	76	config FPGA_ZYNQMPPL
	77	bool "Enable Xilinx FPGA driver for ZynqMP"
6d87b157	78	depends on FPGA_XILINX && ZYNQMP_FIRMWARE
6b245014 SDPP	79	help
	80	Enable FPGA driver for loading bitstream in BIT and BIN format
	81	on Xilinx Zynq UltraScale+ (ZynqMP) device.
	82
26e054c9 SDPP	83	config FPGA_VERSALPL
	84	bool "Enable Xilinx FPGA driver for Versal"
	85	depends on FPGA_XILINX
	86	help
	87	Enable FPGA driver for loading bitstream in PDI format on Xilinx
	88	Versal device. PDI is a new programmable device image format for
	89	Versal. The bitstream will only be generated as PDI for Versal
	90	platform.
	91
312c4b11 AD	92	config FPGA_SPARTAN2
	93	bool "Enable Spartan2 FPGA driver"
	94	depends on FPGA_XILINX
	95	help
	96	Enable Spartan2 FPGA driver.
	97
f4158346	98	config FPGA_SPARTAN3
a225f810	99	bool "Enable Spartan3 FPGA driver"
25d63a36	100	depends on FPGA_XILINX
a225f810 MS	101	help
a225f810 MS	102	Enable Spartan3 FPGA driver for loading in BIT format.
f4158346	103
25d63a36 RH	104	config FPGA_VIRTEX2
	105	bool "Enable Xilinx Virtex-II and later FPGA driver"
	106	depends on FPGA_XILINX
	107	help
	108	Enable Virtex-II FPGA driver for loading in BIT format. This driver
	109	also supports many newer Xilinx FPGA families.
	110
f00f676a TR	111	config SYS_FPGA_CHECK_BUSY
	112	bool "Perform busy check during load from FPGA"
	113	depends on FPGA_SPARTAN2 \|\| FPGA_SPARTAN3 \|\| FPGA_VIRTEX2
	114
3990c9d6	115	config FPGA_ZYNQPL
a225f810 MS	116	bool "Enable Xilinx FPGA for Zynq"
	117	depends on ARCH_ZYNQ
	118	help
	119	Enable FPGA driver for loading bitstream in BIT and BIN format
	120	on Xilinx Zynq devices.
3990c9d6	121
e8ffc1df AD	122	config SYS_FPGA_CHECK_CTRLC
	123	bool "Allow Control-C to interrupt FPGA configuration"
	124	depends on FPGA
	125	help
	126	User can interrupt FPGA configuration by pressing CTRL+C.
	127
8c09cb6f AD	128	config SYS_FPGA_PROG_FEEDBACK
	129	bool "Progress output during FPGA configuration"
	130	depends on FPGA
	131	default y if FPGA_VIRTEX2
	132	help
	133	Enable printing of hash marks during FPGA configuration.
	134
fb2b8856 OS	135	config FPGA_LOAD_SECURE
	136	bool "Enable loading secure bitstreams"
	137	depends on FPGA
	138	help
	139	Enables the fpga loads() functions that are used to load secure
	140	(authenticated or encrypted or both) bitstreams on to FPGA.
	141
	142	config SPL_FPGA_LOAD_SECURE
	143	bool "Enable loading secure bitstreams for SPL"
	144	depends on SPL_FPGA
	145	help
	146	Enables the fpga loads() functions that are used to load secure
	147	(authenticated or encrypted or both) bitstreams on to FPGA.
	148
1323d08b AD	149	config DM_FPGA
	150	bool "Enable Driver Model for FPGA drivers"
	151	depends on DM
	152	select FPGA
	153	help
	154	Enable driver model for Field-Programmable Gate Array (FPGA) devices.
	155	The devices cover a wide range of applications and are configured at
	156	runtime by loading a bitstream into the FPGA device.
	157	Loading a bitstream from any kind of storage is the main task of the
	158	FPGA drivers.
	159	For now this uclass has no methods yet.
	160
	161	config SANDBOX_FPGA
	162	bool "Enable sandbox FPGA driver"
	163	depends on SANDBOX && DM_FPGA
	164	help
	165	This is a driver model based FPGA driver for sandbox.
	166	Currently it is a stub only, as there are no usable uclass methods yet.
	167
8fe042be TR	168	config MAX_FPGA_DEVICES
	169	int "Maximum number of FPGA devices"
	170	depends on FPGA
	171	default 5
	172
6ded73aa	173	endmenu