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[J-u-boot.git] / board / amcc / katmai / katmai.c
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4745acaa 1/*
1095493a 2 * (C) Copyright 2007-2009
4745acaa
SR		 3 * Stefan Roese, DENX Software Engineering, [email protected].
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
4745acaa
SR		 6 */
7
8#include <common.h>
b36df561 9#include <asm/ppc4xx.h>
4745acaa 10#include <i2c.h>
bf8324e4
SR		 11#include <libfdt.h>
12#include <fdt_support.h>
10efa024 13#include <netdev.h>
c7c6da23
SR		 14#include <asm/processor.h>
15#include <asm/io.h>
09887762 16#include <asm/ppc4xx-gpio.h>
c7c6da23 17#include <asm/4xx_pcie.h>
1221ce45 18#include <linux/errno.h>
4745acaa 19
1218abf1
WD		 20DECLARE_GLOBAL_DATA_PTR;
21
4745acaa
SR		 22int board_early_init_f (void)
23{
24 unsigned long mfr;
4745acaa
SR		 25
26 /*----------------------------------------------------------------------+
27 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
28 *-----------------------------------------------------------------------+
29 *-----------------------------------------------------------------------+
30 * Interrupt | Source | Pol. | Sensi.| Crit. |
31 *-----------+-----------------------------------+-------+-------+-------+
32 * IRQ 00 | UART0 | High | Level | Non |
33 * IRQ 01 | UART1 | High | Level | Non |
34 * IRQ 02 | IIC0 | High | Level | Non |
35 * IRQ 03 | IIC1 | High | Level | Non |
36 * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
37 * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
38 * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
39 * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
40 * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
41 * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
42 * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
43 * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
44 * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
45 * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
46 * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
47 * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
48 * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
49 * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
50 * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
51 * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
52 * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
53 * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
54 * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
55 * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
56 * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
57 * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
58 * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
59 * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
60 * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
61 * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
62 * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
63 * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
64 *------------------------------------------------------------------------
65 * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
66 * IRQ 33 | MAL Serr | High | Level | Non |
67 * IRQ 34 | MAL Txde | High | Level | Non |
68 * IRQ 35 | MAL Rxde | High | Level | Non |
69 * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
70 * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
71 * IRQ 38 | MAL TX EOB | High | Level | Non |
72 * IRQ 39 | MAL RX EOB | High | Level | Non |
73 * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
74 * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
75 * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
76 * IRQ 43 | L2 Cache | Risin | Edge | Non |
77 * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
78 * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
79 * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
80 * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
81 * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
82 * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
83 * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
84 * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
85 * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
86 * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
87 * IRQ 54 | DMA Error | High | Level | Non |
88 * IRQ 55 | DMA I2O Error | High | Level | Non |
89 * IRQ 56 | Serial ROM | High | Level | Non |
90 * IRQ 57 | PCIX0 Error | High | Edge | Non |
91 * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
92 * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
93 * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
94 * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
95 * IRQ 62 | Reserved | High | Level | Non |
96 * IRQ 63 | XOR | High | Level | Non |
97 *-----------------------------------------------------------------------
98 * IRQ 64 | PE0 AL | High | Level | Non |
99 * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
100 * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
101 * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
102 * IRQ 68 | PE0 TCR | High | Level | Non |
103 * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
104 * IRQ 70 | PE0 DCR Error | High | Level | Non |
105 * IRQ 71 | Reserved | N/A | N/A | Non |
106 * IRQ 72 | PE1 AL | High | Level | Non |
107 * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
108 * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
109 * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
110 * IRQ 76 | PE1 TCR | High | Level | Non |
111 * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
112 * IRQ 78 | PE1 DCR Error | High | Level | Non |
113 * IRQ 79 | Reserved | N/A | N/A | Non |
114 * IRQ 80 | PE2 AL | High | Level | Non |
115 * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
116 * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
117 * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
118 * IRQ 84 | PE2 TCR | High | Level | Non |
119 * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
120 * IRQ 86 | PE2 DCR Error | High | Level | Non |
121 * IRQ 87 | Reserved | N/A | N/A | Non |
122 * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
123 * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
124 * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
125 * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
126 * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
127 * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
128 * IRQ 94 | Reserved | N/A | N/A | Non |
129 * IRQ 95 | Reserved | N/A | N/A | Non |
130 *-----------------------------------------------------------------------
131 * IRQ 96 | PE0 INTA | High | Level | Non |
132 * IRQ 97 | PE0 INTB | High | Level | Non |
133 * IRQ 98 | PE0 INTC | High | Level | Non |
134 * IRQ 99 | PE0 INTD | High | Level | Non |
135 * IRQ 100 | PE1 INTA | High | Level | Non |
136 * IRQ 101 | PE1 INTB | High | Level | Non |
137 * IRQ 102 | PE1 INTC | High | Level | Non |
138 * IRQ 103 | PE1 INTD | High | Level | Non |
139 * IRQ 104 | PE2 INTA | High | Level | Non |
140 * IRQ 105 | PE2 INTB | High | Level | Non |
141 * IRQ 106 | PE2 INTC | High | Level | Non |
142 * IRQ 107 | PE2 INTD | Risin | Edge | Non |
143 * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
144 * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
145 * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
146 * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
147 * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
148 * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
149 * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
150 * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
151 * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
152 * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
153 * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
154 * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
155 * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
156 * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
157 * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
158 * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
159 * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
160 * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
161 * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
162 * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
163 *-----------+-----------------------------------+-------+-------+-------+ */
164 /*-------------------------------------------------------------------------+
165 * Put UICs in PowerPC440SPemode.
166 * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
167 * Set critical interrupt values. Set interrupt polarities. Set interrupt
168 * trigger levels. Make bit 0 High priority. Clear all interrupts again.
169 *------------------------------------------------------------------------*/
952e7760
SR		 170 mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
171 mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
172 mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
173 mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
174 mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
175 mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
176 mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
177 mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
178
179
180 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
181 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
182 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
183 mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
184 mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
185 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
186 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
187 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
188
189 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
190 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
191 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
192 mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
193 mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
194 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
195 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
196 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
197
198 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
199 mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
200 mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
201 mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
202 mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
203 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
204 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
205 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
4745acaa 206
d1c3b275 207 mfsdr(SDR0_MFR, mfr);
a27044b1 208 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
d1c3b275 209 mtsdr(SDR0_MFR, mfr);
4745acaa 210
6d0f6bcf 211 mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
4745acaa 212
6d0f6bcf
JCPV		 213 out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
214 out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
215 out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
4745acaa
SR		 216
217 return 0;
218}
219
220int checkboard (void)
221{
f0c0b3a9
WD		 222 char buf[64];
223 int i = getenv_f("serial#", buf, sizeof(buf));
4745acaa
SR		 224
225 printf("Board: Katmai - AMCC 440SPe Evaluation Board");
f0c0b3a9 226 if (i > 0) {
4745acaa 227 puts(", serial# ");
f0c0b3a9 228 puts(buf);
4745acaa
SR		 229 }
230 putc('\n');
231
232 return 0;
233}
234
845c6c95 235/*
a47a12be 236 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
845c6c95
SR		 237 * board specific values.
238 */
239u32 ddr_wrdtr(u32 default_val) {
240 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
241}
242
243u32 ddr_clktr(u32 default_val) {
244 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
245}
246
4745acaa 247#if defined(CONFIG_PCI)
b0b86746 248int board_pcie_card_present(int port)
ba58e4c9
SR		 249{
250 u32 val;
251
252 val = in32(GPIO0_IR);
253 switch (port) {
254 case 0:
6d0f6bcf 255 return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
ba58e4c9 256 case 1:
6d0f6bcf 257 return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
ba58e4c9 258 case 2:
6d0f6bcf 259 return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
ba58e4c9
SR		 260 default:
261 return 0;
262 }
263}
4745acaa
SR		 264#endif /* defined(CONFIG_PCI) */
265
10efa024
BW		 266int board_eth_init(bd_t *bis)
267{
cef0efaf 268 cpu_eth_init(bis);
10efa024
BW		 269 return pci_eth_init(bis);
270}
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