[J-u-boot.git] / board / renesas / lager / lager.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/lager/lager.c
 *     This file is lager board support.
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 * Copyright (C) 2013 Nobuhiro Iwamatsu <[email protected]>
 */

#include <common.h>
#include <environment.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* CPU frequency setting. Set to 1.4GHz */
	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
		u32 stat = 0;
		u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
			<< PLL0_STC_BIT;
		clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);

		do {
			stat = readl(PLLECR) & PLL0ST;
		} while (stat == 0x0);
	}

	/* QoS(Quality-of-Service) Init */
	qos_init();
}

#define TMU0_MSTP125	BIT(25)

#define SD1CKCR		0xE6150078
#define SD2CKCR		0xE615026C
#define SD_97500KHZ	0x7

int board_early_init_f(void)
{
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/*
	 * SD0 clock is set to 97.5MHz by default.
	 * Set SD1 and SD2 to the 97.5MHz as well.
	 */
	writel(SD_97500KHZ, SD1CKCR);
	writel(SD_97500KHZ, SD2CKCR);

	return 0;
}

#define ETHERNET_PHY_RESET	185	/* GPIO 5 31 */

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Force ethernet PHY out of reset */
	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	mdelay(10);
	gpio_direction_output(ETHERNET_PHY_RESET, 1);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

/* KSZ8041NL/RNL */
#define PHY_CONTROL1		0x1E
#define PHY_LED_MODE		0xC0000
#define PHY_LED_MODE_ACK	0x4000
int board_phy_config(struct phy_device *phydev)
{
	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	ret &= ~PHY_LED_MODE;
	ret |= PHY_LED_MODE_ACK;
	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);

	return 0;
}

void reset_cpu(ulong addr)
{
	struct udevice *dev;
	const u8 pmic_bus = 2;
	const u8 pmic_addr = 0x58;
	u8 data;
	int ret;

	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	if (ret)
		hang();

	ret = dm_i2c_read(dev, 0x13, &data, 1);
	if (ret)
		hang();

	data |= BIT(1);

	ret = dm_i2c_write(dev, 0x13, &data, 1);
	if (ret)
		hang();
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	const u32 load_magic = 0xb33fc0de;

	/* Block environment access if loaded using JTAG */
	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	    (op != ENVOP_INIT))
		return ENVL_UNKNOWN;

	if (prio)
		return ENVL_UNKNOWN;

	return ENVL_SPI_FLASH;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
f4ec4522 NI	2	/*
	3	* board/renesas/lager/lager.c
	4	* This file is lager board support.
	5	*
	6	* Copyright (C) 2013 Renesas Electronics Corporation
	7	* Copyright (C) 2013 Nobuhiro Iwamatsu <[email protected]>
f4ec4522 NI	8	*/
	9
	10	#include <common.h>
9925f1db	11	#include <environment.h>
f4ec4522 NI	12	#include <malloc.h>
f4ec4522 NI	13	#include <netdev.h>
cf839572 NI	14	#include <dm.h>
cf839572 NI	15	#include <dm/platform_data/serial_sh.h>
f4ec4522 NI	16	#include <asm/processor.h>
	17	#include <asm/mach-types.h>
	18	#include <asm/io.h>
1221ce45	19	#include <linux/errno.h>
f4ec4522 NI	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/gpio.h>
	22	#include <asm/arch/rmobile.h>
44e1eebf	23	#include <asm/arch/rcar-mstp.h>
d7916b1d	24	#include <asm/arch/mmc.h>
acdfecbb	25	#include <asm/arch/sh_sdhi.h>
23565c6b	26	#include <miiphy.h>
b9986be0	27	#include <i2c.h>
d7916b1d	28	#include <mmc.h>
f4ec4522 NI	29	#include "qos.h"
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
2c2c6ba6	33	#define CLK2MHZ(clk) (clk / 1000 / 1000)
f4ec4522 NI	34	void s_init(void)
f4ec4522 NI	35	{
dc535e10 NI	36	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
dc535e10 NI	37	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
f4ec4522 NI	38
	39	/* Watchdog init */
	40	writel(0xA5A5A500, &rwdt->rwtcsra);
	41	writel(0xA5A5A500, &swdt->swtcsra);
	42
2c2c6ba6	43	/* CPU frequency setting. Set to 1.4GHz */
f212a8ab	44	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
d8659c6d	45	u32 stat = 0;
f212a8ab NI	46	u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
	47	<< PLL0_STC_BIT;
	48	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
d8659c6d NI	49
	50	do {
	51	stat = readl(PLLECR) & PLL0ST;
	52	} while (stat == 0x0);
f212a8ab	53	}
2c2c6ba6	54
f4ec4522 NI	55	/* QoS(Quality-of-Service) Init */
f4ec4522 NI	56	qos_init();
f4ec4522 NI	57	}
f4ec4522 NI	58
e6027e6f	59	#define TMU0_MSTP125 BIT(25)
23565c6b	60
e6027e6f MV	61	#define SD1CKCR 0xE6150078
	62	#define SD2CKCR 0xE615026C
	63	#define SD_97500KHZ 0x7
acdfecbb	64
f4ec4522 NI	65	int board_early_init_f(void)
f4ec4522 NI	66	{
f4ec4522	67	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
acdfecbb NI	68
	69	/*
	70	* SD0 clock is set to 97.5MHz by default.
e6027e6f	71	* Set SD1 and SD2 to the 97.5MHz as well.
acdfecbb	72	*/
e6027e6f MV	73	writel(SD_97500KHZ, SD1CKCR);
e6027e6f MV	74	writel(SD_97500KHZ, SD2CKCR);
23565c6b	75
f4ec4522 NI	76	return 0;
	77	}
	78
e6027e6f MV	79	#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
e6027e6f MV	80
f4ec4522 NI	81	int board_init(void)
f4ec4522 NI	82	{
f4ec4522	83	/* adress of boot parameters */
eeb266ab	84	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
f4ec4522	85
e6027e6f MV	86	/* Force ethernet PHY out of reset */
	87	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	88	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	89	mdelay(10);
	90	gpio_direction_output(ETHERNET_PHY_RESET, 1);
23565c6b NI	91
	92	return 0;
	93	}
	94
e6027e6f	95	int dram_init(void)
23565c6b	96	{
e6027e6f MV	97	if (fdtdec_setup_memory_size() != 0)
e6027e6f MV	98	return -EINVAL;
23565c6b	99
e6027e6f MV	100	return 0;
e6027e6f MV	101	}
23565c6b	102
e6027e6f MV	103	int dram_init_banksize(void)
	104	{
	105	fdtdec_setup_memory_banksize();
23565c6b	106
e6027e6f	107	return 0;
23565c6b NI	108	}
23565c6b NI	109
e6027e6f MV	110	/* KSZ8041NL/RNL */
	111	#define PHY_CONTROL1 0x1E
	112	#define PHY_LED_MODE 0xC0000
23565c6b NI	113	#define PHY_LED_MODE_ACK 0x4000
	114	int board_phy_config(struct phy_device *phydev)
	115	{
	116	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	117	ret &= ~PHY_LED_MODE;
	118	ret \|= PHY_LED_MODE_ACK;
	119	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
	120
f4ec4522 NI	121	return 0;
	122	}
	123
e6027e6f	124	void reset_cpu(ulong addr)
d7916b1d	125	{
e6027e6f MV	126	struct udevice *dev;
	127	const u8 pmic_bus = 2;
	128	const u8 pmic_addr = 0x58;
	129	u8 data;
	130	int ret;
acdfecbb	131
e6027e6f MV	132	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	133	if (ret)
	134	hang();
acdfecbb	135
e6027e6f	136	ret = dm_i2c_read(dev, 0x13, &data, 1);
acdfecbb	137	if (ret)
e6027e6f	138	hang();
acdfecbb	139
e6027e6f	140	data \|= BIT(1);
acdfecbb	141
e6027e6f MV	142	ret = dm_i2c_write(dev, 0x13, &data, 1);
	143	if (ret)
	144	hang();
d7916b1d NI	145	}
d7916b1d NI	146
e6027e6f	147	enum env_location env_get_location(enum env_operation op, int prio)
f4ec4522	148	{
e6027e6f	149	const u32 load_magic = 0xb33fc0de;
f4ec4522	150
e6027e6f MV	151	/* Block environment access if loaded using JTAG */
	152	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	153	(op != ENVOP_INIT))
	154	return ENVL_UNKNOWN;
f4ec4522	155
e6027e6f MV	156	if (prio)
e6027e6f MV	157	return ENVL_UNKNOWN;
b9986be0	158
e6027e6f	159	return ENVL_SPI_FLASH;
f4ec4522	160	}