[J-u-boot.git] / include / configs / axs101.h

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_AXS101_H_
#define _CONFIG_AXS101_H_

/*
 *  CPU configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ

/* NAND controller DMA doesn't work correctly with D$ enabled */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Board configuration
 */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */

#define CONFIG_ARCH_EARLY_INIT_R

#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
#define ARC_APB_PERIPHERAL_BASE		0xF0000000
#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)

/*
 * Memory configuration
 */
#define CONFIG_SYS_TEXT_BASE		0x81000000
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		0x20000000	/* 512 Mb */

#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
#define CONFIG_SYS_LOAD_ADDR		0x82000000

/*
 * NAND Flash configuration
 */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_NAND_BASE		(ARC_FPGA_PERIPHERAL_BASE + 0x16000)
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/*
 * UART configuration
 *
 * CONFIG_CONS_INDEX = 1 - Debug UART
 * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
 */
#define CONFIG_CONS_INDEX		4
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#if (CONFIG_CONS_INDEX == 1)
	/* Debug UART */
#	define CONFIG_SYS_NS16550_CLK		33333000
#else
	/* FPGA UARTs use different clock */
#	define CONFIG_SYS_NS16550_CLK		33333333
#endif
#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
#define CONFIG_SYS_NS16550_MEM32

#define CONFIG_BAUDRATE			115200
/*
 * I2C configuration
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS	2
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SLAVE		0
#define CONFIG_SYS_I2C_SLAVE1		0
#define CONFIG_SYS_I2C_SLAVE2		0
#define CONFIG_SYS_I2C_BASE		0xE001D000
#define CONFIG_SYS_I2C_BASE1		0xE001E000
#define CONFIG_SYS_I2C_BASE2		0xE001F000
#define CONFIG_SYS_I2C_BUS_MAX		3
#define IC_CLK				50

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	64

/*
 * SD/MMC configuration
 */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION

/*
 * Ethernet PHY configuration
 */
#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE

/*
 * Ethernet configuration
 */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_AUTONEG
#define CONFIG_NET_MULTI

/*
 * Command line configuration
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_RARP

#define CONFIG_OF_LIBFDT

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		16

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
#define CONFIG_ENV_OFFSET		0

/*
 * Environment configuration
 */
#define CONFIG_BOOTDELAY		3
#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR

/*
 * Console configuration
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"AXS# "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/*
 * Misc utility configuration
 */
#define CONFIG_BOUNCE_BUFFER

#endif /* _CONFIG_AXS101_H_ */
Commit	Line	Data
a7069ddf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_AXS101_H_
	8	#define _CONFIG_AXS101_H_
	9
	10	/*
	11	* CPU configuration
	12	*/
a7069ddf	13	#define CONFIG_SYS_CACHELINE_SIZE 32
a7069ddf AB	14	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
a7069ddf AB	15
0cdd7620	16	/* NAND controller DMA doesn't work correctly with D$ enabled */
a7069ddf AB	17	#define CONFIG_SYS_DCACHE_OFF
	18
	19	/*
	20	* Board configuration
	21	*/
	22	#define CONFIG_SYS_GENERIC_BOARD
	23	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
	24
	25	#define CONFIG_ARCH_EARLY_INIT_R
	26
	27	#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
	28	#define ARC_APB_PERIPHERAL_BASE 0xF0000000
	29	#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
	30	#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
	31
	32	/*
	33	* Memory configuration
	34	*/
	35	#define CONFIG_SYS_TEXT_BASE 0x81000000
	36	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	37
	38	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	39	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
0cdd7620	40	#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */
a7069ddf AB	41
	42	#define CONFIG_SYS_INIT_SP_ADDR \
	43	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
	44
	45	#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
	46	#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
	47	#define CONFIG_SYS_LOAD_ADDR 0x82000000
	48
	49	/*
	50	* NAND Flash configuration
	51	*/
	52	#define CONFIG_SYS_NO_FLASH
	53	#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
	54	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	55
	56	/*
	57	* UART configuration
	58	*
	59	* CONFIG_CONS_INDEX = 1 - Debug UART
	60	* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
	61	*/
	62	#define CONFIG_CONS_INDEX 4
	63	#define CONFIG_SYS_NS16550
	64	#define CONFIG_SYS_NS16550_SERIAL
	65	#define CONFIG_SYS_NS16550_REG_SIZE -4
	66	#if (CONFIG_CONS_INDEX == 1)
	67	/* Debug UART */
	68	# define CONFIG_SYS_NS16550_CLK 33333000
	69	#else
	70	/* FPGA UARTs use different clock */
	71	# define CONFIG_SYS_NS16550_CLK 33333333
	72	#endif
	73	#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
	74	#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
	75	#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
	76	#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
	77	#define CONFIG_SYS_NS16550_MEM32
	78
	79	#define CONFIG_BAUDRATE 115200
	80	/*
	81	* I2C configuration
	82	*/
678398b1 SR	83	#define CONFIG_SYS_I2C
678398b1 SR	84	#define CONFIG_SYS_I2C_DW
a7069ddf AB	85	#define CONFIG_I2C_ENV_EEPROM_BUS 2
a7069ddf AB	86	#define CONFIG_SYS_I2C_SPEED 100000
678398b1 SR	87	#define CONFIG_SYS_I2C_SPEED1 100000
678398b1 SR	88	#define CONFIG_SYS_I2C_SPEED2 100000
a7069ddf	89	#define CONFIG_SYS_I2C_SLAVE 0
678398b1 SR	90	#define CONFIG_SYS_I2C_SLAVE1 0
678398b1 SR	91	#define CONFIG_SYS_I2C_SLAVE2 0
a7069ddf AB	92	#define CONFIG_SYS_I2C_BASE 0xE001D000
	93	#define CONFIG_SYS_I2C_BASE1 0xE001E000
	94	#define CONFIG_SYS_I2C_BASE2 0xE001F000
	95	#define CONFIG_SYS_I2C_BUS_MAX 3
	96	#define IC_CLK 50
	97
	98	/*
	99	* EEPROM configuration
	100	*/
	101	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	102	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
	103	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	104	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
	105	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
6bfa4420	106	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
a7069ddf AB	107
	108	/*
	109	* SD/MMC configuration
	110	*/
	111	#define CONFIG_MMC
	112	#define CONFIG_GENERIC_MMC
	113	#define CONFIG_DWMMC
	114	#define CONFIG_DOS_PARTITION
	115
	116	/*
	117	* Ethernet PHY configuration
	118	*/
	119	#define CONFIG_PHYLIB
	120	#define CONFIG_MII
	121	#define CONFIG_PHY_GIGE
	122
	123	/*
	124	* Ethernet configuration
	125	*/
	126	#define CONFIG_DESIGNWARE_ETH
	127	#define CONFIG_DW_AUTONEG
a7069ddf AB	128	#define CONFIG_NET_MULTI
	129
	130	/*
	131	* Command line configuration
	132	*/
	133	#include <config_cmd_default.h>
	134
	135	#define CONFIG_CMD_DHCP
	136	#define CONFIG_CMD_EEPROM
	137	#define CONFIG_CMD_ELF
	138	#define CONFIG_CMD_FAT
	139	#define CONFIG_CMD_I2C
	140	#define CONFIG_CMD_MMC
	141	#define CONFIG_CMD_NAND
	142	#define CONFIG_CMD_PING
	143	#define CONFIG_CMD_RARP
	144
	145	#define CONFIG_OF_LIBFDT
	146
	147	#define CONFIG_AUTO_COMPLETE
	148	#define CONFIG_SYS_MAXARGS 16
	149
	150	/*
	151	* Environment settings
	152	*/
	153	#define CONFIG_ENV_IS_IN_EEPROM
	154	#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
	155	#define CONFIG_ENV_OFFSET 0
	156
	157	/*
	158	* Environment configuration
	159	*/
	160	#define CONFIG_BOOTDELAY 3
	161	#define CONFIG_BOOTFILE "uImage"
	162	#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
	163	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
	164
	165	/*
	166	* Console configuration
	167	*/
	168	#define CONFIG_SYS_LONGHELP
c42eb7f2	169	#define CONFIG_SYS_PROMPT "AXS# "
a7069ddf AB	170	#define CONFIG_SYS_CBSIZE 256
	171	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	172	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	173	sizeof(CONFIG_SYS_PROMPT) + 16)
	174
	175	/*
	176	* Misc utility configuration
	177	*/
	178	#define CONFIG_BOUNCE_BUFFER
	179
	180	#endif /* _CONFIG_AXS101_H_ */