projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f4158203 T |
1 | CONFIG_PPC=y |
| 2 | CONFIG_TEXT_BASE=0x11000000 | |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x1000 | |
| b182816c TR |
4 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 5 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
| 6 | CONFIG_NR_DRAM_BANKS=5 | |
| 7 | CONFIG_ENV_SIZE=0x2000 | |
| 8 | CONFIG_ENV_SECT_SIZE=0x20000 | |
| f4158203 T |
9 | CONFIG_SYS_MONITOR_LEN=1048576 |
| 10 | CONFIG_SPL_MMC=y | |
| b182816c | 11 | CONFIG_SPL_SERIAL=y |
| 867e16ae | 12 | CONFIG_SPL_TEXT_BASE=0xf8f80000 |
| d8927020 | 13 | CONFIG_SYS_LOAD_ADDR=0x1000000 |
| f4158203 | 14 | CONFIG_SPL=y |
| b182816c TR |
15 | CONFIG_DEBUG_UART_BASE=0xffe04500 |
| 16 | CONFIG_DEBUG_UART_CLOCK=37500000 | |
| b182816c | 17 | CONFIG_ENV_ADDR=0xeff20000 |
| f4158203 T |
18 | CONFIG_MPC85xx=y |
| 19 | CONFIG_SYS_INIT_RAM_LOCK=y | |
| 20 | CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR=y | |
| 21 | CONFIG_TARGET_TURRIS_1X=y | |
| 22 | CONFIG_SYS_CCSRBAR_DEFAULT=0xffe00000 | |
| 23 | CONFIG_L2_CACHE=y | |
| 24 | CONFIG_ENABLE_36BIT_PHYS=y | |
| 25 | CONFIG_SYS_MPC85XX_NO_RESETVEC=y | |
| 26 | CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y | |
| 27 | CONFIG_DEBUG_UART=y | |
| 28 | CONFIG_AHCI=y | |
| b182816c | 29 | CONFIG_OF_BOARD_FIXUP=y |
| f4158203 T |
30 | CONFIG_PCIE1=y |
| 31 | CONFIG_PCIE2=y | |
| 32 | CONFIG_PCIE3=y | |
| 33 | CONFIG_HAS_BOARD_SIZE_LIMIT=y | |
| 34 | CONFIG_BOARD_SIZE_LIMIT=1048576 | |
| 35 | CONFIG_MP=y | |
| 36 | CONFIG_FIT=y | |
| 37 | CONFIG_FIT_VERBOSE=y | |
| 38 | CONFIG_DISTRO_DEFAULTS=y | |
| 39 | CONFIG_BOOTDELAY=3 | |
| 40 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
| 41 | CONFIG_USE_PREBOOT=y | |
| b182816c TR |
42 | CONFIG_PCI_INIT_R=y |
| 43 | # CONFIG_SPL_FRAMEWORK is not set | |
| f4158203 T |
44 | CONFIG_SPL_MAX_SIZE=0x80200 |
| 45 | CONFIG_SPL_PAD_TO=0x0 | |
| 46 | CONFIG_SPL_MMC_BOOT=y | |
| 47 | CONFIG_SPL_GD_ADDR=0xf8f9c000 | |
| 48 | CONFIG_SPL_RELOC_STACK=0xf8f9d000 | |
| 49 | CONFIG_SPL_RELOC_MALLOC=y | |
| 50 | CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 | |
| 51 | CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 | |
| b182816c TR |
52 | CONFIG_SPL_ENV_SUPPORT=y |
| 53 | CONFIG_SPL_I2C=y | |
| 54 | CONFIG_SPL_MPC8XXX_INIT_DDR=y | |
| f4158203 T |
55 | CONFIG_SPL_TARGET="u-boot-with-spl.bin" |
| 56 | CONFIG_CMD_BOOTZ=y | |
| 57 | CONFIG_CMD_IMLS=y | |
| 58 | CONFIG_CMD_MEMTEST=y | |
| 59 | CONFIG_CMD_SHA1SUM=y | |
| 60 | CONFIG_CMD_LZMADEC=y | |
| 61 | CONFIG_CMD_UNLZ4=y | |
| 62 | CONFIG_CMD_UNZIP=y | |
| 63 | CONFIG_CMD_DM=y | |
| 64 | CONFIG_CMD_GPIO=y | |
| 65 | CONFIG_CMD_GPT=y | |
| 66 | CONFIG_CMD_I2C=y | |
| 67 | CONFIG_SYS_LOADS_BAUD_CHANGE=y | |
| 68 | CONFIG_CMD_LSBLK=y | |
| 69 | CONFIG_CMD_MMC=y | |
| 70 | CONFIG_CMD_MTD=y | |
| 71 | CONFIG_CMD_PCI=y | |
| 72 | CONFIG_CMD_SPI=y | |
| 73 | CONFIG_CMD_USB=y | |
| 74 | CONFIG_CMD_WDT=y | |
| 75 | CONFIG_CMD_TFTPPUT=y | |
| 76 | CONFIG_CMD_NFS=y | |
| 77 | CONFIG_CMD_CACHE=y | |
| 78 | CONFIG_CMD_TIME=y | |
| 79 | CONFIG_CMD_BTRFS=y | |
| 80 | CONFIG_CMD_EXT4_WRITE=y | |
| 81 | CONFIG_CMD_SQUASHFS=y | |
| 82 | CONFIG_CMD_FS_UUID=y | |
| 83 | CONFIG_CMD_UBI=y | |
| 84 | CONFIG_OF_CONTROL=y | |
| b182816c TR |
85 | CONFIG_ENV_OVERWRITE=y |
| 86 | CONFIG_ENV_IS_IN_FLASH=y | |
| 87 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| f4158203 T |
88 | CONFIG_USE_ETHPRIME=y |
| 89 | CONFIG_ETHPRIME="eth2" | |
| 90 | CONFIG_NETCONSOLE=y | |
| 91 | CONFIG_SCSI_AHCI=y | |
| 92 | CONFIG_AHCI_PCI=y | |
| 93 | CONFIG_LBA48=y | |
| 94 | CONFIG_SYS_64BIT_LBA=y | |
| b182816c | 95 | CONFIG_DDR_CLK_FREQ=66666666 |
| f4158203 T |
96 | CONFIG_CHIP_SELECTS_PER_CTRL=2 |
| 97 | CONFIG_SYS_BR0_PRELIM_BOOL=y | |
| 98 | CONFIG_SYS_BR0_PRELIM=0xef001001 | |
| 99 | CONFIG_SYS_OR0_PRELIM=0xff000ff7 | |
| 100 | CONFIG_SYS_BR1_PRELIM_BOOL=y | |
| 101 | CONFIG_SYS_BR1_PRELIM=0xff800821 | |
| 102 | CONFIG_SYS_OR1_PRELIM=0xfffc0796 | |
| 103 | CONFIG_SYS_BR3_PRELIM_BOOL=y | |
| 104 | CONFIG_SYS_BR3_PRELIM=0xffa00801 | |
| 105 | CONFIG_SYS_OR3_PRELIM=0xfffe09f7 | |
| 106 | CONFIG_DM_PCA953X=y | |
| b182816c | 107 | CONFIG_MPC8XXX_GPIO=y |
| f4158203 | 108 | CONFIG_DM_I2C=y |
| b182816c TR |
109 | CONFIG_SPL_SYS_I2C_LEGACY=y |
| 110 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y | |
| 111 | CONFIG_SYS_I2C_FSL=y | |
| 112 | CONFIG_SYS_FSL_I2C_OFFSET=0x3000 | |
| 113 | CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y | |
| 114 | CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 | |
| 115 | CONFIG_MISC=y | |
| 116 | CONFIG_ATSHA204A=y | |
| f4158203 | 117 | CONFIG_SYS_I2C_EEPROM_ADDR=0x52 |
| b182816c | 118 | CONFIG_FSL_ESDHC=y |
| f4158203 T |
119 | CONFIG_MTD=y |
| 120 | CONFIG_DM_MTD=y | |
| b182816c TR |
121 | CONFIG_MTD_NOR_FLASH=y |
| 122 | CONFIG_CFI_FLASH=y | |
| 123 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
| f4158203 | 124 | CONFIG_SYS_FLASH_EMPTY_INFO=y |
| b182816c TR |
125 | CONFIG_FLASH_CFI_MTD=y |
| 126 | CONFIG_SYS_FLASH_CFI=y | |
| f4158203 T |
127 | CONFIG_SYS_FLASH_QUIET_TEST=y |
| 128 | CONFIG_SYS_MAX_FLASH_SECT=128 | |
| b182816c TR |
129 | CONFIG_MTD_RAW_NAND=y |
| 130 | CONFIG_NAND_FSL_ELBC=y | |
| 131 | CONFIG_NAND_FSL_ELBC_DT=y | |
| 132 | CONFIG_PHY_FIXED=y | |
| f4158203 | 133 | CONFIG_DM_MDIO=y |
| b182816c TR |
134 | CONFIG_MII=y |
| 135 | CONFIG_TSEC_ENET=y | |
| f4158203 | 136 | CONFIG_NVME_PCI=y |
| b182816c | 137 | CONFIG_PCIE_FSL=y |
| f4158203 T |
138 | CONFIG_DM_RTC=y |
| 139 | CONFIG_RTC_DS1307=y | |
| 140 | CONFIG_SCSI=y | |
| 141 | CONFIG_DM_SERIAL=y | |
| 142 | CONFIG_SPL_SYS_NS16550_SERIAL=y | |
| 143 | CONFIG_SPI=y | |
| 144 | CONFIG_DM_SPI=y | |
| 145 | CONFIG_FSL_ESPI=y | |
| 146 | CONFIG_USB=y | |
| b182816c TR |
147 | CONFIG_USB_XHCI_HCD=y |
| 148 | CONFIG_USB_XHCI_PCI=y | |
| 149 | CONFIG_USB_EHCI_FSL=y | |
| f4158203 | 150 | CONFIG_WDT=y |
| b182816c | 151 | CONFIG_WDT_MAX6370=y |
| f4158203 | 152 | CONFIG_FAT_WRITE=y |
| b182816c | 153 | CONFIG_BCH=y |