projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a36d8672 MS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* | |
| 3 | * (C) Copyright 2022 Advanced Micro Devices, Inc | |
| 4 | * Michal Simek <[email protected]> | |
| 5 | * | |
| 6 | * (C) Copyright 2007 Michal Simek | |
| 7 | * Michal SIMEK <[email protected]> | |
| 8 | */ | |
| 9 | ||
| a36d8672 MS |
10 | #include <dm.h> |
| 11 | #include <timer.h> | |
| 12 | #include <regmap.h> | |
| 13 | #include <dm/device_compat.h> | |
| 14 | ||
| 15 | #define TIMER_ENABLE_ALL 0x400 /* ENALL */ | |
| 16 | #define TIMER_PWM 0x200 /* PWMA0 */ | |
| 17 | #define TIMER_INTERRUPT 0x100 /* T0INT */ | |
| 18 | #define TIMER_ENABLE 0x080 /* ENT0 */ | |
| 19 | #define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ | |
| 20 | #define TIMER_RESET 0x020 /* LOAD0 */ | |
| 21 | #define TIMER_RELOAD 0x010 /* ARHT0 */ | |
| 22 | #define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ | |
| 23 | #define TIMER_EXT_COMPARE 0x004 /* GENT0 */ | |
| 24 | #define TIMER_DOWN_COUNT 0x002 /* UDT0 */ | |
| 25 | #define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ | |
| 26 | ||
| 27 | #define TIMER_CONTROL_OFFSET 0 | |
| 28 | #define TIMER_LOADREG_OFFSET 4 | |
| 29 | #define TIMER_COUNTER_OFFSET 8 | |
| 30 | ||
| 31 | struct xilinx_timer_priv { | |
| 32 | struct regmap *regs; | |
| 33 | }; | |
| 34 | ||
| 35 | static u64 xilinx_timer_get_count(struct udevice *dev) | |
| 36 | { | |
| 37 | struct xilinx_timer_priv *priv = dev_get_priv(dev); | |
| 38 | u32 value; | |
| 39 | ||
| 40 | regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value); | |
| 41 | ||
| b34bc22b | 42 | return timer_conv_64(value); |
| a36d8672 MS |
43 | } |
| 44 | ||
| 45 | static int xilinx_timer_probe(struct udevice *dev) | |
| 46 | { | |
| 47 | struct xilinx_timer_priv *priv = dev_get_priv(dev); | |
| 48 | int ret; | |
| 49 | ||
| 50 | /* uc_priv->clock_rate has already clock rate */ | |
| 51 | ret = regmap_init_mem(dev_ofnode(dev), &priv->regs); | |
| 52 | if (ret) { | |
| 53 | dev_dbg(dev, "failed to get regbase of timer\n"); | |
| 54 | return ret; | |
| 55 | } | |
| 56 | ||
| 57 | regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0); | |
| 58 | regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET); | |
| 59 | regmap_write(priv->regs, TIMER_CONTROL_OFFSET, | |
| 60 | TIMER_ENABLE | TIMER_RELOAD); | |
| 61 | ||
| 62 | return 0; | |
| 63 | } | |
| 64 | ||
| 65 | static const struct timer_ops xilinx_timer_ops = { | |
| 66 | .get_count = xilinx_timer_get_count, | |
| 67 | }; | |
| 68 | ||
| 69 | static const struct udevice_id xilinx_timer_ids[] = { | |
| 70 | { .compatible = "xlnx,xps-timer-1.00.a" }, | |
| 71 | {} | |
| 72 | }; | |
| 73 | ||
| 74 | U_BOOT_DRIVER(xilinx_timer) = { | |
| 75 | .name = "xilinx_timer", | |
| 76 | .id = UCLASS_TIMER, | |
| 77 | .of_match = xilinx_timer_ids, | |
| 78 | .priv_auto = sizeof(struct xilinx_timer_priv), | |
| 79 | .probe = xilinx_timer_probe, | |
| 80 | .ops = &xilinx_timer_ops, | |
| 81 | }; |