[J-u-boot.git] / include / configs / ls2080aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017, 2019-2021 NXP
 * Copyright 2015 Freescale Semiconductor
 */

#ifndef __LS2_QDS_H
#define __LS2_QDS_H

#include "ls2080a_common.h"

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
#endif

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk()/4)

#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_QSPI		0x0f
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x107
#define QIXIS_RCW_SRC_SD		0x40
#define QIXIS_RCW_SRC_QSPI		0x62
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
#endif
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

/*
 * I2C
 */
#define I2C_MUX_PCA_ADDR		0x77
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */

/*
 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 */
#define FSL_QIXIS_BRDCFG9_QSPI		0x1

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=esbc_validate 0x580640000;"  \
	"esbc_validate 0x580680000;"            \
	"fsl_mc start mc 0x580a00000"           \
	" 0x580e00000 \0"
#else
#ifdef CONFIG_TFABOOT
#define SD_MC_INIT_CMD				\
	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD				\
	"fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x80100000\0"                 \
	"loadaddr_sd=0x90100000\0"                 \
	"kernel_addr=0x581000000\0"		          \
	"kernel_addr_sd=0x8000\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x581000000\0"            \
	"kernel_start_sd=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x2800000\0"               \
	"kernel_size_sd=0x14000\0"               \
	"load_addr=0xa0000000\0"		            \
	"kernelheader_addr=0x580600000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernelheader_size=0x40000\0"		\
	"BOARD=ls2088aqds\0" \
	"mcmemsize=0x70000000 \0" \
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	IFC_MC_INIT_CMD				\
	BOOTENV					\
	"boot_scripts=ls2088aqds_boot.scr\0"	\
	"boot_script_hdr=hdr_ls2088aqds_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"nor_bootcmd=echo Trying load from nor..;"		\
		"cp.b $kernel_addr $load_addr "			\
		"$kernel_size ; env exists secureboot && "	\
		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$BOARD\0"	\
	"sd_bootcmd=echo Trying load from SD ..;" \
	"mmcinfo; mmc read $load_addr "		\
	"$kernel_addr_sd $kernel_size_sd && "	\
	"bootm $load_addr#$BOARD\0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x90100000\0"                 \
	"kernel_addr=0x800\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x14000\0"               \
	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"       \
	"mcmemsize=0x70000000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_NXP_ESBC */

#ifdef CONFIG_TFABOOT
#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#define SD_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
			"&& esbc_validate $load_addr; "			\
			"env exists mcinitcmd && run mcinitcmd "	\
			"&& mmc read 0x80d00000 0x6800 0x800 "		\
			"&& fsl_mc lazyapply dpl 0x80d00000; "		\
			"run distro_bootcmd;run sd_bootcmd; "		\
			"env exists secureboot && esbc_halt;"

#define IFC_NOR_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
			"run distro_bootcmd;run nor_bootcmd; "		\
			"env exists secureboot && esbc_halt;"
#endif

#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_FSL_MEMAC
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_QDS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
7288c2c2	2	/*
34f39ce8	3	* Copyright 2017, 2019-2021 NXP
7288c2c2	4	* Copyright 2015 Freescale Semiconductor
7288c2c2 YS	5	*/
	6
	7	#ifndef __LS2_QDS_H
	8	#define __LS2_QDS_H
	9
44937214	10	#include "ls2080a_common.h"
7288c2c2	11
8c77ef85	12	#ifdef CONFIG_FSL_QSPI
8c77ef85 YY	13	#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
	14	#endif
	15
	16	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
2f8a6db5	17	#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
7288c2c2	18
7288c2c2 YS	19	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	20	#define SPD_EEPROM_ADDRESS1 0x51
	21	#define SPD_EEPROM_ADDRESS2 0x52
	22	#define SPD_EEPROM_ADDRESS3 0x53
	23	#define SPD_EEPROM_ADDRESS4 0x54
	24	#define SPD_EEPROM_ADDRESS5 0x55
	25	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	26	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
7288c2c2	27
7288c2c2 YS	28	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	29	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	30	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	31
	32	#define CONFIG_SYS_NOR0_CSPR \
	33	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	34	CSPR_PORT_SIZE_16 \| \
	35	CSPR_MSEL_NOR \| \
	36	CSPR_V)
	37	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	38	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	39	CSPR_PORT_SIZE_16 \| \
	40	CSPR_MSEL_NOR \| \
	41	CSPR_V)
	42	#define CONFIG_SYS_NOR1_CSPR \
	43	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	44	CSPR_PORT_SIZE_16 \| \
	45	CSPR_MSEL_NOR \| \
	46	CSPR_V)
	47	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	48	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	49	CSPR_PORT_SIZE_16 \| \
	50	CSPR_MSEL_NOR \| \
	51	CSPR_V)
	52	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	53	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	54	FTIM0_NOR_TEADC(0x5) \| \
	55	FTIM0_NOR_TEAHC(0x5))
	56	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	57	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	58	FTIM1_NOR_TSEQRAD_NOR(0x13))
	59	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	60	FTIM2_NOR_TCH(0x4) \| \
	61	FTIM2_NOR_TWPH(0x0E) \| \
	62	FTIM2_NOR_TWP(0x1c))
	63	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	64	#define CONFIG_SYS_IFC_CCR 0x01000000
	65
e856bdcf	66	#ifdef CONFIG_MTD_NOR_FLASH
7288c2c2 YS	67	#define CONFIG_SYS_FLASH_QUIET_TEST
	68	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	69
7288c2c2 YS	70	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	71	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	72	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	73
	74	#define CONFIG_SYS_FLASH_EMPTY_INFO
	75	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	76	CONFIG_SYS_FLASH_BASE + 0x40000000}
	77	#endif
	78
7288c2c2 YS	79	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	80	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	81
7288c2c2 YS	82	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	83	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	84	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	85	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	86	\| CSPR_V)
	87	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	88
	89	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	90	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	91	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	92	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	93	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	94	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	95	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	96
7288c2c2 YS	97	/* ONFI NAND Flash mode0 Timing Params */
	98	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	99	FTIM0_NAND_TWP(0x18) \| \
	100	FTIM0_NAND_TWCHT(0x07) \| \
	101	FTIM0_NAND_TWH(0x0a))
	102	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	103	FTIM1_NAND_TWBE(0x39) \| \
	104	FTIM1_NAND_TRR(0x0e) \| \
	105	FTIM1_NAND_TRP(0x18))
	106	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	107	FTIM2_NAND_TREH(0x0a) \| \
	108	FTIM2_NAND_TWHRE(0x1e))
	109	#define CONFIG_SYS_NAND_FTIM3 0x0
	110
	111	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	112	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	113	#define CONFIG_MTD_NAND_VERIFY_WRITE
7288c2c2	114
7288c2c2 YS	115	#define QIXIS_LBMAP_SWITCH 0x06
	116	#define QIXIS_LBMAP_MASK 0x0f
	117	#define QIXIS_LBMAP_SHIFT 0
	118	#define QIXIS_LBMAP_DFLTBANK 0x00
	119	#define QIXIS_LBMAP_ALTBANK 0x04
b2d5ac59	120	#define QIXIS_LBMAP_NAND 0x09
1f55a938	121	#define QIXIS_LBMAP_SD 0x00
a646f669	122	#define QIXIS_LBMAP_QSPI 0x0f
7288c2c2 YS	123	#define QIXIS_RST_CTL_RESET 0x31
	124	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	125	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	126	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
b2d5ac59	127	#define QIXIS_RCW_SRC_NAND 0x107
1f55a938	128	#define QIXIS_RCW_SRC_SD 0x40
a646f669	129	#define QIXIS_RCW_SRC_QSPI 0x62
7288c2c2 YS	130	#define QIXIS_RST_FORCE_MEM 0x01
	131
	132	#define CONFIG_SYS_CSPR3_EXT (0x0)
	133	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	134	\| CSPR_PORT_SIZE_8 \
	135	\| CSPR_MSEL_GPCM \
	136	\| CSPR_V)
	137	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	138	\| CSPR_PORT_SIZE_8 \
	139	\| CSPR_MSEL_GPCM \
	140	\| CSPR_V)
	141
	142	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	143	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	144	/* QIXIS Timing parameters for IFC CS3 */
	145	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	146	FTIM0_GPCM_TEADC(0x0e) \| \
	147	FTIM0_GPCM_TEAHC(0x0e))
	148	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	149	FTIM1_GPCM_TRAD(0x3f))
	150	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	151	FTIM2_GPCM_TCH(0xf) \| \
	152	FTIM2_GPCM_TWP(0x3E))
	153	#define CONFIG_SYS_CS3_FTIM3 0x0
	154
faed6bde SK	155	#if defined(CONFIG_SPL)
faed6bde SK	156	#if defined(CONFIG_NAND_BOOT)
b2d5ac59 SW	157	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	158	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
	159	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
	160	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	161	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	162	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	163	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	164	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	165	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	166	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	167	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
	168	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
	169	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
	170	#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
	171	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	172	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	173	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	174	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	175	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	176	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	177	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	178	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	179	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	180	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	181	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	182	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	183	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	184
74cac00c	185	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
faed6bde	186	#endif
b2d5ac59	187	#else
7288c2c2 YS	188	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	189	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	190	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	191	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	192	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	193	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	194	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	195	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	196	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	197	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	198	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	199	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	200	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	201	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	202	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	203	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	204	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	205	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	206	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	207	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	208	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	209	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	210	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	211	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	212	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	213	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	214	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
a646f669	215	#endif
b2d5ac59	216
7288c2c2 YS	217	/* Debug Server firmware */
	218	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	219	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
	220
7288c2c2 YS	221	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
	222
	223	/*
	224	* I2C
	225	*/
	226	#define I2C_MUX_PCA_ADDR 0x77
	227	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
	228
	229	/* I2C bus multiplexer */
	230	#define I2C_MUX_CH_DEFAULT 0x8
	231
b7774b05	232	/* SPI */
b718d371	233
453418f2 YY	234	/*
	235	* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
	236	* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
	237	* If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
	238	*/
	239	#define FSL_QIXIS_BRDCFG9_QSPI 0x1
b718d371	240
7288c2c2 YS	241	/*
	242	* RTC configuration
	243	*/
	244	#define RTC
	245	#define CONFIG_RTC_DS3231 1
	246	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	247
	248	/* EEPROM */
7288c2c2 YS	249	#define CONFIG_SYS_I2C_EEPROM_NXID
7288c2c2 YS	250	#define CONFIG_SYS_EEPROM_BUS_NUM 0
7288c2c2	251
7288c2c2	252	#define CONFIG_FSL_MEMAC
7288c2c2 YS	253
7288c2c2 YS	254	#ifdef CONFIG_PCI
7288c2c2	255	#define CONFIG_PCI_SCAN_SHOW
7288c2c2 YS	256	#endif
7288c2c2 YS	257
7288c2c2 YS	258	/* Initial environment variables */
7288c2c2 YS	259	#undef CONFIG_EXTRA_ENV_SETTINGS
5536c3c9	260	#ifdef CONFIG_NXP_ESBC
7288c2c2 YS	261	#define CONFIG_EXTRA_ENV_SETTINGS \
	262	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	263	"loadaddr=0x80100000\0" \
	264	"kernel_addr=0x100000\0" \
	265	"ramdisk_addr=0x800000\0" \
	266	"ramdisk_size=0x2000000\0" \
	267	"fdt_high=0xa0000000\0" \
	268	"initrd_high=0xffffffffffffffff\0" \
7676074a	269	"kernel_start=0x581000000\0" \
7288c2c2	270	"kernel_load=0xa0000000\0" \
16ed8560	271	"kernel_size=0x2800000\0" \
6d7b9e78	272	"mcmemsize=0x40000000\0" \
8526a58a PS	273	"mcinitcmd=esbc_validate 0x580640000;" \
8526a58a PS	274	"esbc_validate 0x580680000;" \
7676074a UA	275	"fsl_mc start mc 0x580a00000" \
7676074a UA	276	" 0x580e00000 \0"
1908201c RB	277	#else
	278	#ifdef CONFIG_TFABOOT
	279	#define SD_MC_INIT_CMD \
f1898997	280	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
c3d141e0 WK	281	"mmc read 0x80e00000 0x7000 0x800;" \
c3d141e0 WK	282	"fsl_mc start mc 0x80a00000 0x80e00000\0"
1908201c RB	283	#define IFC_MC_INIT_CMD \
	284	"fsl_mc start mc 0x580a00000" \
	285	" 0x580e00000 \0"
	286	#define CONFIG_EXTRA_ENV_SETTINGS \
	287	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	288	"loadaddr=0x80100000\0" \
	289	"loadaddr_sd=0x90100000\0" \
d7a4ddd3 WK	290	"kernel_addr=0x581000000\0" \
d7a4ddd3 WK	291	"kernel_addr_sd=0x8000\0" \
1908201c RB	292	"ramdisk_addr=0x800000\0" \
	293	"ramdisk_size=0x2000000\0" \
	294	"fdt_high=0xa0000000\0" \
	295	"initrd_high=0xffffffffffffffff\0" \
	296	"kernel_start=0x581000000\0" \
	297	"kernel_start_sd=0x8000\0" \
	298	"kernel_load=0xa0000000\0" \
	299	"kernel_size=0x2800000\0" \
	300	"kernel_size_sd=0x14000\0" \
d7a4ddd3	301	"load_addr=0xa0000000\0" \
8526a58a	302	"kernelheader_addr=0x580600000\0" \
d7a4ddd3 WK	303	"kernelheader_addr_r=0x80200000\0" \
	304	"kernelheader_size=0x40000\0" \
	305	"BOARD=ls2088aqds\0" \
	306	"mcmemsize=0x70000000 \0" \
1a9ce6e0 BL	307	"scriptaddr=0x80000000\0" \
1a9ce6e0 BL	308	"scripthdraddr=0x80080000\0" \
d7a4ddd3	309	IFC_MC_INIT_CMD \
1a9ce6e0 BL	310	BOOTENV \
	311	"boot_scripts=ls2088aqds_boot.scr\0" \
	312	"boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
	313	"scan_dev_for_boot_part=" \
	314	"part list ${devtype} ${devnum} devplist; " \
	315	"env exists devplist \|\| setenv devplist 1; " \
	316	"for distro_bootpart in ${devplist}; do " \
	317	"if fstype ${devtype} " \
	318	"${devnum}:${distro_bootpart} " \
	319	"bootfstype; then " \
	320	"run scan_dev_for_boot; " \
	321	"fi; " \
	322	"done\0" \
	323	"boot_a_script=" \
	324	"load ${devtype} ${devnum}:${distro_bootpart} " \
	325	"${scriptaddr} ${prefix}${script}; " \
	326	"env exists secureboot && load ${devtype} " \
	327	"${devnum}:${distro_bootpart} " \
	328	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	329	"&& esbc_validate ${scripthdraddr};" \
	330	"source ${scriptaddr}\0" \
d7a4ddd3 WK	331	"nor_bootcmd=echo Trying load from nor..;" \
	332	"cp.b $kernel_addr $load_addr " \
	333	"$kernel_size ; env exists secureboot && " \
	334	"cp.b $kernelheader_addr $kernelheader_addr_r " \
	335	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	336	"bootm $load_addr#$BOARD\0" \
	337	"sd_bootcmd=echo Trying load from SD ..;" \
	338	"mmcinfo; mmc read $load_addr " \
	339	"$kernel_addr_sd $kernel_size_sd && " \
	340	"bootm $load_addr#$BOARD\0"
1f55a938 SK	341	#elif defined(CONFIG_SD_BOOT)
	342	#define CONFIG_EXTRA_ENV_SETTINGS \
	343	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	344	"loadaddr=0x90100000\0" \
	345	"kernel_addr=0x800\0" \
	346	"ramdisk_addr=0x800000\0" \
	347	"ramdisk_size=0x2000000\0" \
	348	"fdt_high=0xa0000000\0" \
	349	"initrd_high=0xffffffffffffffff\0" \
	350	"kernel_start=0x8000\0" \
	351	"kernel_load=0xa0000000\0" \
	352	"kernel_size=0x14000\0" \
f1898997 PJ	353	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
	354	"mmc read 0x80e00000 0x7000 0x800;" \
	355	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
1f55a938	356	"mcmemsize=0x70000000 \0"
9ed44787 UA	357	#else
	358	#define CONFIG_EXTRA_ENV_SETTINGS \
	359	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	360	"loadaddr=0x80100000\0" \
	361	"kernel_addr=0x100000\0" \
	362	"ramdisk_addr=0x800000\0" \
	363	"ramdisk_size=0x2000000\0" \
	364	"fdt_high=0xa0000000\0" \
	365	"initrd_high=0xffffffffffffffff\0" \
f5bf23d8	366	"kernel_start=0x581000000\0" \
9ed44787 UA	367	"kernel_load=0xa0000000\0" \
9ed44787 UA	368	"kernel_size=0x2800000\0" \
6d7b9e78	369	"mcmemsize=0x40000000\0" \
f5bf23d8 SK	370	"mcinitcmd=fsl_mc start mc 0x580a00000" \
f5bf23d8 SK	371	" 0x580e00000 \0"
1908201c	372	#endif /* CONFIG_TFABOOT */
5536c3c9	373	#endif /* CONFIG_NXP_ESBC */
9ed44787	374
d7a4ddd3	375	#ifdef CONFIG_TFABOOT
1a9ce6e0 BL	376	#define BOOT_TARGET_DEVICES(func) \
	377	func(USB, usb, 0) \
	378	func(MMC, mmc, 0) \
	379	func(SCSI, scsi, 0) \
	380	func(DHCP, dhcp, na)
	381	#include <config_distro_bootcmd.h>
	382
d7a4ddd3 WK	383	#define SD_BOOTCOMMAND \
d7a4ddd3 WK	384	"env exists mcinitcmd && env exists secureboot "\
8526a58a	385	"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
d7a4ddd3 WK	386	"&& esbc_validate $load_addr; " \
d7a4ddd3 WK	387	"env exists mcinitcmd && run mcinitcmd " \
c3d141e0 WK	388	"&& mmc read 0x80d00000 0x6800 0x800 " \
c3d141e0 WK	389	"&& fsl_mc lazyapply dpl 0x80d00000; " \
1a9ce6e0	390	"run distro_bootcmd;run sd_bootcmd; " \
d7a4ddd3 WK	391	"env exists secureboot && esbc_halt;"
	392
	393	#define IFC_NOR_BOOTCOMMAND \
	394	"env exists mcinitcmd && env exists secureboot "\
8526a58a	395	"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
d7a4ddd3	396	"&& fsl_mc lazyapply dpl 0x580d00000;" \
1a9ce6e0	397	"run distro_bootcmd;run nor_bootcmd; " \
d7a4ddd3 WK	398	"env exists secureboot && esbc_halt;"
	399	#endif
	400
910feb50	401	#if defined(CONFIG_FSL_MC_ENET)
e60476a0	402	#define CONFIG_FSL_MEMAC
e60476a0 PK	403	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	404	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	405	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	406	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	407
cf7ee6c4 PK	408	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	409	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	410	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	411	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	412	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	413	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	414	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	415	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	416	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	417	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	418	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	419	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	420	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	421	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	422	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	423	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	424
e60476a0 PK	425	#endif
e60476a0 PK	426
fcfdb6d5 SJ	427	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	428
7288c2c2	429	#endif /* __LS2_QDS_H */