[J-u-boot.git] / include / configs / ls1088aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017, 2020-2021 NXP
 */

#ifndef __LS1088A_QDS_H
#define __LS1088A_QDS_H

#include "ls1088a_common.h"

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define SYS_NO_FLASH
#endif

#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk()/4)

#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#define SPD_EEPROM_ADDRESS		0x51


/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TAVDS(0x6) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) | \
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x8) | \
				FTIM2_NOR_TCH(0x8) | \
				FTIM2_NOR_TWPH(0xe) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef SYS_NO_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
#endif

#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_QMAP_MASK			0xe0
#define QIXIS_QMAP_SHIFT		5
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x0e
#define QIXIS_LBMAP_ALTBANK		0x2e
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_EMMC		0x00
#define QIXIS_LBMAP_IFC			0x00
#define QIXIS_LBMAP_SD_QSPI		0x0e
#define QIXIS_LBMAP_QSPI		0x0e
#define QIXIS_RCW_SRC_IFC		0x25
#define QIXIS_RCW_SRC_SD		0x40
#define QIXIS_RCW_SRC_EMMC		0x41
#define QIXIS_RCW_SRC_QSPI		0x62
#define QIXIS_RST_CTL_RESET		0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define	QIXIS_RST_FORCE_MEM		0x01
#define QIXIS_STAT_PRES1		0xb
#define QIXIS_SDID_MASK			0x07
#define QIXIS_ESDHC_NO_ADAPTER		0x7

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
					| CSPR_PORT_SIZE_8 \
					| CSPR_MSEL_GPCM \
					| CSPR_V)
#define SYS_FPGA_CSPR_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
					| CSPR_PORT_SIZE_8 \
					| CSPR_MSEL_GPCM \
					| CSPR_V)

#define SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
#else
#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
#endif
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define SYS_FPGA_CS_FTIM1	(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define SYS_FPGA_CS_FTIM2	(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3	0x0

#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK2		SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
#endif
#endif

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_RETIMER_ADDR2		0x19
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH5			0xD

#define I2C_MUX_CH_VOL_MONITOR          0xA

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x63
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
#define I2C_SVDD_MONITOR_ADDR           0x4F

/* The lowest and highest voltage allowed for LS1088AQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

#define PWM_CHANNEL0                    0x0

/*
* RTC configuration
*/
#define RTC
#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0

#ifdef CONFIG_FSL_DSPI
#if !defined(CONFIG_TFABOOT) && \
	!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#endif
#endif

#define CONFIG_FSL_MEMAC

#define COMMON_ENV \
	"kernelheader_addr_r=0x80200000\0"	\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernel_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"

/* Initial environment variables */
#ifdef CONFIG_NXP_ESBC
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	COMMON_ENV				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x90100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"	\
	"sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;"	\
	"sf read 0xa0e00000 0xe00000 0x100000;"	\
	"sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"	\
	"fsl_mc start mc 0xa0a00000 0xa0e00000\0"			\
	"mcmemsize=0x70000000 \0"
#else /* if !(CONFIG_NXP_ESBC) */
#ifdef CONFIG_TFABOOT
#define QSPI_MC_INIT_CMD				\
	"sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"	\
	"sf read 0x80e00000 0xE00000 0x100000;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define SD_MC_INIT_CMD				\
	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD				\
	"fsl_mc start mc 0x580A00000 0x580E00000\0"

#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	COMMON_ENV				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x90100000\0"			\
	"kernel_addr=0x100000\0"		\
	"kernel_addr_sd=0x800\0"                \
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_start_sd=0x8000\0"              \
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernel_size_sd=0x14000\0"               \
	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"	\
	"sf read 0x80e00000 0xE00000 0x100000;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"	\
	"mcmemsize=0x70000000 \0"		\
	"BOARD=ls1088aqds\0" \
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	BOOTENV					\
	"boot_scripts=ls1088aqds_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1088aqds_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} " \
		"${scriptaddr} ${prefix}${script}; "		\
	"env exists secureboot && load ${devtype} "		\
		"${devnum}:${distro_bootpart} "			\
		"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
		"env exists secureboot "			\
		"&& esbc_validate ${scripthdraddr};"		\
		"source ${scriptaddr}\0"			\
	"qspi_bootcmd=echo Trying load from qspi..; " \
		"sf probe 0:0; " \
		"sf read 0x80001000 0xd00000 0x100000; " \
		"fsl_mc lazyapply dpl 0x80001000 && " \
		"sf read $kernel_load $kernel_start " \
		"$kernel_size && bootm $kernel_load#$BOARD\0" \
	"sd_bootcmd=echo Trying load from sd card..; " \
		"mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
		"fsl_mc lazyapply dpl 0x80001000 && " \
		"mmc read $kernel_load $kernel_start_sd " \
		"$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
	"nor_bootcmd=echo Trying load from nor..; " \
		"fsl_mc lazyapply dpl 0x580d00000 && " \
		"cp.b $kernel_start $kernel_load " \
		"$kernel_size && bootm $kernel_load#$BOARD\0"
#else
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	COMMON_ENV				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x90100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"	\
	"sf read 0x80e00000 0xE00000 0x100000;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"	\
	"mcmemsize=0x70000000 \0"
#elif defined(CONFIG_SD_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS               \
	COMMON_ENV				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x90100000\0"                 \
	"kernel_addr=0x800\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x14000\0"               \
	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"       \
	"mcmemsize=0x70000000 \0"
#else	/* NOR BOOT */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	COMMON_ENV				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x90100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"	\
	"mcmemsize=0x70000000 \0"
#endif
#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_NXP_ESBC */

#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;;"
#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
			   "env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;;"
#endif

#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define RGMII_PHY1_ADDR		0x1
#define RGMII_PHY2_ADDR		0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#endif

#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#include <asm/fsl_secure_boot.h>

#endif /* __LS1088A_QDS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
7769776a	2	/*
34f39ce8	3	* Copyright 2017, 2020-2021 NXP
7769776a AK	4	*/
	5
	6	#ifndef __LS1088A_QDS_H
	7	#define __LS1088A_QDS_H
	8
	9	#include "ls1088a_common.h"
	10
91fded62	11	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
7769776a	12	#define SYS_NO_FLASH
7769776a AK	13	#endif
7769776a AK	14
2f8a6db5	15	#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
7769776a	16
7769776a AK	17	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
7769776a AK	18	#define SPD_EEPROM_ADDRESS 0x51
7769776a AK	19
	20
	21	/*
	22	* IFC Definitions
	23	*/
	24	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	25	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	26	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	27	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	28
	29	#define CONFIG_SYS_NOR0_CSPR \
	30	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	31	CSPR_PORT_SIZE_16 \| \
	32	CSPR_MSEL_NOR \| \
	33	CSPR_V)
	34	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	35	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	36	CSPR_PORT_SIZE_16 \| \
	37	CSPR_MSEL_NOR \| \
	38	CSPR_V)
	39	#define CONFIG_SYS_NOR1_CSPR \
	40	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	41	CSPR_PORT_SIZE_16 \| \
	42	CSPR_MSEL_NOR \| \
	43	CSPR_V)
	44	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	45	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	46	CSPR_PORT_SIZE_16 \| \
	47	CSPR_MSEL_NOR \| \
	48	CSPR_V)
	49	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	50	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	51	FTIM0_NOR_TEADC(0x5) \| \
c1c597e8	52	FTIM0_NOR_TAVDS(0x6) \| \
7769776a AK	53	FTIM0_NOR_TEAHC(0x5))
7769776a AK	54	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
c1c597e8	55	FTIM1_NOR_TRAD_NOR(0x1a) \| \
7769776a	56	FTIM1_NOR_TSEQRAD_NOR(0x13))
c1c597e8 AK	57	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) \| \
	58	FTIM2_NOR_TCH(0x8) \| \
	59	FTIM2_NOR_TWPH(0xe) \| \
7769776a AK	60	FTIM2_NOR_TWP(0x1c))
	61	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	62	#define CONFIG_SYS_IFC_CCR 0x01000000
	63
	64	#ifndef SYS_NO_FLASH
7769776a AK	65	#define CONFIG_SYS_FLASH_QUIET_TEST
	66	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	67
7769776a AK	68	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	69	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	70	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	71
	72	#define CONFIG_SYS_FLASH_EMPTY_INFO
	73	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	74	CONFIG_SYS_FLASH_BASE + 0x40000000}
	75	#endif
	76	#endif
	77
7769776a AK	78	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	79	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	80
	81	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	82	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	83	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	84	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	85	\| CSPR_V)
	86	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	87
	88	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	89	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	90	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	91	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	92	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	93	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	94	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	95
7769776a AK	96	/* ONFI NAND Flash mode0 Timing Params */
	97	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	98	FTIM0_NAND_TWP(0x18) \| \
	99	FTIM0_NAND_TWCHT(0x07) \| \
	100	FTIM0_NAND_TWH(0x0a))
	101	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	102	FTIM1_NAND_TWBE(0x39) \| \
	103	FTIM1_NAND_TRR(0x0e) \| \
	104	FTIM1_NAND_TRP(0x18))
	105	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	106	FTIM2_NAND_TREH(0x0a) \| \
	107	FTIM2_NAND_TWHRE(0x1e))
	108	#define CONFIG_SYS_NAND_FTIM3 0x0
	109
	110	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	111	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	112	#define CONFIG_MTD_NAND_VERIFY_WRITE
7769776a	113
7769776a AK	114	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	115	#define QIXIS_LBMAP_SWITCH 6
	116	#define QIXIS_QMAP_MASK 0xe0
	117	#define QIXIS_QMAP_SHIFT 5
	118	#define QIXIS_LBMAP_MASK 0x0f
	119	#define QIXIS_LBMAP_SHIFT 0
	120	#define QIXIS_LBMAP_DFLTBANK 0x0e
	121	#define QIXIS_LBMAP_ALTBANK 0x2e
	122	#define QIXIS_LBMAP_SD 0x00
6c8945ec AK	123	#define QIXIS_LBMAP_EMMC 0x00
6c8945ec AK	124	#define QIXIS_LBMAP_IFC 0x00
7769776a AK	125	#define QIXIS_LBMAP_SD_QSPI 0x0e
7769776a AK	126	#define QIXIS_LBMAP_QSPI 0x0e
6c8945ec	127	#define QIXIS_RCW_SRC_IFC 0x25
7769776a	128	#define QIXIS_RCW_SRC_SD 0x40
6c8945ec	129	#define QIXIS_RCW_SRC_EMMC 0x41
7769776a AK	130	#define QIXIS_RCW_SRC_QSPI 0x62
	131	#define QIXIS_RST_CTL_RESET 0x41
	132	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	133	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	134	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	135	#define QIXIS_RST_FORCE_MEM 0x01
	136	#define QIXIS_STAT_PRES1 0xb
	137	#define QIXIS_SDID_MASK 0x07
	138	#define QIXIS_ESDHC_NO_ADAPTER 0x7
	139
	140	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	141	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	142	\| CSPR_PORT_SIZE_8 \
	143	\| CSPR_MSEL_GPCM \
	144	\| CSPR_V)
	145	#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	146	\| CSPR_PORT_SIZE_8 \
	147	\| CSPR_MSEL_GPCM \
	148	\| CSPR_V)
	149
b555e293	150	#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
91fded62	151	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
7769776a AK	152	#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
	153	#else
	154	#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
	155	#endif
	156	/* QIXIS Timing parameters*/
	157	#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	158	FTIM0_GPCM_TEADC(0x0e) \| \
	159	FTIM0_GPCM_TEAHC(0x0e))
	160	#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	161	FTIM1_GPCM_TRAD(0x3f))
	162	#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	163	FTIM2_GPCM_TCH(0xf) \| \
	164	FTIM2_GPCM_TWP(0x3E))
	165	#define SYS_FPGA_CS_FTIM3 0x0
	166
1a12b4a0 PG	167	#ifdef CONFIG_TFABOOT
	168	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	169	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	170	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	171	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	172	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	173	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	174	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	175	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	176	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	177	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	178	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	179	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	180	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	181	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	182	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	183	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	184	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	185	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	186	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	187	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	188	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	189	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	190	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	191	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	192	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	193	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	194	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	195	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	196	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	197	#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
	198	#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
	199	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	200	#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
	201	#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
	202	#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
	203	#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
	204	#else
7769776a AK	205	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	206	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	207	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	208	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	209	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	210	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	211	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	212	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	213	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	214	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
	215	#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
	216	#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
b555e293	217	#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
7769776a AK	218	#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
	219	#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
	220	#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
	221	#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
	222	#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
	223	#else
	224	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	225	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	226	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	227	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	228	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	229	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	230	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	231	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	232	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	233	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	234	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	235	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	236	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	237	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	238	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	239	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	240	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	241	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	242	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	243	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	244	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	245	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	246	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	247	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	248	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	249	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	250	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	251	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	252	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
b555e293 AK	253	#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
b555e293 AK	254	#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
7769776a	255	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
b555e293 AK	256	#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
	257	#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
	258	#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
	259	#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
7769776a	260	#endif
1a12b4a0	261	#endif
7769776a AK	262
	263	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
	264
	265	/*
	266	* I2C bus multiplexer
	267	*/
	268	#define I2C_MUX_PCA_ADDR_PRI 0x77
	269	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
	270	#define I2C_RETIMER_ADDR 0x18
	271	#define I2C_RETIMER_ADDR2 0x19
	272	#define I2C_MUX_CH_DEFAULT 0x8
	273	#define I2C_MUX_CH5 0xD
	274
23a12cb3 RB	275	#define I2C_MUX_CH_VOL_MONITOR 0xA
	276
	277	/* Voltage monitor on channel 2*/
	278	#define I2C_VOL_MONITOR_ADDR 0x63
	279	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	280	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	281	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
ef0789b7 RB	282	#define I2C_SVDD_MONITOR_ADDR 0x4F
ef0789b7 RB	283
ef0789b7 RB	284	/* The lowest and highest voltage allowed for LS1088AQDS */
	285	#define VDD_MV_MIN 819
	286	#define VDD_MV_MAX 1212
	287
23a12cb3 RB	288	#define PWM_CHANNEL0 0x0
23a12cb3 RB	289
7769776a AK	290	/*
	291	* RTC configuration
	292	*/
	293	#define RTC
7769776a	294	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
7769776a AK	295
7769776a AK	296	/* EEPROM */
7769776a AK	297	#define CONFIG_SYS_I2C_EEPROM_NXID
7769776a AK	298	#define CONFIG_SYS_EEPROM_BUS_NUM 0
7769776a	299
7769776a	300	#ifdef CONFIG_FSL_DSPI
1a12b4a0 PG	301	#if !defined(CONFIG_TFABOOT) && \
1a12b4a0 PG	302	!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
7769776a AK	303	#endif
	304	#endif
	305
7769776a AK	306	#define CONFIG_FSL_MEMAC
7769776a AK	307
166e40bd BL	308	#define COMMON_ENV \
	309	"kernelheader_addr_r=0x80200000\0" \
	310	"fdtheader_addr_r=0x80100000\0" \
	311	"kernel_addr_r=0x81000000\0" \
	312	"fdt_addr_r=0x90000000\0" \
	313	"load_addr=0xa0000000\0"
	314
7769776a	315	/* Initial environment variables */
5536c3c9	316	#ifdef CONFIG_NXP_ESBC
30c41d21 UA	317	#undef CONFIG_EXTRA_ENV_SETTINGS
30c41d21 UA	318	#define CONFIG_EXTRA_ENV_SETTINGS \
166e40bd	319	COMMON_ENV \
30c41d21 UA	320	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	321	"loadaddr=0x90100000\0" \
	322	"kernel_addr=0x100000\0" \
	323	"ramdisk_addr=0x800000\0" \
	324	"ramdisk_size=0x2000000\0" \
	325	"fdt_high=0xa0000000\0" \
	326	"initrd_high=0xffffffffffffffff\0" \
	327	"kernel_start=0x1000000\0" \
	328	"kernel_load=0xa0000000\0" \
	329	"kernel_size=0x2800000\0" \
50ddea6a	330	"mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
4238e373	331	"sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
30c41d21	332	"sf read 0xa0e00000 0xe00000 0x100000;" \
4238e373	333	"sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
30c41d21 UA	334	"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
30c41d21 UA	335	"mcmemsize=0x70000000 \0"
5536c3c9	336	#else /* if !(CONFIG_NXP_ESBC) */
1a12b4a0 PG	337	#ifdef CONFIG_TFABOOT
1a12b4a0 PG	338	#define QSPI_MC_INIT_CMD \
50ddea6a PJ	339	"sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
	340	"sf read 0x80e00000 0xE00000 0x100000;" \
	341	"fsl_mc start mc 0x80a00000 0x80e00000\0"
1a12b4a0	342	#define SD_MC_INIT_CMD \
50ddea6a PJ	343	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
	344	"mmc read 0x80e00000 0x7000 0x800;" \
	345	"fsl_mc start mc 0x80a00000 0x80e00000\0"
1a12b4a0 PG	346	#define IFC_MC_INIT_CMD \
	347	"fsl_mc start mc 0x580A00000 0x580E00000\0"
	348
	349	#undef CONFIG_EXTRA_ENV_SETTINGS
	350	#define CONFIG_EXTRA_ENV_SETTINGS \
166e40bd	351	COMMON_ENV \
1a12b4a0 PG	352	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	353	"loadaddr=0x90100000\0" \
	354	"kernel_addr=0x100000\0" \
	355	"kernel_addr_sd=0x800\0" \
	356	"ramdisk_addr=0x800000\0" \
	357	"ramdisk_size=0x2000000\0" \
	358	"fdt_high=0xa0000000\0" \
	359	"initrd_high=0xffffffffffffffff\0" \
	360	"kernel_start=0x1000000\0" \
	361	"kernel_start_sd=0x8000\0" \
	362	"kernel_load=0xa0000000\0" \
	363	"kernel_size=0x2800000\0" \
	364	"kernel_size_sd=0x14000\0" \
50ddea6a PJ	365	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
	366	"sf read 0x80e00000 0xE00000 0x100000;" \
	367	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
472dfe54 BL	368	"mcmemsize=0x70000000 \0" \
	369	"BOARD=ls1088aqds\0" \
	370	"scriptaddr=0x80000000\0" \
	371	"scripthdraddr=0x80080000\0" \
	372	BOOTENV \
	373	"boot_scripts=ls1088aqds_boot.scr\0" \
	374	"boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
	375	"scan_dev_for_boot_part=" \
	376	"part list ${devtype} ${devnum} devplist; " \
	377	"env exists devplist \|\| setenv devplist 1; " \
	378	"for distro_bootpart in ${devplist}; do " \
	379	"if fstype ${devtype} " \
	380	"${devnum}:${distro_bootpart} " \
	381	"bootfstype; then " \
	382	"run scan_dev_for_boot; " \
	383	"fi; " \
	384	"done\0" \
	385	"boot_a_script=" \
	386	"load ${devtype} ${devnum}:${distro_bootpart} " \
	387	"${scriptaddr} ${prefix}${script}; " \
	388	"env exists secureboot && load ${devtype} " \
	389	"${devnum}:${distro_bootpart} " \
	390	"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
	391	"env exists secureboot " \
	392	"&& esbc_validate ${scripthdraddr};" \
	393	"source ${scriptaddr}\0" \
	394	"qspi_bootcmd=echo Trying load from qspi..; " \
	395	"sf probe 0:0; " \
	396	"sf read 0x80001000 0xd00000 0x100000; " \
	397	"fsl_mc lazyapply dpl 0x80001000 && " \
	398	"sf read $kernel_load $kernel_start " \
	399	"$kernel_size && bootm $kernel_load#$BOARD\0" \
	400	"sd_bootcmd=echo Trying load from sd card..; " \
	401	"mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
	402	"fsl_mc lazyapply dpl 0x80001000 && " \
	403	"mmc read $kernel_load $kernel_start_sd " \
	404	"$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
	405	"nor_bootcmd=echo Trying load from nor..; " \
	406	"fsl_mc lazyapply dpl 0x580d00000 && " \
	407	"cp.b $kernel_start $kernel_load " \
	408	"$kernel_size && bootm $kernel_load#$BOARD\0"
1a12b4a0	409	#else
7769776a AK	410	#if defined(CONFIG_QSPI_BOOT)
	411	#undef CONFIG_EXTRA_ENV_SETTINGS
	412	#define CONFIG_EXTRA_ENV_SETTINGS \
166e40bd	413	COMMON_ENV \
7769776a AK	414	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	415	"loadaddr=0x90100000\0" \
	416	"kernel_addr=0x100000\0" \
	417	"ramdisk_addr=0x800000\0" \
	418	"ramdisk_size=0x2000000\0" \
	419	"fdt_high=0xa0000000\0" \
	420	"initrd_high=0xffffffffffffffff\0" \
	421	"kernel_start=0x1000000\0" \
	422	"kernel_load=0xa0000000\0" \
	423	"kernel_size=0x2800000\0" \
50ddea6a PJ	424	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
	425	"sf read 0x80e00000 0xE00000 0x100000;" \
	426	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
7769776a	427	"mcmemsize=0x70000000 \0"
91fded62 AK	428	#elif defined(CONFIG_SD_BOOT)
	429	#undef CONFIG_EXTRA_ENV_SETTINGS
	430	#define CONFIG_EXTRA_ENV_SETTINGS \
166e40bd	431	COMMON_ENV \
91fded62 AK	432	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	433	"loadaddr=0x90100000\0" \
	434	"kernel_addr=0x800\0" \
	435	"ramdisk_addr=0x800000\0" \
	436	"ramdisk_size=0x2000000\0" \
	437	"fdt_high=0xa0000000\0" \
	438	"initrd_high=0xffffffffffffffff\0" \
	439	"kernel_start=0x8000\0" \
	440	"kernel_load=0xa0000000\0" \
	441	"kernel_size=0x14000\0" \
50ddea6a PJ	442	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
	443	"mmc read 0x80e00000 0x7000 0x800;" \
	444	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
91fded62	445	"mcmemsize=0x70000000 \0"
7769776a AK	446	#else /* NOR BOOT */
	447	#undef CONFIG_EXTRA_ENV_SETTINGS
	448	#define CONFIG_EXTRA_ENV_SETTINGS \
166e40bd	449	COMMON_ENV \
7769776a AK	450	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	451	"loadaddr=0x90100000\0" \
	452	"kernel_addr=0x100000\0" \
	453	"ramdisk_addr=0x800000\0" \
	454	"ramdisk_size=0x2000000\0" \
	455	"fdt_high=0xa0000000\0" \
	456	"initrd_high=0xffffffffffffffff\0" \
	457	"kernel_start=0x1000000\0" \
	458	"kernel_load=0xa0000000\0" \
	459	"kernel_size=0x2800000\0" \
	460	"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
	461	"mcmemsize=0x70000000 \0"
	462	#endif
1a12b4a0	463	#endif /* CONFIG_TFABOOT */
5536c3c9	464	#endif /* CONFIG_NXP_ESBC */
7769776a	465
472dfe54 BL	466	#ifdef CONFIG_TFABOOT
	467	#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
	468	"env exists secureboot && esbc_halt;;"
	469	#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
	470	"env exists secureboot && esbc_halt;;"
	471	#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
	472	"env exists secureboot && esbc_halt;;"
	473	#endif
	474
7769776a AK	475	#ifdef CONFIG_FSL_MC_ENET
7769776a AK	476	#define CONFIG_FSL_MEMAC
7769776a AK	477	#define RGMII_PHY1_ADDR 0x1
	478	#define RGMII_PHY2_ADDR 0x2
	479	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	480	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	481	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	482	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	483
	484	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	485	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	486	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	487	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	488	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	489	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	490	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	491	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	492	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	493	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	494	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	495	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	496	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	497	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	498	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	499	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	500
7769776a AK	501	#endif
7769776a AK	502
7769776a AK	503	#define BOOT_TARGET_DEVICES(func) \
	504	func(USB, usb, 0) \
	505	func(MMC, mmc, 0) \
	506	func(SCSI, scsi, 0) \
	507	func(DHCP, dhcp, na)
	508	#include <config_distro_bootcmd.h>
	509
	510	#include <asm/fsl_secure_boot.h>
	511
	512	#endif /* __LS1088A_QDS_H */